Patchwork powerpc: Decode correct MSR bits in oops output

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Submitter Anton Blanchard
Date Nov. 25, 2011, 5:35 a.m.
Message ID <20111125163557.5a464006@kryten>
Download mbox | patch
Permalink /patch/127643/
State Accepted
Commit 3bfd0c9c8f9cd2c09cf3e5376c7113eec3370ebd
Headers show

Comments

Anton Blanchard - Nov. 25, 2011, 5:35 a.m.
On a 64bit book3s machine I have an oops from a system reset that
claims the book3e CE bit was set:

MSR: 8000000000021032 <ME,CE,IR,DR>  CR: 24004082  XER: 00000010

On a book3s machine system reset sets IBM bit 46 and 47 depending on
the power saving mode. Separate the definitions by type and for
completeness add the rest of the bits in.

Signed-off-by: Anton Blanchard <anton@samba.org>
---
Kumar Gala - Nov. 28, 2011, 4:04 p.m.
On Nov 24, 2011, at 11:35 PM, Anton Blanchard wrote:

> 
> On a 64bit book3s machine I have an oops from a system reset that
> claims the book3e CE bit was set:
> 
> MSR: 8000000000021032 <ME,CE,IR,DR>  CR: 24004082  XER: 00000010
> 
> On a book3s machine system reset sets IBM bit 46 and 47 depending on
> the power saving mode. Separate the definitions by type and for
> completeness add the rest of the bits in.
> 
> Signed-off-by: Anton Blanchard <anton@samba.org>
> ---
> 
> Index: linux-build/arch/powerpc/kernel/process.c
> ===================================================================
> --- linux-build.orig/arch/powerpc/kernel/process.c	2011-11-25 13:22:24.294919094 +1100
> +++ linux-build/arch/powerpc/kernel/process.c	2011-11-25 13:36:23.213834524 +1100
> @@ -584,16 +584,32 @@ static struct regbit {
> 	unsigned long bit;
> 	const char *name;
> } msr_bits[] = {
> +#if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE)
> +	{MSR_SF,	"SF"},
> +	{MSR_HV,	"HV"},
> +#endif
> +	{MSR_VEC,	"VEC"},
> +	{MSR_VSX,	"VSX"},
> +#ifdef CONFIG_BOOKE
> +	{MSR_CE,	"CE"},
> +#endif
> 	{MSR_EE,	"EE"},
> 	{MSR_PR,	"PR"},
> 	{MSR_FP,	"FP"},
> -	{MSR_VEC,	"VEC"},
> -	{MSR_VSX,	"VSX"},
> 	{MSR_ME,	"ME"},
> -	{MSR_CE,	"CE"},
> +#ifdef CONFIG_BOOKE
> 	{MSR_DE,	"DE"},
> +#else
> +	{MSR_SE,	"SE"},
> +	{MSR_BE,	"BE"},
> +#endif
> 	{MSR_IR,	"IR"},
> 	{MSR_DR,	"DR"},
> +	{MSR_PMM,	"PMM"},
> +#ifndef CONFIG_BOOKE
> +	{MSR_RI,	"RI"},

We have 'RI' on some BOOKE so lets allow for it to be decoded

> +	{MSR_LE,	"LE"},
> +#endif
> 	{0,		NULL}
> };

Since you're fixing this can you add the following for CONFIG_BOOKE:

MSR_GS, MSR_UCLE, MSR_PMM, MSR_CM

- k
Josh Boyer - Nov. 28, 2011, 4:23 p.m.
On Mon, Nov 28, 2011 at 11:04 AM, Kumar Gala <galak@kernel.crashing.org> wrote:
>
> On Nov 24, 2011, at 11:35 PM, Anton Blanchard wrote:
>
>>
>> On a 64bit book3s machine I have an oops from a system reset that
>> claims the book3e CE bit was set:
>>
>> MSR: 8000000000021032 <ME,CE,IR,DR>  CR: 24004082  XER: 00000010
>>
>> On a book3s machine system reset sets IBM bit 46 and 47 depending on
>> the power saving mode. Separate the definitions by type and for
>> completeness add the rest of the bits in.
>>
>> Signed-off-by: Anton Blanchard <anton@samba.org>
>> ---
>>
>> Index: linux-build/arch/powerpc/kernel/process.c
>> ===================================================================
>> --- linux-build.orig/arch/powerpc/kernel/process.c    2011-11-25 13:22:24.294919094 +1100
>> +++ linux-build/arch/powerpc/kernel/process.c 2011-11-25 13:36:23.213834524 +1100
>> @@ -584,16 +584,32 @@ static struct regbit {
>>       unsigned long bit;
>>       const char *name;
>> } msr_bits[] = {
>> +#if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE)
>> +     {MSR_SF,        "SF"},
>> +     {MSR_HV,        "HV"},
>> +#endif
>> +     {MSR_VEC,       "VEC"},
>> +     {MSR_VSX,       "VSX"},
>> +#ifdef CONFIG_BOOKE
>> +     {MSR_CE,        "CE"},
>> +#endif
>>       {MSR_EE,        "EE"},
>>       {MSR_PR,        "PR"},
>>       {MSR_FP,        "FP"},
>> -     {MSR_VEC,       "VEC"},
>> -     {MSR_VSX,       "VSX"},
>>       {MSR_ME,        "ME"},
>> -     {MSR_CE,        "CE"},
>> +#ifdef CONFIG_BOOKE
>>       {MSR_DE,        "DE"},
>> +#else
>> +     {MSR_SE,        "SE"},
>> +     {MSR_BE,        "BE"},
>> +#endif
>>       {MSR_IR,        "IR"},
>>       {MSR_DR,        "DR"},
>> +     {MSR_PMM,       "PMM"},
>> +#ifndef CONFIG_BOOKE
>> +     {MSR_RI,        "RI"},
>
> We have 'RI' on some BOOKE so lets allow for it to be decoded
>
>> +     {MSR_LE,        "LE"},
>> +#endif
>>       {0,             NULL}
>> };
>
> Since you're fixing this can you add the following for CONFIG_BOOKE:
>
> MSR_GS, MSR_UCLE, MSR_PMM, MSR_CM

Those don't exist on 4xx, so CONFIG_BOOKE doesn't seem appropriate.

josh
Scott Wood - Nov. 28, 2011, 7:30 p.m.
On 11/28/2011 10:23 AM, Josh Boyer wrote:
> On Mon, Nov 28, 2011 at 11:04 AM, Kumar Gala <galak@kernel.crashing.org> wrote:
>>
>> Since you're fixing this can you add the following for CONFIG_BOOKE:
>>
>> MSR_GS, MSR_UCLE, MSR_PMM, MSR_CM
> 
> Those don't exist on 4xx, so CONFIG_BOOKE doesn't seem appropriate.

They're defined by book3e of ISA 2.06.

Not all bits are going to exist on all CPUs -- does 4xx use these bits
to mean something different?

-Scott
Josh Boyer - Nov. 28, 2011, 7:46 p.m.
On Mon, Nov 28, 2011 at 2:30 PM, Scott Wood <scottwood@freescale.com> wrote:
> On 11/28/2011 10:23 AM, Josh Boyer wrote:
>> On Mon, Nov 28, 2011 at 11:04 AM, Kumar Gala <galak@kernel.crashing.org> wrote:
>>>
>>> Since you're fixing this can you add the following for CONFIG_BOOKE:
>>>
>>> MSR_GS, MSR_UCLE, MSR_PMM, MSR_CM
>>
>> Those don't exist on 4xx, so CONFIG_BOOKE doesn't seem appropriate.
>
> They're defined by book3e of ISA 2.06.

4xx existed before that, sadly (as did CONFIG_BOOKE).

> Not all bits are going to exist on all CPUs -- does 4xx use these bits
> to mean something different?

No, marked as reserved.  However, given the patch shows up in human
readable output, I don't think we want reserved bits being decoded and
showing up inadvertently.

Could introduce BOOK3E_32 to cover cases like this.

josh
Scott Wood - Nov. 28, 2011, 8:04 p.m.
On 11/28/2011 01:46 PM, Josh Boyer wrote:
> On Mon, Nov 28, 2011 at 2:30 PM, Scott Wood <scottwood@freescale.com> wrote:
>> On 11/28/2011 10:23 AM, Josh Boyer wrote:
>>> On Mon, Nov 28, 2011 at 11:04 AM, Kumar Gala <galak@kernel.crashing.org> wrote:
>>>>
>>>> Since you're fixing this can you add the following for CONFIG_BOOKE:
>>>>
>>>> MSR_GS, MSR_UCLE, MSR_PMM, MSR_CM

PMM is not just BookE, and is already present in the patch.

RI is present on e500mc (despite being reserved in book3e), so might not
want to stick that inside #ifndef CONFIG_BOOKE.

>> Not all bits are going to exist on all CPUs -- does 4xx use these bits
>> to mean something different?
> 
> No, marked as reserved.  However, given the patch shows up in human
> readable output, I don't think we want reserved bits being decoded and
> showing up inadvertently.

Do the bits ever actually get set on 4xx (documented or otherwise), or
is this a theoretical concern?

If 4xx must be excluded, use something like:
#if defined(CONFIG_BOOKE) && !defined(CONFIG_4xx)

Do we also need to patch out things like MSR_VEC at runtime, in case it
randomly shows up on a pre-Altivec CPU?

> Could introduce BOOK3E_32 to cover cases like this.

Why _32?  These bits apply to 64-bit as well.  MSR_CM is only for 64-bit.

UCLE and PMM are present on pre-2.06 e500 cores as well.

-Scott
Josh Boyer - Nov. 28, 2011, 8:12 p.m.
On Mon, Nov 28, 2011 at 3:04 PM, Scott Wood <scottwood@freescale.com> wrote:
> On 11/28/2011 01:46 PM, Josh Boyer wrote:
>> On Mon, Nov 28, 2011 at 2:30 PM, Scott Wood <scottwood@freescale.com> wrote:
>>> On 11/28/2011 10:23 AM, Josh Boyer wrote:
>>>> On Mon, Nov 28, 2011 at 11:04 AM, Kumar Gala <galak@kernel.crashing.org> wrote:
>>>>>
>>>>> Since you're fixing this can you add the following for CONFIG_BOOKE:
>>>>>
>>>>> MSR_GS, MSR_UCLE, MSR_PMM, MSR_CM
>
> PMM is not just BookE, and is already present in the patch.
>
> RI is present on e500mc (despite being reserved in book3e), so might not
> want to stick that inside #ifndef CONFIG_BOOKE.
>
>>> Not all bits are going to exist on all CPUs -- does 4xx use these bits
>>> to mean something different?
>>
>> No, marked as reserved.  However, given the patch shows up in human
>> readable output, I don't think we want reserved bits being decoded and
>> showing up inadvertently.
>
> Do the bits ever actually get set on 4xx (documented or otherwise), or
> is this a theoretical concern?
>
> If 4xx must be excluded, use something like:
> #if defined(CONFIG_BOOKE) && !defined(CONFIG_4xx)

I was going for something a bit simpler.  Basically, CONFIG_BOOKE
should be treated as a legacy Kconfig variable that has nothing to do
with ISA 2.06 because it existed before that and is used by things
that aren't compliant with 2.06 (both FSL and 4xx).  If we use it for
things that show up on these non-compliant CPUs, we'll have to
continually add the !defined(WHATEVER) and that just gets ugly over
time.

> Do we also need to patch out things like MSR_VEC at runtime, in case it
> randomly shows up on a pre-Altivec CPU?
>
>> Could introduce BOOK3E_32 to cover cases like this.
>
> Why _32?  These bits apply to 64-bit as well.  MSR_CM is only for 64-bit.

Because CONFIG_BOOK3E depeonds on PPC_BOOK3E_64.  So either that
dependency needs to go so it's selectable elsewhere, or a similarly
intended PPC_BOOK3E_32 needs to get created.  Or something.

> UCLE and PMM are present on pre-2.06 e500 cores as well.

Sigh.  Maybe there is no way to get un-ugly.

josh
Scott Wood - Nov. 28, 2011, 8:32 p.m.
On 11/28/2011 02:12 PM, Josh Boyer wrote:
> On Mon, Nov 28, 2011 at 3:04 PM, Scott Wood <scottwood@freescale.com> wrote:
>> On 11/28/2011 01:46 PM, Josh Boyer wrote:
>>> Could introduce BOOK3E_32 to cover cases like this.
>>
>> Why _32?  These bits apply to 64-bit as well.  MSR_CM is only for 64-bit.
> 
> Because CONFIG_BOOK3E depeonds on PPC_BOOK3E_64.  So either that
> dependency needs to go so it's selectable elsewhere, or a similarly
> intended PPC_BOOK3E_32 needs to get created.  Or something.

I think that dependency should go, in any case.  We already have
PPC_BOOK3E_64 for places that need to depend on that, and we don't want
to end up having this all over the place:

#if defined(CONFIG_PPC_BOOK3E_32) || defined(CONFIG_PPC_BOOK3E_64)

>> UCLE and PMM are present on pre-2.06 e500 cores as well.
> 
> Sigh.  Maybe there is no way to get un-ugly.

If we drop the 64-bit dependency, we could do this for UCLE if it really
needs to be omitted from a 4xx kernel:

#if defined(CONFIG_PPC_BOOK3E) || defined(CONFIG_E500)

PMM is not just a BookE thing, so if 4xx really needs to exclude it,
#ifndef CONFIG_4xx is the way to go.

I wouldn't bother unless 4xx is known to set these bits, though.

For GS and CM CONFIG_PPC_BOOK3E is OK, once 32-bit e500mc/e5500 kernels
start selecting it.

-Scott
Benjamin Herrenschmidt - Nov. 28, 2011, 8:40 p.m.
On Mon, 2011-11-28 at 10:04 -0600, Kumar Gala wrote:

> > +#ifndef CONFIG_BOOKE
> > +	{MSR_RI,	"RI"},
> 
> We have 'RI' on some BOOKE so lets allow for it to be decoded
> 
> > +	{MSR_LE,	"LE"},
> > +#endif
> > 	{0,		NULL}
> > };
> 
> Since you're fixing this can you add the following for CONFIG_BOOKE:
> 
> MSR_GS, MSR_UCLE, MSR_PMM, MSR_CM

Please send a followup patch.

Cheers,
Ben.

Patch

Index: linux-build/arch/powerpc/kernel/process.c
===================================================================
--- linux-build.orig/arch/powerpc/kernel/process.c	2011-11-25 13:22:24.294919094 +1100
+++ linux-build/arch/powerpc/kernel/process.c	2011-11-25 13:36:23.213834524 +1100
@@ -584,16 +584,32 @@  static struct regbit {
 	unsigned long bit;
 	const char *name;
 } msr_bits[] = {
+#if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE)
+	{MSR_SF,	"SF"},
+	{MSR_HV,	"HV"},
+#endif
+	{MSR_VEC,	"VEC"},
+	{MSR_VSX,	"VSX"},
+#ifdef CONFIG_BOOKE
+	{MSR_CE,	"CE"},
+#endif
 	{MSR_EE,	"EE"},
 	{MSR_PR,	"PR"},
 	{MSR_FP,	"FP"},
-	{MSR_VEC,	"VEC"},
-	{MSR_VSX,	"VSX"},
 	{MSR_ME,	"ME"},
-	{MSR_CE,	"CE"},
+#ifdef CONFIG_BOOKE
 	{MSR_DE,	"DE"},
+#else
+	{MSR_SE,	"SE"},
+	{MSR_BE,	"BE"},
+#endif
 	{MSR_IR,	"IR"},
 	{MSR_DR,	"DR"},
+	{MSR_PMM,	"PMM"},
+#ifndef CONFIG_BOOKE
+	{MSR_RI,	"RI"},
+	{MSR_LE,	"LE"},
+#endif
 	{0,		NULL}
 };