Patchwork [U-Boot,04/11] MIPS: add register definition for EBase register

login
register
mail settings
Submitter Daniel Schwierzeck
Date Nov. 24, 2011, 1:57 p.m.
Message ID <1322143076-20349-5-git-send-email-daniel.schwierzeck@googlemail.com>
Download mbox | patch
Permalink /patch/127520/
State Superseded
Delegated to: Marek Vasut
Headers show

Comments

Daniel Schwierzeck - Nov. 24, 2011, 1:57 p.m.
The CPUNum field in the Ebase register contains an unique identifier
for each CPU. This helps to distinguish between CPU cores in
multi-processor systems.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
---
 arch/mips/include/asm/mipsregs.h |   13 +++++++++++++
 1 files changed, 13 insertions(+), 0 deletions(-)
Marek Vasut - Nov. 25, 2011, 8:43 a.m.
> The CPUNum field in the Ebase register contains an unique identifier
> for each CPU. This helps to distinguish between CPU cores in
> multi-processor systems.
> 
> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
> ---
>  arch/mips/include/asm/mipsregs.h |   13 +++++++++++++
>  1 files changed, 13 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/mips/include/asm/mipsregs.h
> b/arch/mips/include/asm/mipsregs.h index be7e5c6..15a9fd5 100644
> --- a/arch/mips/include/asm/mipsregs.h
> +++ b/arch/mips/include/asm/mipsregs.h
> @@ -89,6 +89,13 @@
>  #define CP0_DWATCH $19
> 
>  /*
> + * Additional Coprocessor 0 register names.
> + * These registers are listed for completeness and are intended
> + * for usage in assembly code.
> + */
> +#define CP0_EBASE $15,1
> +
> +/*
>   * Coprocessor 0 Set 1 register names
>   */
>  #define CP0_S1_DERRADDR0  $26
> @@ -395,6 +402,12 @@
>  #define  CAUSEF_BD		(_ULCAST_(1)   << 31)
> 
>  /*
> + * Bits in the coprocessor 0 EBase register.
> + */
> +#define EBASEB_CPUNUM		0
> +#define EBASEF_CPUNUM		(_ULCAST_(1023))

What's this? Isn't the maximum CPU number on MIPS 32 CPUs? Or maybe that's only 
4kc limit?

> +
> +/*
>   * Bits in the coprocessor 0 config register.
>   */
>  /* Generic bits.  */

M
Daniel Schwierzeck - Nov. 25, 2011, 12:10 p.m.
On Fri, Nov 25, 2011 at 9:43 AM, Marek Vasut <marek.vasut@gmail.com> wrote:
>> The CPUNum field in the Ebase register contains an unique identifier
>> for each CPU. This helps to distinguish between CPU cores in
>> multi-processor systems.
>>
>> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
>> ---
>>  arch/mips/include/asm/mipsregs.h |   13 +++++++++++++
>>  1 files changed, 13 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/mips/include/asm/mipsregs.h
>> b/arch/mips/include/asm/mipsregs.h index be7e5c6..15a9fd5 100644
>> --- a/arch/mips/include/asm/mipsregs.h
>> +++ b/arch/mips/include/asm/mipsregs.h
>> @@ -89,6 +89,13 @@
>>  #define CP0_DWATCH $19
>>
>>  /*
>> + * Additional Coprocessor 0 register names.
>> + * These registers are listed for completeness and are intended
>> + * for usage in assembly code.
>> + */
>> +#define CP0_EBASE $15,1
>> +
>> +/*
>>   * Coprocessor 0 Set 1 register names
>>   */
>>  #define CP0_S1_DERRADDR0  $26
>> @@ -395,6 +402,12 @@
>>  #define  CAUSEF_BD           (_ULCAST_(1)   << 31)
>>
>>  /*
>> + * Bits in the coprocessor 0 EBase register.
>> + */
>> +#define EBASEB_CPUNUM                0
>> +#define EBASEF_CPUNUM                (_ULCAST_(1023))
>
> What's this? Isn't the maximum CPU number on MIPS 32 CPUs? Or maybe that's only
> 4kc limit?
>

that is only the bit shift and bit mask for the CPUNum[9:0] field in
the EBase Register.

CPUNum = (EBASE & EBASEF_CPUNUM) >> EBASEB_CPUNUM

Patch

diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index be7e5c6..15a9fd5 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -89,6 +89,13 @@ 
 #define CP0_DWATCH $19
 
 /*
+ * Additional Coprocessor 0 register names.
+ * These registers are listed for completeness and are intended
+ * for usage in assembly code.
+ */
+#define CP0_EBASE $15,1
+
+/*
  * Coprocessor 0 Set 1 register names
  */
 #define CP0_S1_DERRADDR0  $26
@@ -395,6 +402,12 @@ 
 #define  CAUSEF_BD		(_ULCAST_(1)   << 31)
 
 /*
+ * Bits in the coprocessor 0 EBase register.
+ */
+#define EBASEB_CPUNUM		0
+#define EBASEF_CPUNUM		(_ULCAST_(1023))
+
+/*
  * Bits in the coprocessor 0 config register.
  */
 /* Generic bits.  */