Patchwork [U-Boot,06/11] MIPS: make cache operation mode configurable in dcache_enable()

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Submitter Daniel Schwierzeck
Date Nov. 24, 2011, 1:57 p.m.
Message ID <1322143076-20349-7-git-send-email-daniel.schwierzeck@googlemail.com>
Download mbox | patch
Permalink /patch/127519/
State Accepted
Commit 979cfeaf36bf8719d4a1a98f1e8a3e16ef3d1fba
Delegated to: Marek Vasut
Headers show

Comments

Daniel Schwierzeck - Nov. 24, 2011, 1:57 p.m.
Commit ab2a98b11716364bc5a8c43cdfa7fee176cda1d8 missed to
use the new config option in dcache_enable().

Fix this to avoid inconsistencies if someone wants to disable
and enable D-caches.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
---
 arch/mips/cpu/mips32/cache.S |    6 +++++-
 1 files changed, 5 insertions(+), 1 deletions(-)
Marek Vasut - Nov. 25, 2011, 8:45 a.m.
> Commit ab2a98b11716364bc5a8c43cdfa7fee176cda1d8 missed to
> use the new config option in dcache_enable().
> 
> Fix this to avoid inconsistencies if someone wants to disable
> and enable D-caches.
> 
> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
> ---
>  arch/mips/cpu/mips32/cache.S |    6 +++++-
>  1 files changed, 5 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/mips/cpu/mips32/cache.S b/arch/mips/cpu/mips32/cache.S
> index 5ce0ec4..e683e8b 100644
> --- a/arch/mips/cpu/mips32/cache.S
> +++ b/arch/mips/cpu/mips32/cache.S
> @@ -30,6 +30,10 @@
>  #include <asm/addrspace.h>
>  #include <asm/cacheops.h>
> 
> +#ifndef CONFIG_SYS_MIPS_CACHE_MODE
> +#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
> +#endif
> +
>  #define RA		t8
> 
>  /*
> @@ -224,7 +228,7 @@ LEAF(dcache_enable)
>  	mfc0	t0, CP0_CONFIG
>  	ori	t0, CONF_CM_CMASK
>  	xori	t0, CONF_CM_CMASK
> -	ori	t0, CONF_CM_CACHABLE_NONCOHERENT
> +	ori	t0, CONFIG_SYS_MIPS_CACHE_MODE
>  	mtc0	t0, CP0_CONFIG
>  	jr	ra
>  	END(dcache_enable)

Acked-by: Marek Vasut <marek.vasut@gmail.com>

Patch

diff --git a/arch/mips/cpu/mips32/cache.S b/arch/mips/cpu/mips32/cache.S
index 5ce0ec4..e683e8b 100644
--- a/arch/mips/cpu/mips32/cache.S
+++ b/arch/mips/cpu/mips32/cache.S
@@ -30,6 +30,10 @@ 
 #include <asm/addrspace.h>
 #include <asm/cacheops.h>
 
+#ifndef CONFIG_SYS_MIPS_CACHE_MODE
+#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
+#endif
+
 #define RA		t8
 
 /*
@@ -224,7 +228,7 @@  LEAF(dcache_enable)
 	mfc0	t0, CP0_CONFIG
 	ori	t0, CONF_CM_CMASK
 	xori	t0, CONF_CM_CMASK
-	ori	t0, CONF_CM_CACHABLE_NONCOHERENT
+	ori	t0, CONFIG_SYS_MIPS_CACHE_MODE
 	mtc0	t0, CP0_CONFIG
 	jr	ra
 	END(dcache_enable)