Patchwork [U-Boot,10/14] tegra: usb: Add support for USB peripheral

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Submitter Simon Glass
Date Nov. 24, 2011, 3:54 a.m.
Message ID <1322106896-23054-11-git-send-email-sjg@chromium.org>
Download mbox | patch
Permalink /patch/127434/
State New, archived
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Comments

Simon Glass - Nov. 24, 2011, 3:54 a.m.
This adds basic support for the Tegra2 USB controller. Board files should
call board_usb_init() to set things up.

Configuration through FDT and CONFIG is supported. For FDT, the device
tree aliases set the order of the port, like this fragment:

        aliases {
		/* This defines the order of our USB ports */
                usb0 = "/usb@0xc5008000";
                usb1 = "/usb@0xc5000000";
        };

For CONFIG-based configuration, where CONFIG_OF_CONTROL is not defined,
USB ports rely on CONFIG_TEGRA2_USBx macros to select the ordering.
For example:

	#define CONFIG_TEGRA_USB0	TEGRA_USB3_BASE
	#define CONFIG_TEGRA_USB1	TEGRA_USB1_BASE

We record the order that the ports are configured and use that to select
ports by number.

Signed-off-by: Simon Glass <sjg@chromium.org>
---
 arch/arm/cpu/armv7/tegra2/Makefile        |    4 +-
 arch/arm/cpu/armv7/tegra2/usb.c           |  494 +++++++++++++++++++++++++++++
 arch/arm/include/asm/arch-tegra2/tegra2.h |    2 +
 arch/arm/include/asm/arch-tegra2/usb.h    |  255 +++++++++++++++
 drivers/usb/host/Makefile                 |    1 +
 drivers/usb/host/ehci-tegra.c             |   63 ++++
 include/fdtdec.h                          |    1 +
 lib/fdtdec.c                              |    1 +
 8 files changed, 820 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/tegra2/usb.c
 create mode 100644 arch/arm/include/asm/arch-tegra2/usb.h
 create mode 100644 drivers/usb/host/ehci-tegra.c
Stephen Warren - Nov. 28, 2011, 7:21 p.m.
On 11/23/2011 08:54 PM, Simon Glass wrote:
> This adds basic support for the Tegra2 USB controller. Board files should
> call board_usb_init() to set things up.

Just a very brief review:

> +/* Put the port into host mode (this only works for USB1) */
> +static void set_host_mode(struct usb_ctlr *usbctlr)
> +{
> +       /* Check whether remote host from USB1 is driving VBus */
> +       if (readl(&usbctlr->phy_vbus_sensors) & VBUS_VLD_STS)
> +               return;
> +
> +       /*
> +        * If not driving, we set GPIO USB1_VBus_En. Seaboard platform uses
> +        * PAD SLXK (GPIO D.00) as USB1_VBus_En Config as GPIO
> +        */
> +       gpio_direction_output(GPIO_PD0, 1);

The GPIO to use here needs to be parameterized; there's no reason to
believe it'll be the same on all boards (or even that boards will have
any such GPIO).

> +/* Put our ports into host mode */
> +void usb_set_host_mode(void)
> +{
> +       if (host_dev_ctlr)
> +               set_host_mode(host_dev_ctlr);
> +}

Why not just call set_host_mode() directly from board_usb_init()?

> +#ifndef CONFIG_OF_CONTROL
> +static int probe_port(struct usb_ctlr *usbctlr, const int params[])
> +{
> +       enum periph_id id;
> +       int utmi = 0;
> +
> +       /*
> +        * Get the periph id. Port 1 has an internal transceiver, port 3 is
> +        * external
> +        */
> +       switch ((u32)usbctlr) {
> +       case TEGRA_USB1_BASE:
> +               id = PERIPH_ID_USBD;
> +               break;
> +
> +       case TEGRA_USB3_BASE:
> +               id = PERIPH_ID_USB3;
> +               utmi = 1;
> +               break;
> +
> +       default:
> +               printf("tegrausb: probe_port: no such port %p\n", usbctlr);
> +               return -1;
> +       }

What about the other port (USB2)?

> +#ifdef CONFIG_OF_CONTROL
> +int fdt_decode_usb(const void *blob, int node, unsigned osc_frequency_mhz,
> +                  struct fdt_usb *config)
> +{
> +       int clk_node = 0, rate;
> +
> +       /* Find the parameters for our oscillator frequency */
> +       do {
> +               clk_node = fdt_node_offset_by_compatible(blob, clk_node,
> +                                       "nvidia,tegra20-usbparams");
> +               if (clk_node < 0) {
> +                       debug("Cannot find USB params for clock %u",
> +                             osc_frequency_mhz);
> +                       return -FDT_ERR_NOTFOUND;
> +               }
> +               rate = fdtdec_get_int(blob, clk_node, "osc-frequency", 0);
> +       } while (rate != osc_frequency_mhz);
> +
> +       config->reg = (struct usb_ctlr *)fdtdec_get_addr(blob, node, "reg");
> +       config->host_mode = fdtdec_get_bool(blob, node, "support-host-mode");

Property "support-host-mode" isn't something that's supported by the
kernel binding, and needs discussion/ack there.

> +       config->utmi = fdtdec_lookup_phandle(blob, node, "utmi") >= 0;

In the kernel DT binding, this is property "phy_type" with legal values
"utmi" or "ulpi."

> +       config->enabled = fdtdec_get_is_enabled(blob, node);
> +       config->periph_id = fdtdec_get_int(blob, node, "periph-id", -1);

periph-id is a U-Boot specific concept, not HW description. The DT
shouldn't contain that value.

> +       if (config->periph_id == -1)
> +               return -FDT_ERR_NOTFOUND;
> +
> +       return fdtdec_get_int_array(blob, clk_node, "params", config->params,
> +                       PARAM_COUNT);

Property "params" (which should probably be named something better
anyway) isn't something that's supported by the kernel binding, and
needs discussion/ack there. Instead, I suggest following the kernel's
approach for now - don't specify these PHY parameters in the binding,
but rather just apply the defaults, which are apparently suitable for
all the boards supported by the mainline kernel at least.


> +int board_usb_init(const void *blob)
> +{
> +#ifdef CONFIG_OF_CONTROL
> +       struct fdt_usb config;
> +       int clk_done = 0;
> +       int node, upto = 0;
> +       unsigned osc_freq = clock_get_rate(CLOCK_ID_OSC);
> +
> +       do {
> +               node = fdtdec_next_alias(blob, "usb",
> +                                        COMPAT_NVIDIA_TEGRA20_USB, &upto);

Why only initialize USB controllers with aliases? Surely this should
enumerate all nodes with a specific compatible flag?

> +               /* The first port we find gets to set the clocks */

Ick.

> +       /* Set up our two ports */
> +#ifdef CONFIG_TEGRA_USB1_HOST
> +       host_dev_ctlr = (struct usb_ctlr *)TEGRA_USB1_BASE;
> +#endif

That port is always the host/device switchable controller. Why not
always make that assignment? The issue here is probably that
set_host_mode() isn't suitable for all boards. The solution seems to be
to fix that.
Simon Glass - Dec. 2, 2011, 1:51 a.m.
Hi Stephen,

On Mon, Nov 28, 2011 at 11:21 AM, Stephen Warren <swarren@nvidia.com> wrote:
> On 11/23/2011 08:54 PM, Simon Glass wrote:
>> This adds basic support for the Tegra2 USB controller. Board files should
>> call board_usb_init() to set things up.
>
> Just a very brief review:

Thank you.

I will tidy up the code changes later, but just wanted to pick up on a
few general points.

>
>> +/* Put the port into host mode (this only works for USB1) */
>> +static void set_host_mode(struct usb_ctlr *usbctlr)
>> +{
>> +       /* Check whether remote host from USB1 is driving VBus */
>> +       if (readl(&usbctlr->phy_vbus_sensors) & VBUS_VLD_STS)
>> +               return;
>> +
>> +       /*
>> +        * If not driving, we set GPIO USB1_VBus_En. Seaboard platform uses
>> +        * PAD SLXK (GPIO D.00) as USB1_VBus_En Config as GPIO
>> +        */
>> +       gpio_direction_output(GPIO_PD0, 1);
>
> The GPIO to use here needs to be parameterized; there's no reason to
> believe it'll be the same on all boards (or even that boards will have
> any such GPIO).
>
>> +/* Put our ports into host mode */
>> +void usb_set_host_mode(void)
>> +{
>> +       if (host_dev_ctlr)
>> +               set_host_mode(host_dev_ctlr);
>> +}
>
> Why not just call set_host_mode() directly from board_usb_init()?
>
>> +#ifndef CONFIG_OF_CONTROL
>> +static int probe_port(struct usb_ctlr *usbctlr, const int params[])
>> +{
>> +       enum periph_id id;
>> +       int utmi = 0;
>> +
>> +       /*
>> +        * Get the periph id. Port 1 has an internal transceiver, port 3 is
>> +        * external
>> +        */
>> +       switch ((u32)usbctlr) {
>> +       case TEGRA_USB1_BASE:
>> +               id = PERIPH_ID_USBD;
>> +               break;
>> +
>> +       case TEGRA_USB3_BASE:
>> +               id = PERIPH_ID_USB3;
>> +               utmi = 1;
>> +               break;
>> +
>> +       default:
>> +               printf("tegrausb: probe_port: no such port %p\n", usbctlr);
>> +               return -1;
>> +       }
>
> What about the other port (USB2)?

Not yet supported. I don't have a board that brings it out.

>
>> +#ifdef CONFIG_OF_CONTROL
>> +int fdt_decode_usb(const void *blob, int node, unsigned osc_frequency_mhz,
>> +                  struct fdt_usb *config)
>> +{
>> +       int clk_node = 0, rate;
>> +
>> +       /* Find the parameters for our oscillator frequency */
>> +       do {
>> +               clk_node = fdt_node_offset_by_compatible(blob, clk_node,
>> +                                       "nvidia,tegra20-usbparams");
>> +               if (clk_node < 0) {
>> +                       debug("Cannot find USB params for clock %u",
>> +                             osc_frequency_mhz);
>> +                       return -FDT_ERR_NOTFOUND;
>> +               }
>> +               rate = fdtdec_get_int(blob, clk_node, "osc-frequency", 0);
>> +       } while (rate != osc_frequency_mhz);
>> +
>> +       config->reg = (struct usb_ctlr *)fdtdec_get_addr(blob, node, "reg");
>> +       config->host_mode = fdtdec_get_bool(blob, node, "support-host-mode");
>
> Property "support-host-mode" isn't something that's supported by the
> kernel binding, and needs discussion/ack there.

Do you mean device-tree list? I did send the patch there. Does the
kernel have another way of knowing that this port is special?

>
>> +       config->utmi = fdtdec_lookup_phandle(blob, node, "utmi") >= 0;
>
> In the kernel DT binding, this is property "phy_type" with legal values
> "utmi" or "ulpi."
>
>> +       config->enabled = fdtdec_get_is_enabled(blob, node);
>> +       config->periph_id = fdtdec_get_int(blob, node, "periph-id", -1);
>
> periph-id is a U-Boot specific concept, not HW description. The DT
> shouldn't contain that value.

It is actually the bit position of the peripheral in the clock
registers, so arguably a hardware description. U-Boot uses this to
efficiently manage peripheral clocks, reset, pinmux, etc.

How does the kernel figure out the clock register (etc.) to use with a
particular peripheral? Also bear in mind that the intent with U-Boot
is to be a lot more lightweight with these things.

>
>> +       if (config->periph_id == -1)
>> +               return -FDT_ERR_NOTFOUND;
>> +
>> +       return fdtdec_get_int_array(blob, clk_node, "params", config->params,
>> +                       PARAM_COUNT);
>
> Property "params" (which should probably be named something better
> anyway) isn't something that's supported by the kernel binding, and
> needs discussion/ack there. Instead, I suggest following the kernel's
> approach for now - don't specify these PHY parameters in the binding,
> but rather just apply the defaults, which are apparently suitable for
> all the boards supported by the mainline kernel at least.

My actual intent was that the device tree would provide options for
each oscillator frequency and the board would simply select which it
is using.  This does not fit well with out the device tree works
though - we end up having everything in there and available at
run-time, even useless data. Anyway, the oscillator frequency is
detected at run-time, so I decided to put these into the SOC
description.

Since you say these values are fixed for all boards we might as well
put them back into the code.

>
>
>> +int board_usb_init(const void *blob)
>> +{
>> +#ifdef CONFIG_OF_CONTROL
>> +       struct fdt_usb config;
>> +       int clk_done = 0;
>> +       int node, upto = 0;
>> +       unsigned osc_freq = clock_get_rate(CLOCK_ID_OSC);
>> +
>> +       do {
>> +               node = fdtdec_next_alias(blob, "usb",
>> +                                        COMPAT_NVIDIA_TEGRA20_USB, &upto);
>
> Why only initialize USB controllers with aliases? Surely this should
> enumerate all nodes with a specific compatible flag?

The aliases are (I thought) the official way that device trees specify
device ordering. No we do not enumerate things in U-Boot - there is no
device model as such. We can do this on Tegra, but still need to know
the order to use (i.e. which is port 0).

Regards,
Simon

>
>> +               /* The first port we find gets to set the clocks */
>
> Ick.
>
>> +       /* Set up our two ports */
>> +#ifdef CONFIG_TEGRA_USB1_HOST
>> +       host_dev_ctlr = (struct usb_ctlr *)TEGRA_USB1_BASE;
>> +#endif
>
> That port is always the host/device switchable controller. Why not
> always make that assignment? The issue here is probably that
> set_host_mode() isn't suitable for all boards. The solution seems to be
> to fix that.
>
> --
> nvpublic
>
Stephen Warren - Dec. 2, 2011, 4:10 p.m.
On 12/01/2011 06:51 PM, Simon Glass wrote:
> Hi Stephen,
> 
> On Mon, Nov 28, 2011 at 11:21 AM, Stephen Warren <swarren@nvidia.com> wrote:
>> On 11/23/2011 08:54 PM, Simon Glass wrote:
>>> This adds basic support for the Tegra2 USB controller. Board files should
>>> call board_usb_init() to set things up.

>>> +#ifdef CONFIG_OF_CONTROL
>>> +int fdt_decode_usb(const void *blob, int node, unsigned osc_frequency_mhz,
>>> +                  struct fdt_usb *config)
>>> +{
>>> +       int clk_node = 0, rate;
>>> +
>>> +       /* Find the parameters for our oscillator frequency */
>>> +       do {
>>> +               clk_node = fdt_node_offset_by_compatible(blob, clk_node,
>>> +                                       "nvidia,tegra20-usbparams");
>>> +               if (clk_node < 0) {
>>> +                       debug("Cannot find USB params for clock %u",
>>> +                             osc_frequency_mhz);
>>> +                       return -FDT_ERR_NOTFOUND;
>>> +               }
>>> +               rate = fdtdec_get_int(blob, clk_node, "osc-frequency", 0);
>>> +       } while (rate != osc_frequency_mhz);
>>> +
>>> +       config->reg = (struct usb_ctlr *)fdtdec_get_addr(blob, node, "reg");
>>> +       config->host_mode = fdtdec_get_bool(blob, node, "support-host-mode");
>>
>> Property "support-host-mode" isn't something that's supported by the
>> kernel binding, and needs discussion/ack there.
> 
> Do you mean device-tree list? I did send the patch there.

linux-tegra and perhaps linux-usb too.

> Does the kernel have another way of knowing that this port is special?

When booted without DT, the platform data defines mode: device, host, OTG.

The current DT bindings for Tegra USB are the minimum required to get
host mode working, and don't include any representation of this, and so
host mode is assumed.

>>> +       config->utmi = fdtdec_lookup_phandle(blob, node, "utmi") >= 0;
>>
>> In the kernel DT binding, this is property "phy_type" with legal values
>> "utmi" or "ulpi."
>>
>>> +       config->enabled = fdtdec_get_is_enabled(blob, node);
>>> +       config->periph_id = fdtdec_get_int(blob, node, "periph-id", -1);
>>
>> periph-id is a U-Boot specific concept, not HW description. The DT
>> shouldn't contain that value.
> 
> It is actually the bit position of the peripheral in the clock
> registers, so arguably a hardware description. U-Boot uses this to
> efficiently manage peripheral clocks, reset, pinmux, etc.
> 
> How does the kernel figure out the clock register (etc.) to use with a
> particular peripheral? Also bear in mind that the intent with U-Boot
> is to be a lot more lightweight with these things.

The DT binding has to be identical though; U-Boot implementation details
aren't supposed to affect the content of the DT.

Clock bindings are an area of active development. I haven't been
following the progress, but I imagine that the clock controller will
define a node per clock, and the devices that consume the clock will
refer to that node using a phandle. It's then up to the clock controller
driver to extract whatever information it needs from the clock node and
map that to an internal periph-id. It's plausible that a legitimate part
of the clock binding itself is such a periph-id field, but that should
be defined by the clock controller binding, not the peripheral binding.

>>> +       if (config->periph_id == -1)
>>> +               return -FDT_ERR_NOTFOUND;
>>> +
>>> +       return fdtdec_get_int_array(blob, clk_node, "params", config->params,
>>> +                       PARAM_COUNT);
>>
>> Property "params" (which should probably be named something better
>> anyway) isn't something that's supported by the kernel binding, and
>> needs discussion/ack there. Instead, I suggest following the kernel's
>> approach for now - don't specify these PHY parameters in the binding,
>> but rather just apply the defaults, which are apparently suitable for
>> all the boards supported by the mainline kernel at least.
> 
> My actual intent was that the device tree would provide options for
> each oscillator frequency and the board would simply select which it
> is using.  This does not fit well with out the device tree works
> though - we end up having everything in there and available at
> run-time, even useless data. Anyway, the oscillator frequency is
> detected at run-time, so I decided to put these into the SOC
> description.
> 
> Since you say these values are fixed for all boards we might as well
> put them back into the code.

The values aren't necessarily fixed for /all/ boards, they just /happen/
to be identical for all boards currently supported in the mainline
kernel. I imagine that as more boards are supported, we'll see different
sets of values in use.

>>> +int board_usb_init(const void *blob)
>>> +{
>>> +#ifdef CONFIG_OF_CONTROL
>>> +       struct fdt_usb config;
>>> +       int clk_done = 0;
>>> +       int node, upto = 0;
>>> +       unsigned osc_freq = clock_get_rate(CLOCK_ID_OSC);
>>> +
>>> +       do {
>>> +               node = fdtdec_next_alias(blob, "usb",
>>> +                                        COMPAT_NVIDIA_TEGRA20_USB, &upto);
>>
>> Why only initialize USB controllers with aliases? Surely this should
>> enumerate all nodes with a specific compatible flag?
> 
> The aliases are (I thought) the official way that device trees specify
> device ordering. No we do not enumerate things in U-Boot - there is no
> device model as such. We can do this on Tegra, but still need to know
> the order to use (i.e. which is port 0).

I don't believe the kernel uses the alias for anything at all right now.
Instead, it enumerates all nodes that match a certain compatible flag,
and instantiates a device for each one it has a driver for. I believe
this mode of operation is pretty implicit in DT itself; it's something
U-Boot should do too.

If U-boot were to operate solely based on the aliases node, it wouldn't
work at all for the .dts files currently in the kernel since there are
no aliases, and if there were aliases, might end up instantiating a
subset of devices if some devices weren't mentioned in aliases.

I believe what aliases is meant for is that once you've enumerated all
the devices, then check the aliases node in order to override the
default naming (or set up alternative names). Still, you'd have to check
with a DT expert here, since I've never done anything with the aliases node.
Simon Glass - Dec. 2, 2011, 5 p.m.
Hi Stephen,

On Fri, Dec 2, 2011 at 8:10 AM, Stephen Warren <swarren@nvidia.com> wrote:
> On 12/01/2011 06:51 PM, Simon Glass wrote:
>> Hi Stephen,
>>
>> On Mon, Nov 28, 2011 at 11:21 AM, Stephen Warren <swarren@nvidia.com> wrote:
>>> On 11/23/2011 08:54 PM, Simon Glass wrote:
>>>> This adds basic support for the Tegra2 USB controller. Board files should
>>>> call board_usb_init() to set things up.
>
>>>> +#ifdef CONFIG_OF_CONTROL
>>>> +int fdt_decode_usb(const void *blob, int node, unsigned osc_frequency_mhz,
>>>> +                  struct fdt_usb *config)
>>>> +{
>>>> +       int clk_node = 0, rate;
>>>> +
>>>> +       /* Find the parameters for our oscillator frequency */
>>>> +       do {
>>>> +               clk_node = fdt_node_offset_by_compatible(blob, clk_node,
>>>> +                                       "nvidia,tegra20-usbparams");
>>>> +               if (clk_node < 0) {
>>>> +                       debug("Cannot find USB params for clock %u",
>>>> +                             osc_frequency_mhz);
>>>> +                       return -FDT_ERR_NOTFOUND;
>>>> +               }
>>>> +               rate = fdtdec_get_int(blob, clk_node, "osc-frequency", 0);
>>>> +       } while (rate != osc_frequency_mhz);
>>>> +
>>>> +       config->reg = (struct usb_ctlr *)fdtdec_get_addr(blob, node, "reg");
>>>> +       config->host_mode = fdtdec_get_bool(blob, node, "support-host-mode");
>>>
>>> Property "support-host-mode" isn't something that's supported by the
>>> kernel binding, and needs discussion/ack there.
>>
>> Do you mean device-tree list? I did send the patch there.
>
> linux-tegra and perhaps linux-usb too.

OK

>
>> Does the kernel have another way of knowing that this port is special?
>
> When booted without DT, the platform data defines mode: device, host, OTG.
>
> The current DT bindings for Tegra USB are the minimum required to get
> host mode working, and don't include any representation of this, and so
> host mode is assumed.

OK, I will take a closer look, but may keep this in anticipation of
the kernel catching up.

>
>>>> +       config->utmi = fdtdec_lookup_phandle(blob, node, "utmi") >= 0;
>>>
>>> In the kernel DT binding, this is property "phy_type" with legal values
>>> "utmi" or "ulpi."
>>>
>>>> +       config->enabled = fdtdec_get_is_enabled(blob, node);
>>>> +       config->periph_id = fdtdec_get_int(blob, node, "periph-id", -1);
>>>
>>> periph-id is a U-Boot specific concept, not HW description. The DT
>>> shouldn't contain that value.
>>
>> It is actually the bit position of the peripheral in the clock
>> registers, so arguably a hardware description. U-Boot uses this to
>> efficiently manage peripheral clocks, reset, pinmux, etc.
>>
>> How does the kernel figure out the clock register (etc.) to use with a
>> particular peripheral? Also bear in mind that the intent with U-Boot
>> is to be a lot more lightweight with these things.
>
> The DT binding has to be identical though; U-Boot implementation details
> aren't supposed to affect the content of the DT.
>
> Clock bindings are an area of active development. I haven't been
> following the progress, but I imagine that the clock controller will
> define a node per clock, and the devices that consume the clock will
> refer to that node using a phandle. It's then up to the clock controller
> driver to extract whatever information it needs from the clock node and
> map that to an internal periph-id. It's plausible that a legitimate part
> of the clock binding itself is such a periph-id field, but that should
> be defined by the clock controller binding, not the peripheral binding.

OK, well this is an example of where I would like to run with what we
have, and adjust it later when things are finalized in the kernel.

I'm not sure about your analysis here actually. The peripherals have a
selectable source clock and their own divider from that clock, plus
they have bits for enabling their internal clock and reset. The
registers for all of these can sort-of be indexed through the
peripheral ID. I think with this model you would need to have a
separate clock node for every peripheral, with the peripheral node
pointing back to that. Perhaps that is what you mean. It means that
every peripheral has its own node and then a clock node. It probably
won't be too slow to decode.

>
>>>> +       if (config->periph_id == -1)
>>>> +               return -FDT_ERR_NOTFOUND;
>>>> +
>>>> +       return fdtdec_get_int_array(blob, clk_node, "params", config->params,
>>>> +                       PARAM_COUNT);
>>>
>>> Property "params" (which should probably be named something better
>>> anyway) isn't something that's supported by the kernel binding, and
>>> needs discussion/ack there. Instead, I suggest following the kernel's
>>> approach for now - don't specify these PHY parameters in the binding,
>>> but rather just apply the defaults, which are apparently suitable for
>>> all the boards supported by the mainline kernel at least.
>>
>> My actual intent was that the device tree would provide options for
>> each oscillator frequency and the board would simply select which it
>> is using.  This does not fit well with out the device tree works
>> though - we end up having everything in there and available at
>> run-time, even useless data. Anyway, the oscillator frequency is
>> detected at run-time, so I decided to put these into the SOC
>> description.
>>
>> Since you say these values are fixed for all boards we might as well
>> put them back into the code.
>
> The values aren't necessarily fixed for /all/ boards, they just /happen/
> to be identical for all boards currently supported in the mainline
> kernel. I imagine that as more boards are supported, we'll see different
> sets of values in use.

OK so perhaps I should keep my bindings here...

>
>>>> +int board_usb_init(const void *blob)
>>>> +{
>>>> +#ifdef CONFIG_OF_CONTROL
>>>> +       struct fdt_usb config;
>>>> +       int clk_done = 0;
>>>> +       int node, upto = 0;
>>>> +       unsigned osc_freq = clock_get_rate(CLOCK_ID_OSC);
>>>> +
>>>> +       do {
>>>> +               node = fdtdec_next_alias(blob, "usb",
>>>> +                                        COMPAT_NVIDIA_TEGRA20_USB, &upto);
>>>
>>> Why only initialize USB controllers with aliases? Surely this should
>>> enumerate all nodes with a specific compatible flag?
>>
>> The aliases are (I thought) the official way that device trees specify
>> device ordering. No we do not enumerate things in U-Boot - there is no
>> device model as such. We can do this on Tegra, but still need to know
>> the order to use (i.e. which is port 0).
>
> I don't believe the kernel uses the alias for anything at all right now.
> Instead, it enumerates all nodes that match a certain compatible flag,
> and instantiates a device for each one it has a driver for. I believe
> this mode of operation is pretty implicit in DT itself; it's something
> U-Boot should do too.

It does this at present with USB. But we want to enumerate the ports
and know which is port 0, which is port 1, etc. How does the kernel do
that?

>
> If U-boot were to operate solely based on the aliases node, it wouldn't
> work at all for the .dts files currently in the kernel since there are
> no aliases, and if there were aliases, might end up instantiating a
> subset of devices if some devices weren't mentioned in aliases.
>
> I believe what aliases is meant for is that once you've enumerated all
> the devices, then check the aliases node in order to override the
> default naming (or set up alternative names). Still, you'd have to check
> with a DT expert here, since I've never done anything with the aliases node.

I did go around this loop some time ago and my understanding was that
aliases were the correct way to enumerate ports (I originally just had
an ID in the port which is easier to decode).

Regards,
Simon

>
> --
> nvpublic
>
Stephen Warren - Dec. 2, 2011, 8:40 p.m.
On 12/02/2011 10:00 AM, Simon Glass wrote:
> On Fri, Dec 2, 2011 at 8:10 AM, Stephen Warren <swarren@nvidia.com> wrote:
>> On 12/01/2011 06:51 PM, Simon Glass wrote:
>>> On Mon, Nov 28, 2011 at 11:21 AM, Stephen Warren <swarren@nvidia.com> wrote:
>>>> On 11/23/2011 08:54 PM, Simon Glass wrote:
>>>>> This adds basic support for the Tegra2 USB controller. Board files should
>>>>> call board_usb_init() to set things up.
...
>>>>> +       config->enabled = fdtdec_get_is_enabled(blob, node);
>>>>> +       config->periph_id = fdtdec_get_int(blob, node, "periph-id", -1);
>>>>
>>>> periph-id is a U-Boot specific concept, not HW description. The DT
>>>> shouldn't contain that value.
>>>
>>> It is actually the bit position of the peripheral in the clock
>>> registers, so arguably a hardware description. U-Boot uses this to
>>> efficiently manage peripheral clocks, reset, pinmux, etc.
>>>
>>> How does the kernel figure out the clock register (etc.) to use with a
>>> particular peripheral? Also bear in mind that the intent with U-Boot
>>> is to be a lot more lightweight with these things.
>>
>> The DT binding has to be identical though; U-Boot implementation details
>> aren't supposed to affect the content of the DT.
>>
>> Clock bindings are an area of active development. I haven't been
>> following the progress, but I imagine that the clock controller will
>> define a node per clock, and the devices that consume the clock will
>> refer to that node using a phandle. It's then up to the clock controller
>> driver to extract whatever information it needs from the clock node and
>> map that to an internal periph-id. It's plausible that a legitimate part
>> of the clock binding itself is such a periph-id field, but that should
>> be defined by the clock controller binding, not the peripheral binding.
> 
> OK, well this is an example of where I would like to run with what we
> have, and adjust it later when things are finalized in the kernel.
> 
> I'm not sure about your analysis here actually. The peripherals have a
> selectable source clock and their own divider from that clock, plus
> they have bits for enabling their internal clock and reset. The
> registers for all of these can sort-of be indexed through the
> peripheral ID. I think with this model you would need to have a
> separate clock node for every peripheral, with the peripheral node
> pointing back to that. Perhaps that is what you mean. It means that
> every peripheral has its own node and then a clock node. It probably
> won't be too slow to decode.

re: the last-but-one sentence: Yes, I think that's how it'll work.

>>>>> +int board_usb_init(const void *blob)
>>>>> +{
>>>>> +#ifdef CONFIG_OF_CONTROL
>>>>> +       struct fdt_usb config;
>>>>> +       int clk_done = 0;
>>>>> +       int node, upto = 0;
>>>>> +       unsigned osc_freq = clock_get_rate(CLOCK_ID_OSC);
>>>>> +
>>>>> +       do {
>>>>> +               node = fdtdec_next_alias(blob, "usb",
>>>>> +                                        COMPAT_NVIDIA_TEGRA20_USB, &upto);
>>>>
>>>> Why only initialize USB controllers with aliases? Surely this should
>>>> enumerate all nodes with a specific compatible flag?
>>>
>>> The aliases are (I thought) the official way that device trees specify
>>> device ordering. No we do not enumerate things in U-Boot - there is no
>>> device model as such. We can do this on Tegra, but still need to know
>>> the order to use (i.e. which is port 0).
>>
>> I don't believe the kernel uses the alias for anything at all right now.
>> Instead, it enumerates all nodes that match a certain compatible flag,
>> and instantiates a device for each one it has a driver for. I believe
>> this mode of operation is pretty implicit in DT itself; it's something
>> U-Boot should do too.
> 
> It does this at present with USB. But we want to enumerate the ports
> and know which is port 0, which is port 1, etc. How does the kernel do
> that?

I don't think it cares; it just hosts a number of USB ports, and
peripherals show up on those USB ports. The numbering of the ports is
entirely arbitrary AFAIK.
Simon Glass - Dec. 2, 2011, 11:07 p.m.
Hi Stephen,

On Fri, Dec 2, 2011 at 12:40 PM, Stephen Warren <swarren@nvidia.com> wrote:
> On 12/02/2011 10:00 AM, Simon Glass wrote:
>> On Fri, Dec 2, 2011 at 8:10 AM, Stephen Warren <swarren@nvidia.com> wrote:
>>> On 12/01/2011 06:51 PM, Simon Glass wrote:
>>>> On Mon, Nov 28, 2011 at 11:21 AM, Stephen Warren <swarren@nvidia.com> wrote:
>>>>> On 11/23/2011 08:54 PM, Simon Glass wrote:
>>>>>> This adds basic support for the Tegra2 USB controller. Board files should
>>>>>> call board_usb_init() to set things up.
> ...
>>>>>> +       config->enabled = fdtdec_get_is_enabled(blob, node);
>>>>>> +       config->periph_id = fdtdec_get_int(blob, node, "periph-id", -1);
>>>>>
>>>>> periph-id is a U-Boot specific concept, not HW description. The DT
>>>>> shouldn't contain that value.
>>>>
>>>> It is actually the bit position of the peripheral in the clock
>>>> registers, so arguably a hardware description. U-Boot uses this to
>>>> efficiently manage peripheral clocks, reset, pinmux, etc.
>>>>
>>>> How does the kernel figure out the clock register (etc.) to use with a
>>>> particular peripheral? Also bear in mind that the intent with U-Boot
>>>> is to be a lot more lightweight with these things.
>>>
>>> The DT binding has to be identical though; U-Boot implementation details
>>> aren't supposed to affect the content of the DT.
>>>
>>> Clock bindings are an area of active development. I haven't been
>>> following the progress, but I imagine that the clock controller will
>>> define a node per clock, and the devices that consume the clock will
>>> refer to that node using a phandle. It's then up to the clock controller
>>> driver to extract whatever information it needs from the clock node and
>>> map that to an internal periph-id. It's plausible that a legitimate part
>>> of the clock binding itself is such a periph-id field, but that should
>>> be defined by the clock controller binding, not the peripheral binding.
>>
>> OK, well this is an example of where I would like to run with what we
>> have, and adjust it later when things are finalized in the kernel.
>>
>> I'm not sure about your analysis here actually. The peripherals have a
>> selectable source clock and their own divider from that clock, plus
>> they have bits for enabling their internal clock and reset. The
>> registers for all of these can sort-of be indexed through the
>> peripheral ID. I think with this model you would need to have a
>> separate clock node for every peripheral, with the peripheral node
>> pointing back to that. Perhaps that is what you mean. It means that
>> every peripheral has its own node and then a clock node. It probably
>> won't be too slow to decode.
>
> re: the last-but-one sentence: Yes, I think that's how it'll work.
>
>>>>>> +int board_usb_init(const void *blob)
>>>>>> +{
>>>>>> +#ifdef CONFIG_OF_CONTROL
>>>>>> +       struct fdt_usb config;
>>>>>> +       int clk_done = 0;
>>>>>> +       int node, upto = 0;
>>>>>> +       unsigned osc_freq = clock_get_rate(CLOCK_ID_OSC);
>>>>>> +
>>>>>> +       do {
>>>>>> +               node = fdtdec_next_alias(blob, "usb",
>>>>>> +                                        COMPAT_NVIDIA_TEGRA20_USB, &upto);
>>>>>
>>>>> Why only initialize USB controllers with aliases? Surely this should
>>>>> enumerate all nodes with a specific compatible flag?
>>>>
>>>> The aliases are (I thought) the official way that device trees specify
>>>> device ordering. No we do not enumerate things in U-Boot - there is no
>>>> device model as such. We can do this on Tegra, but still need to know
>>>> the order to use (i.e. which is port 0).
>>>
>>> I don't believe the kernel uses the alias for anything at all right now.
>>> Instead, it enumerates all nodes that match a certain compatible flag,
>>> and instantiates a device for each one it has a driver for. I believe
>>> this mode of operation is pretty implicit in DT itself; it's something
>>> U-Boot should do too.
>>
>> It does this at present with USB. But we want to enumerate the ports
>> and know which is port 0, which is port 1, etc. How does the kernel do
>> that?
>
> I don't think it cares; it just hosts a number of USB ports, and
> peripherals show up on those USB ports. The numbering of the ports is
> entirely arbitrary AFAIK.

OK. For the moment in U-Boot we do care, so I will leave the alias
solution in there for now. I may look later at the patch to suppose a
virtual hub on Tegra.

Regards,
Simon

>
> --
> nvpublic
>
Simon Glass - Dec. 3, 2011, 12:59 a.m.
Hi Stephen,

Here are my comments on the rest of your email.

On Mon, Nov 28, 2011 at 11:21 AM, Stephen Warren <swarren@nvidia.com> wrote:
> On 11/23/2011 08:54 PM, Simon Glass wrote:
>> This adds basic support for the Tegra2 USB controller. Board files should
>> call board_usb_init() to set things up.
>
> Just a very brief review:
>
>> +/* Put the port into host mode (this only works for USB1) */
>> +static void set_host_mode(struct usb_ctlr *usbctlr)
>> +{
>> +       /* Check whether remote host from USB1 is driving VBus */
>> +       if (readl(&usbctlr->phy_vbus_sensors) & VBUS_VLD_STS)
>> +               return;
>> +
>> +       /*
>> +        * If not driving, we set GPIO USB1_VBus_En. Seaboard platform uses
>> +        * PAD SLXK (GPIO D.00) as USB1_VBus_En Config as GPIO
>> +        */
>> +       gpio_direction_output(GPIO_PD0, 1);
>
> The GPIO to use here needs to be parameterized; there's no reason to
> believe it'll be the same on all boards (or even that boards will have
> any such GPIO).

I have done this. It is tricky since so far we have no way of setting
up the pinmux for a given GPIO. Rather than bite off that camel I have
just set up the pinmux in the board file.

>
>> +/* Put our ports into host mode */
>> +void usb_set_host_mode(void)
>> +{
>> +       if (host_dev_ctlr)
>> +               set_host_mode(host_dev_ctlr);
>> +}
>
> Why not just call set_host_mode() directly from board_usb_init()?

This function is exported, and the caller doesn't have a pointer to
the host/device-switchable port.

>
>> +#ifndef CONFIG_OF_CONTROL
>> +static int probe_port(struct usb_ctlr *usbctlr, const int params[])
>> +{
>> +       enum periph_id id;
>> +       int utmi = 0;
>> +
>> +       /*
>> +        * Get the periph id. Port 1 has an internal transceiver, port 3 is
>> +        * external
>> +        */
>> +       switch ((u32)usbctlr) {
>> +       case TEGRA_USB1_BASE:
>> +               id = PERIPH_ID_USBD;
>> +               break;
>> +
>> +       case TEGRA_USB3_BASE:
>> +               id = PERIPH_ID_USB3;
>> +               utmi = 1;
>> +               break;
>> +
>> +       default:
>> +               printf("tegrausb: probe_port: no such port %p\n", usbctlr);
>> +               return -1;
>> +       }
>
> What about the other port (USB2)?

I have removed this function.

>
>> +#ifdef CONFIG_OF_CONTROL
>> +int fdt_decode_usb(const void *blob, int node, unsigned osc_frequency_mhz,
>> +                  struct fdt_usb *config)
>> +{
>> +       int clk_node = 0, rate;
>> +
>> +       /* Find the parameters for our oscillator frequency */
>> +       do {
>> +               clk_node = fdt_node_offset_by_compatible(blob, clk_node,
>> +                                       "nvidia,tegra20-usbparams");
>> +               if (clk_node < 0) {
>> +                       debug("Cannot find USB params for clock %u",
>> +                             osc_frequency_mhz);
>> +                       return -FDT_ERR_NOTFOUND;
>> +               }
>> +               rate = fdtdec_get_int(blob, clk_node, "osc-frequency", 0);
>> +       } while (rate != osc_frequency_mhz);
>> +
>> +       config->reg = (struct usb_ctlr *)fdtdec_get_addr(blob, node, "reg");
>> +       config->host_mode = fdtdec_get_bool(blob, node, "support-host-mode");
>
> Property "support-host-mode" isn't something that's supported by the
> kernel binding, and needs discussion/ack there.

OK will await comments. The kernel bindings seem very basic at this stage.

>
>> +       config->utmi = fdtdec_lookup_phandle(blob, node, "utmi") >= 0;
>
> In the kernel DT binding, this is property "phy_type" with legal values
> "utmi" or "ulpi."

OK I have changed this.

>
>> +       config->enabled = fdtdec_get_is_enabled(blob, node);
>> +       config->periph_id = fdtdec_get_int(blob, node, "periph-id", -1);
>
> periph-id is a U-Boot specific concept, not HW description. The DT
> shouldn't contain that value.

See my previous comments as to why this is desirable. We can change
over to a clock-based approach once the kernel implements it.

>
>> +       if (config->periph_id == -1)
>> +               return -FDT_ERR_NOTFOUND;
>> +
>> +       return fdtdec_get_int_array(blob, clk_node, "params", config->params,
>> +                       PARAM_COUNT);
>
> Property "params" (which should probably be named something better
> anyway) isn't something that's supported by the kernel binding, and
> needs discussion/ack there. Instead, I suggest following the kernel's
> approach for now - don't specify these PHY parameters in the binding,
> but rather just apply the defaults, which are apparently suitable for
> all the boards supported by the mainline kernel at least.

As discussed I have changed the name but otherwise left this as is.
since you mentioned that some boards may need to change the parameters
(it seems Tegra3 is different also).

>
>
>> +int board_usb_init(const void *blob)
>> +{
>> +#ifdef CONFIG_OF_CONTROL
>> +       struct fdt_usb config;
>> +       int clk_done = 0;
>> +       int node, upto = 0;
>> +       unsigned osc_freq = clock_get_rate(CLOCK_ID_OSC);
>> +
>> +       do {
>> +               node = fdtdec_next_alias(blob, "usb",
>> +                                        COMPAT_NVIDIA_TEGRA20_USB, &upto);
>
> Why only initialize USB controllers with aliases? Surely this should
> enumerate all nodes with a specific compatible flag?

See my other comments - we want to know that port 0 is USB3 on Seaboard.

>
>> +               /* The first port we find gets to set the clocks */
>
> Ick.

Well they all uses the same params anyway. It could be refactored to
read the timing separately but it is convenient to have it in one
structure.

>
>> +       /* Set up our two ports */
>> +#ifdef CONFIG_TEGRA_USB1_HOST
>> +       host_dev_ctlr = (struct usb_ctlr *)TEGRA_USB1_BASE;
>> +#endif
>
> That port is always the host/device switchable controller. Why not
> always make that assignment? The issue here is probably that
> set_host_mode() isn't suitable for all boards. The solution seems to be
> to fix that.

I have removed this code.

Regards,
Simon

>
> --
> nvpublic
>
Stephen Warren - Dec. 5, 2011, 9:33 p.m.
On 12/02/2011 05:59 PM, Simon Glass wrote:
> Hi Stephen,
> 
> Here are my comments on the rest of your email.
> 
> On Mon, Nov 28, 2011 at 11:21 AM, Stephen Warren <swarren@nvidia.com> wrote:
>> On 11/23/2011 08:54 PM, Simon Glass wrote:
>>> This adds basic support for the Tegra2 USB controller. Board files should
>>> call board_usb_init() to set things up.

>>> +       config->enabled = fdtdec_get_is_enabled(blob, node);
>>> +       config->periph_id = fdtdec_get_int(blob, node, "periph-id", -1);
>>
>> periph-id is a U-Boot specific concept, not HW description. The DT
>> shouldn't contain that value.
> 
> See my previous comments as to why this is desirable. We can change
> over to a clock-based approach once the kernel implements it.

That will cause backwards-compatibility problems; older FDTs won't work
with newer U-Boots. We should avoid incompatible changes like this if at
all possible.

>>> +int board_usb_init(const void *blob)
>>> +{
>>> +#ifdef CONFIG_OF_CONTROL
>>> +       struct fdt_usb config;
>>> +       int clk_done = 0;
>>> +       int node, upto = 0;
>>> +       unsigned osc_freq = clock_get_rate(CLOCK_ID_OSC);
>>> +
>>> +       do {
>>> +               node = fdtdec_next_alias(blob, "usb",
>>> +                                        COMPAT_NVIDIA_TEGRA20_USB, &upto);
>>
>> Why only initialize USB controllers with aliases? Surely this should
>> enumerate all nodes with a specific compatible flag?
> 
> See my other comments - we want to know that port 0 is USB3 on Seaboard.

Why does U-Boot care? Everything should be enumerating which peripherals
happen to appear on the various USB busses, and not care which host
controller they're attached to.

(With the exception of USB port 0 being device-capable, but that should
be configured by an explicit property, not based on aliases or anything
like that)
Simon Glass - Dec. 5, 2011, 9:46 p.m.
Hi Stephen,

On Mon, Dec 5, 2011 at 1:33 PM, Stephen Warren <swarren@nvidia.com> wrote:
> On 12/02/2011 05:59 PM, Simon Glass wrote:
>> Hi Stephen,
>>
>> Here are my comments on the rest of your email.
>>
>> On Mon, Nov 28, 2011 at 11:21 AM, Stephen Warren <swarren@nvidia.com> wrote:
>>> On 11/23/2011 08:54 PM, Simon Glass wrote:
>>>> This adds basic support for the Tegra2 USB controller. Board files should
>>>> call board_usb_init() to set things up.
>
>>>> +       config->enabled = fdtdec_get_is_enabled(blob, node);
>>>> +       config->periph_id = fdtdec_get_int(blob, node, "periph-id", -1);
>>>
>>> periph-id is a U-Boot specific concept, not HW description. The DT
>>> shouldn't contain that value.
>>
>> See my previous comments as to why this is desirable. We can change
>> over to a clock-based approach once the kernel implements it.
>
> That will cause backwards-compatibility problems; older FDTs won't work
> with newer U-Boots. We should avoid incompatible changes like this if at
> all possible.

At the moment the fdts are in the U-Boot tree, so we should be able to
change them at the same time. But of course when we update the fdt  we
need to update the U-Boot code. Is there any alternative other than
doing nothing until the kernel decides everything?

>
>>>> +int board_usb_init(const void *blob)
>>>> +{
>>>> +#ifdef CONFIG_OF_CONTROL
>>>> +       struct fdt_usb config;
>>>> +       int clk_done = 0;
>>>> +       int node, upto = 0;
>>>> +       unsigned osc_freq = clock_get_rate(CLOCK_ID_OSC);
>>>> +
>>>> +       do {
>>>> +               node = fdtdec_next_alias(blob, "usb",
>>>> +                                        COMPAT_NVIDIA_TEGRA20_USB, &upto);
>>>
>>> Why only initialize USB controllers with aliases? Surely this should
>>> enumerate all nodes with a specific compatible flag?
>>
>> See my other comments - we want to know that port 0 is USB3 on Seaboard.
>
> Why does U-Boot care? Everything should be enumerating which peripherals
> happen to appear on the various USB busses, and not care which host
> controller they're attached to.

At present we do:

'usb start 0'
'usb start 1'

to select between the ports. There is a patch in the works to change
that but it hasn't gone upstream yet, or at least wasn't accepted.

There is a problem with adopting that approach in general - e.g.
*which* UART you write to has a big effect on whether the user sees
any output.

>
> (With the exception of USB port 0 being device-capable, but that should
> be configured by an explicit property, not based on aliases or anything
> like that)

Yes it is - in fact I added that property.

Regards,
Simon

>
> --
> nvpublic
Stephen Warren - Dec. 5, 2011, 10:15 p.m.
On 12/05/2011 02:46 PM, Simon Glass wrote:
> Hi Stephen,
> 
> On Mon, Dec 5, 2011 at 1:33 PM, Stephen Warren <swarren@nvidia.com> wrote:
>> On 12/02/2011 05:59 PM, Simon Glass wrote:
>>> Hi Stephen,
>>>
>>> Here are my comments on the rest of your email.
>>>
>>> On Mon, Nov 28, 2011 at 11:21 AM, Stephen Warren <swarren@nvidia.com> wrote:
>>>> On 11/23/2011 08:54 PM, Simon Glass wrote:
>>>>> This adds basic support for the Tegra2 USB controller. Board files should
>>>>> call board_usb_init() to set things up.
>>
>>>>> +       config->enabled = fdtdec_get_is_enabled(blob, node);
>>>>> +       config->periph_id = fdtdec_get_int(blob, node, "periph-id", -1);
>>>>
>>>> periph-id is a U-Boot specific concept, not HW description. The DT
>>>> shouldn't contain that value.
>>>
>>> See my previous comments as to why this is desirable. We can change
>>> over to a clock-based approach once the kernel implements it.
>>
>> That will cause backwards-compatibility problems; older FDTs won't work
>> with newer U-Boots. We should avoid incompatible changes like this if at
>> all possible.
> 
> At the moment the fdts are in the U-Boot tree, so we should be able to
> change them at the same time. But of course when we update the fdt  we
> need to update the U-Boot code. Is there any alternative other than
> doing nothing until the kernel decides everything?

You can choose not to represent these parameters in the device tree at
all, but rather hard-code the values in the driver. This is what the
kernel currently does; as luck would have it, the required values are
identical for all the boards the kernel currently supports. Once that's
all in place and working, we can work on defining a binding for those
parameters and review/implement it in both U-Boot and the kernel.

>>>>> +int board_usb_init(const void *blob)
>>>>> +{
>>>>> +#ifdef CONFIG_OF_CONTROL
>>>>> +       struct fdt_usb config;
>>>>> +       int clk_done = 0;
>>>>> +       int node, upto = 0;
>>>>> +       unsigned osc_freq = clock_get_rate(CLOCK_ID_OSC);
>>>>> +
>>>>> +       do {
>>>>> +               node = fdtdec_next_alias(blob, "usb",
>>>>> +                                        COMPAT_NVIDIA_TEGRA20_USB, &upto);
>>>>
>>>> Why only initialize USB controllers with aliases? Surely this should
>>>> enumerate all nodes with a specific compatible flag?
>>>
>>> See my other comments - we want to know that port 0 is USB3 on Seaboard.
>>
>> Why does U-Boot care? Everything should be enumerating which peripherals
>> happen to appear on the various USB busses, and not care which host
>> controller they're attached to.
> 
> At present we do:
> 
> 'usb start 0'
> 'usb start 1'
> 
> to select between the ports. There is a patch in the works to change
> that but it hasn't gone upstream yet, or at least wasn't accepted.

Can you point out the patch that changes this, and what exactly it
changes. Hopefully it removes the parameter from the "usb start" command.

I'm still not convinced why U-Boot cares about this (as opposed to the
user using U-Boot).
Simon Glass - Dec. 5, 2011, 11:35 p.m.
Hi Stephen,

On Mon, Dec 5, 2011 at 2:15 PM, Stephen Warren <swarren@nvidia.com> wrote:
> On 12/05/2011 02:46 PM, Simon Glass wrote:
>> Hi Stephen,
>>
>> On Mon, Dec 5, 2011 at 1:33 PM, Stephen Warren <swarren@nvidia.com> wrote:
>>> On 12/02/2011 05:59 PM, Simon Glass wrote:
>>>> Hi Stephen,
>>>>
>>>> Here are my comments on the rest of your email.
>>>>
>>>> On Mon, Nov 28, 2011 at 11:21 AM, Stephen Warren <swarren@nvidia.com> wrote:
>>>>> On 11/23/2011 08:54 PM, Simon Glass wrote:
>>>>>> This adds basic support for the Tegra2 USB controller. Board files should
>>>>>> call board_usb_init() to set things up.
>>>
>>>>>> +       config->enabled = fdtdec_get_is_enabled(blob, node);
>>>>>> +       config->periph_id = fdtdec_get_int(blob, node, "periph-id", -1);
>>>>>
>>>>> periph-id is a U-Boot specific concept, not HW description. The DT
>>>>> shouldn't contain that value.
>>>>
>>>> See my previous comments as to why this is desirable. We can change
>>>> over to a clock-based approach once the kernel implements it.
>>>
>>> That will cause backwards-compatibility problems; older FDTs won't work
>>> with newer U-Boots. We should avoid incompatible changes like this if at
>>> all possible.
>>
>> At the moment the fdts are in the U-Boot tree, so we should be able to
>> change them at the same time. But of course when we update the fdt  we
>> need to update the U-Boot code. Is there any alternative other than
>> doing nothing until the kernel decides everything?
>
> You can choose not to represent these parameters in the device tree at
> all, but rather hard-code the values in the driver. This is what the
> kernel currently does; as luck would have it, the required values are
> identical for all the boards the kernel currently supports. Once that's
> all in place and working, we can work on defining a binding for those
> parameters and review/implement it in both U-Boot and the kernel.

OK, but how about we have this conversation when things are actually
in the kernel and working? The scheme used in this series (peripheral
IDs) is very handy for U-Boot and avoids this hard-coding that you
refer to.

Also the only way I can see it being hard-coded is by the kernel
looking at the peripheral address and converting this to an ID. That
seems really ugly to me. Or am I missing something?

>
>>>>>> +int board_usb_init(const void *blob)
>>>>>> +{
>>>>>> +#ifdef CONFIG_OF_CONTROL
>>>>>> +       struct fdt_usb config;
>>>>>> +       int clk_done = 0;
>>>>>> +       int node, upto = 0;
>>>>>> +       unsigned osc_freq = clock_get_rate(CLOCK_ID_OSC);
>>>>>> +
>>>>>> +       do {
>>>>>> +               node = fdtdec_next_alias(blob, "usb",
>>>>>> +                                        COMPAT_NVIDIA_TEGRA20_USB, &upto);
>>>>>
>>>>> Why only initialize USB controllers with aliases? Surely this should
>>>>> enumerate all nodes with a specific compatible flag?
>>>>
>>>> See my other comments - we want to know that port 0 is USB3 on Seaboard.
>>>
>>> Why does U-Boot care? Everything should be enumerating which peripherals
>>> happen to appear on the various USB busses, and not care which host
>>> controller they're attached to.
>>
>> At present we do:
>>
>> 'usb start 0'
>> 'usb start 1'
>>
>> to select between the ports. There is a patch in the works to change
>> that but it hasn't gone upstream yet, or at least wasn't accepted.
>
> Can you point out the patch that changes this, and what exactly it
> changes. Hopefully it removes the parameter from the "usb start" command.

Yes, they are in the Chromium tree:

https://gerrit.chromium.org/gerrit/#change,4951
https://gerrit.chromium.org/gerrit/#change,4981

>
> I'm still not convinced why U-Boot cares about this (as opposed to the
> user using U-Boot).

Well if U-Boot presents the ports in the wrong order, the user's
scripts will fail.

Also, what about the console UART problem? Surely the kernel provides
a way to select the ordering of those? How do I know what UART I am
getting on /dev/ttyS0?

Regards,
Simon

>
> --
> nvpublic
Stephen Warren - Dec. 6, 2011, 12:17 a.m.
On 12/05/2011 04:35 PM, Simon Glass wrote:
> Hi Stephen,
> 
> On Mon, Dec 5, 2011 at 2:15 PM, Stephen Warren <swarren@nvidia.com> wrote:
>> On 12/05/2011 02:46 PM, Simon Glass wrote:
>>> Hi Stephen,
>>>
>>> On Mon, Dec 5, 2011 at 1:33 PM, Stephen Warren <swarren@nvidia.com> wrote:
>>>> On 12/02/2011 05:59 PM, Simon Glass wrote:
>>>>> Hi Stephen,
>>>>>
>>>>> Here are my comments on the rest of your email.
>>>>>
>>>>> On Mon, Nov 28, 2011 at 11:21 AM, Stephen Warren <swarren@nvidia.com> wrote:
>>>>>> On 11/23/2011 08:54 PM, Simon Glass wrote:
>>>>>>> This adds basic support for the Tegra2 USB controller. Board files should
>>>>>>> call board_usb_init() to set things up.
>>>>
>>>>>>> +       config->enabled = fdtdec_get_is_enabled(blob, node);
>>>>>>> +       config->periph_id = fdtdec_get_int(blob, node, "periph-id", -1);
>>>>>>
>>>>>> periph-id is a U-Boot specific concept, not HW description. The DT
>>>>>> shouldn't contain that value.
>>>>>
>>>>> See my previous comments as to why this is desirable. We can change
>>>>> over to a clock-based approach once the kernel implements it.
>>>>
>>>> That will cause backwards-compatibility problems; older FDTs won't work
>>>> with newer U-Boots. We should avoid incompatible changes like this if at
>>>> all possible.
>>>
>>> At the moment the fdts are in the U-Boot tree, so we should be able to
>>> change them at the same time. But of course when we update the fdt  we
>>> need to update the U-Boot code. Is there any alternative other than
>>> doing nothing until the kernel decides everything?
>>
>> You can choose not to represent these parameters in the device tree at
>> all, but rather hard-code the values in the driver. This is what the
>> kernel currently does; as luck would have it, the required values are
>> identical for all the boards the kernel currently supports. Once that's
>> all in place and working, we can work on defining a binding for those
>> parameters and review/implement it in both U-Boot and the kernel.
> 
> OK, but how about we have this conversation when things are actually
> in the kernel and working? The scheme used in this series (peripheral
> IDs) is very handy for U-Boot and avoids this hard-coding that you
> refer to.

I'd really like to avoid adding stuff to the .dts file when we know we
going to rip it out again ASAP. I'd prefer to incrementally enhance the
.dts bindings always moving forward, and never removing/breaking stuff
if possible.

Now you did point out that the .dts files are currently in U-Boot, so
this is slightly moot since the binding documentation, .dts file and
driver can all be rev'd in sync. However, I hope this will change soon.
Otherwise, every addition to them means changing U-Boot, the Linux
kernel, U-Boot v2, fastboot, quick boot, .....

> Also the only way I can see it being hard-coded is by the kernel
> looking at the peripheral address and converting this to an ID. That
> seems really ugly to me. Or am I missing something?

Well, the Tegra SD/MMC driver works exactly that way (well, mapping an
instance ID to both base address and periph ID), so there's certainly
precedent for this. And that driver is not unique.

>>>>>>> +int board_usb_init(const void *blob)
>>>>>>> +{
>>>>>>> +#ifdef CONFIG_OF_CONTROL
>>>>>>> +       struct fdt_usb config;
>>>>>>> +       int clk_done = 0;
>>>>>>> +       int node, upto = 0;
>>>>>>> +       unsigned osc_freq = clock_get_rate(CLOCK_ID_OSC);
>>>>>>> +
>>>>>>> +       do {
>>>>>>> +               node = fdtdec_next_alias(blob, "usb",
>>>>>>> +                                        COMPAT_NVIDIA_TEGRA20_USB, &upto);
>>>>>>
>>>>>> Why only initialize USB controllers with aliases? Surely this should
>>>>>> enumerate all nodes with a specific compatible flag?
>>>>>
>>>>> See my other comments - we want to know that port 0 is USB3 on Seaboard.
>>>>
>>>> Why does U-Boot care? Everything should be enumerating which peripherals
>>>> happen to appear on the various USB busses, and not care which host
>>>> controller they're attached to.
>>>
>>> At present we do:
>>>
>>> 'usb start 0'
>>> 'usb start 1'
>>>
>>> to select between the ports. There is a patch in the works to change
>>> that but it hasn't gone upstream yet, or at least wasn't accepted.

Judging by the USB driver, there's actually only "usb start" with no
parameter, and ehc-tegra.c:ehci_hcd_init() hard-codes this as starting
port 0. That's a little more severe. Anyway, that implies to me that
tegra-seaboard.dts should set status = "disabled" on all but one port,
because the others will be useless anyway.

>> Can you point out the patch that changes this, and what exactly it
>> changes. Hopefully it removes the parameter from the "usb start" command.
> 
> Yes, they are in the Chromium tree:
> 
> https://gerrit.chromium.org/gerrit/#change,4951
> https://gerrit.chromium.org/gerrit/#change,4981

OK, those look interesting, at least from the commit descriptions. I'd
assert they really should be upstreamed before or as part of the Tegra
USB driver addition, since it makes the whole /aliases thing completely
irrelevant for USB.

>> I'm still not convinced why U-Boot cares about this (as opposed to the
>> user using U-Boot).
> 
> Well if U-Boot presents the ports in the wrong order, the user's
> scripts will fail.
> 
> Also, what about the console UART problem? Surely the kernel provides
> a way to select the ordering of those? How do I know what UART I am
> getting on /dev/ttyS0?

That's a question my subconscious has been asking me for a while to. The
answer is that it's all very accidental...

The kernel serial driver needs a clock-frequency property. If it isn't
present, the driver won't initialize. The .dts files in the kernel only
have this property for serial ports that are hooked up on the given
board. In the case (Paz00 a/k/a Toshiba AC100) where multiple serial
ports have this property, the useful one just happens to be the one the
kernel processes first. So, it all just happens to work out. I have
since at least posted patches to add explicit status = "disabled" for
the ports that aren't hooked up, but we should start thinking about how
to use /aliases to force a particular enumeration order rather than
relying on whatever is making it work accidentally.
Simon Glass - Dec. 6, 2011, 1:14 a.m.
Hi Stephen,

On Mon, Dec 5, 2011 at 4:17 PM, Stephen Warren <swarren@nvidia.com> wrote:
> On 12/05/2011 04:35 PM, Simon Glass wrote:
>> Hi Stephen,
>>
>> On Mon, Dec 5, 2011 at 2:15 PM, Stephen Warren <swarren@nvidia.com> wrote:
>>> On 12/05/2011 02:46 PM, Simon Glass wrote:
>>>> Hi Stephen,
>>>>
>>>> On Mon, Dec 5, 2011 at 1:33 PM, Stephen Warren <swarren@nvidia.com> wrote:
>>>>> On 12/02/2011 05:59 PM, Simon Glass wrote:
>>>>>> Hi Stephen,
>>>>>>
>>>>>> Here are my comments on the rest of your email.
>>>>>>
>>>>>> On Mon, Nov 28, 2011 at 11:21 AM, Stephen Warren <swarren@nvidia.com> wrote:
>>>>>>> On 11/23/2011 08:54 PM, Simon Glass wrote:
>>>>>>>> This adds basic support for the Tegra2 USB controller. Board files should
>>>>>>>> call board_usb_init() to set things up.
>>>>>
>>>>>>>> +       config->enabled = fdtdec_get_is_enabled(blob, node);
>>>>>>>> +       config->periph_id = fdtdec_get_int(blob, node, "periph-id", -1);
>>>>>>>
>>>>>>> periph-id is a U-Boot specific concept, not HW description. The DT
>>>>>>> shouldn't contain that value.
>>>>>>
>>>>>> See my previous comments as to why this is desirable. We can change
>>>>>> over to a clock-based approach once the kernel implements it.
>>>>>
>>>>> That will cause backwards-compatibility problems; older FDTs won't work
>>>>> with newer U-Boots. We should avoid incompatible changes like this if at
>>>>> all possible.
>>>>
>>>> At the moment the fdts are in the U-Boot tree, so we should be able to
>>>> change them at the same time. But of course when we update the fdt  we
>>>> need to update the U-Boot code. Is there any alternative other than
>>>> doing nothing until the kernel decides everything?
>>>
>>> You can choose not to represent these parameters in the device tree at
>>> all, but rather hard-code the values in the driver. This is what the
>>> kernel currently does; as luck would have it, the required values are
>>> identical for all the boards the kernel currently supports. Once that's
>>> all in place and working, we can work on defining a binding for those
>>> parameters and review/implement it in both U-Boot and the kernel.
>>
>> OK, but how about we have this conversation when things are actually
>> in the kernel and working? The scheme used in this series (peripheral
>> IDs) is very handy for U-Boot and avoids this hard-coding that you
>> refer to.
>
> I'd really like to avoid adding stuff to the .dts file when we know we
> going to rip it out again ASAP. I'd prefer to incrementally enhance the
> .dts bindings always moving forward, and never removing/breaking stuff
> if possible.
>
> Now you did point out that the .dts files are currently in U-Boot, so
> this is slightly moot since the binding documentation, .dts file and
> driver can all be rev'd in sync. However, I hope this will change soon.
> Otherwise, every addition to them means changing U-Boot, the Linux
> kernel, U-Boot v2, fastboot, quick boot, .....

OK well I can remove the USB params and put in the C file with an
#ifdef for T30. Ick.

>
>> Also the only way I can see it being hard-coded is by the kernel
>> looking at the peripheral address and converting this to an ID. That
>> seems really ugly to me. Or am I missing something?
>
> Well, the Tegra SD/MMC driver works exactly that way (well, mapping an
> instance ID to both base address and periph ID), so there's certainly
> precedent for this. And that driver is not unique.

I don't know if I can NAK a comment but I would like to NAK this one.

>
>>>>>>>> +int board_usb_init(const void *blob)
>>>>>>>> +{
>>>>>>>> +#ifdef CONFIG_OF_CONTROL
>>>>>>>> +       struct fdt_usb config;
>>>>>>>> +       int clk_done = 0;
>>>>>>>> +       int node, upto = 0;
>>>>>>>> +       unsigned osc_freq = clock_get_rate(CLOCK_ID_OSC);
>>>>>>>> +
>>>>>>>> +       do {
>>>>>>>> +               node = fdtdec_next_alias(blob, "usb",
>>>>>>>> +                                        COMPAT_NVIDIA_TEGRA20_USB, &upto);
>>>>>>>
>>>>>>> Why only initialize USB controllers with aliases? Surely this should
>>>>>>> enumerate all nodes with a specific compatible flag?
>>>>>>
>>>>>> See my other comments - we want to know that port 0 is USB3 on Seaboard.
>>>>>
>>>>> Why does U-Boot care? Everything should be enumerating which peripherals
>>>>> happen to appear on the various USB busses, and not care which host
>>>>> controller they're attached to.
>>>>
>>>> At present we do:
>>>>
>>>> 'usb start 0'
>>>> 'usb start 1'
>>>>
>>>> to select between the ports. There is a patch in the works to change
>>>> that but it hasn't gone upstream yet, or at least wasn't accepted.
>
> Judging by the USB driver, there's actually only "usb start" with no
> parameter, and ehc-tegra.c:ehci_hcd_init() hard-codes this as starting
> port 0. That's a little more severe. Anyway, that implies to me that
> tegra-seaboard.dts should set status = "disabled" on all but one port,
> because the others will be useless anyway.
>
>>> Can you point out the patch that changes this, and what exactly it
>>> changes. Hopefully it removes the parameter from the "usb start" command.
>>
>> Yes, they are in the Chromium tree:
>>
>> https://gerrit.chromium.org/gerrit/#change,4951
>> https://gerrit.chromium.org/gerrit/#change,4981
>
> OK, those look interesting, at least from the commit descriptions. I'd
> assert they really should be upstreamed before or as part of the Tegra
> USB driver addition, since it makes the whole /aliases thing completely
> irrelevant for USB.

No, that needs to be decoupled from this in my view. That is a large
and invasive change which is AFAIK only useful for Tegra. It's not at
all clear it will be accepted.

>
>>> I'm still not convinced why U-Boot cares about this (as opposed to the
>>> user using U-Boot).
>>
>> Well if U-Boot presents the ports in the wrong order, the user's
>> scripts will fail.
>>
>> Also, what about the console UART problem? Surely the kernel provides
>> a way to select the ordering of those? How do I know what UART I am
>> getting on /dev/ttyS0?
>
> That's a question my subconscious has been asking me for a while to. The
> answer is that it's all very accidental...
>
> The kernel serial driver needs a clock-frequency property. If it isn't
> present, the driver won't initialize. The .dts files in the kernel only
> have this property for serial ports that are hooked up on the given
> board. In the case (Paz00 a/k/a Toshiba AC100) where multiple serial
> ports have this property, the useful one just happens to be the one the
> kernel processes first. So, it all just happens to work out. I have
> since at least posted patches to add explicit status = "disabled" for
> the ports that aren't hooked up, but we should start thinking about how
> to use /aliases to force a particular enumeration order rather than
> relying on whatever is making it work accidentally.

Ickity ick. I think I'll keep my aliases if it's ok with you?

Regards,
Simon

>
> --
> nvpublic
Stephen Warren - Dec. 6, 2011, 8:42 p.m.
On 12/05/2011 06:14 PM, Simon Glass wrote:
> Hi Stephen,
> 
> On Mon, Dec 5, 2011 at 4:17 PM, Stephen Warren <swarren@nvidia.com> wrote:
>> On 12/05/2011 04:35 PM, Simon Glass wrote:
...
>> I'd really like to avoid adding stuff to the .dts file when we know we
>> going to rip it out again ASAP. I'd prefer to incrementally enhance the
>> .dts bindings always moving forward, and never removing/breaking stuff
>> if possible.
>>
>> Now you did point out that the .dts files are currently in U-Boot, so
>> this is slightly moot since the binding documentation, .dts file and
>> driver can all be rev'd in sync. However, I hope this will change soon.
>> Otherwise, every addition to them means changing U-Boot, the Linux
>> kernel, U-Boot v2, fastboot, quick boot, .....
> 
> OK well I can remove the USB params and put in the C file with an
> #ifdef for T30. Ick.

There's no T30 support in mainline U-Boot, so I think you can avoid any
ifdefs.

>>> Also the only way I can see it being hard-coded is by the kernel
>>> looking at the peripheral address and converting this to an ID. That
>>> seems really ugly to me. Or am I missing something?
>>
>> Well, the Tegra SD/MMC driver works exactly that way (well, mapping an
>> instance ID to both base address and periph ID), so there's certainly
>> precedent for this. And that driver is not unique.
> 
> I don't know if I can NAK a comment but I would like to NAK this one.

I don't know what that means; that you believe my statement is
incorrect, or you don't like the argument I'm basing on it or ...?

>>>>> At present we do:
>>>>>
>>>>> 'usb start 0'
>>>>> 'usb start 1'
>>>>>
>>>>> to select between the ports. There is a patch in the works to change
>>>>> that but it hasn't gone upstream yet, or at least wasn't accepted.
>>>> Can you point out the patch that changes this, and what exactly it
>>>> changes. Hopefully it removes the parameter from the "usb start" command.
>>>
>>> Yes, they are in the Chromium tree:
>>>
>>> https://gerrit.chromium.org/gerrit/#change,4951
>>> https://gerrit.chromium.org/gerrit/#change,4981
>>
>> OK, those look interesting, at least from the commit descriptions. I'd
>> assert they really should be upstreamed before or as part of the Tegra
>> USB driver addition, since it makes the whole /aliases thing completely
>> irrelevant for USB.
> 
> No, that needs to be decoupled from this in my view. That is a large
> and invasive change which is AFAIK only useful for Tegra. It's not at
> all clear it will be accepted.

Surely it's useful for any SoC that has multiple USB controllers, and
where the user may plug peripherals into more than 1 of them. I assume
that's common. Or am I misunderstanding what those patches do?

>>>> I'm still not convinced why U-Boot cares about this (as opposed to the
>>>> user using U-Boot).
>>>
>>> Well if U-Boot presents the ports in the wrong order, the user's
>>> scripts will fail.
>>>
>>> Also, what about the console UART problem? Surely the kernel provides
>>> a way to select the ordering of those? How do I know what UART I am
>>> getting on /dev/ttyS0?
>>
>> That's a question my subconscious has been asking me for a while to. The
>> answer is that it's all very accidental...
>>
>> The kernel serial driver needs a clock-frequency property. If it isn't
>> present, the driver won't initialize. The .dts files in the kernel only
>> have this property for serial ports that are hooked up on the given
>> board. In the case (Paz00 a/k/a Toshiba AC100) where multiple serial
>> ports have this property, the useful one just happens to be the one the
>> kernel processes first. So, it all just happens to work out. I have
>> since at least posted patches to add explicit status = "disabled" for
>> the ports that aren't hooked up, but we should start thinking about how
>> to use /aliases to force a particular enumeration order rather than
>> relying on whatever is making it work accidentally.
> 
> Ickity ick. I think I'll keep my aliases if it's ok with you?

Having aliases is fine.

Using aliases to name the devices which get instantiated through
standardized enumeration mechanisms is fine.

To the best of my knowledge, restricting device enumeration based on the
aliases is non-standard, hence wrong.

As I mentioned elsewhere, the patches only allow one to actually use usb
controller 0; ehci-tegra.c's ehci_hcd_init() hard-codes port 0 when
calling tegrausb_start_port(). Rather than relying on non-standard
aliases usage to restrict the set of USB devices that get instantiated,
why not just add status = "disabled" to all but one USB host's node in
each board's .dts file; that's the standard way to disable devices.
Simon Glass - Dec. 6, 2011, 9:23 p.m.
Hi Stephen,

On Tue, Dec 6, 2011 at 12:42 PM, Stephen Warren <swarren@nvidia.com> wrote:
> On 12/05/2011 06:14 PM, Simon Glass wrote:
>> Hi Stephen,
>>
>> On Mon, Dec 5, 2011 at 4:17 PM, Stephen Warren <swarren@nvidia.com> wrote:
>>> On 12/05/2011 04:35 PM, Simon Glass wrote:
> ...
>>> I'd really like to avoid adding stuff to the .dts file when we know we
>>> going to rip it out again ASAP. I'd prefer to incrementally enhance the
>>> .dts bindings always moving forward, and never removing/breaking stuff
>>> if possible.
>>>
>>> Now you did point out that the .dts files are currently in U-Boot, so
>>> this is slightly moot since the binding documentation, .dts file and
>>> driver can all be rev'd in sync. However, I hope this will change soon.
>>> Otherwise, every addition to them means changing U-Boot, the Linux
>>> kernel, U-Boot v2, fastboot, quick boot, .....
>>
>> OK well I can remove the USB params and put in the C file with an
>> #ifdef for T30. Ick.
>
> There's no T30 support in mainline U-Boot, so I think you can avoid any
> ifdefs.
>
>>>> Also the only way I can see it being hard-coded is by the kernel
>>>> looking at the peripheral address and converting this to an ID. That
>>>> seems really ugly to me. Or am I missing something?
>>>
>>> Well, the Tegra SD/MMC driver works exactly that way (well, mapping an
>>> instance ID to both base address and periph ID), so there's certainly
>>> precedent for this. And that driver is not unique.
>>
>> I don't know if I can NAK a comment but I would like to NAK this one.
>
> I don't know what that means; that you believe my statement is
> incorrect, or you don't like the argument I'm basing on it or ...?

What happens is that the SD/MMC driver (dating from pre-FDT days) has
a hard-coded base address and peripheral ID, based on an instance ID
(0, 1, 2).

I would expect that we want the FDT to control all of this - it
already has the base address, can have the peripheral ID, and the
instance ID (ordering) should be set by the FDT not hard-coded IMO.
That's the reason for my NAK comment. It just seems completely wrong
to duplicate this information in the driver and require the instance
ordering to be hard-coded in the driver. It means that boards that
want to change this ordering must fiddle around in the driver to make
this work.

Also this is U-Boot, not the kernel. Commands like 'ext2load' require
that you pass the instance ID to indicate which device to use.

>
>>>>>> At present we do:
>>>>>>
>>>>>> 'usb start 0'
>>>>>> 'usb start 1'
>>>>>>
>>>>>> to select between the ports. There is a patch in the works to change
>>>>>> that but it hasn't gone upstream yet, or at least wasn't accepted.
>>>>> Can you point out the patch that changes this, and what exactly it
>>>>> changes. Hopefully it removes the parameter from the "usb start" command.
>>>>
>>>> Yes, they are in the Chromium tree:
>>>>
>>>> https://gerrit.chromium.org/gerrit/#change,4951
>>>> https://gerrit.chromium.org/gerrit/#change,4981
>>>
>>> OK, those look interesting, at least from the commit descriptions. I'd
>>> assert they really should be upstreamed before or as part of the Tegra
>>> USB driver addition, since it makes the whole /aliases thing completely
>>> irrelevant for USB.
>>
>> No, that needs to be decoupled from this in my view. That is a large
>> and invasive change which is AFAIK only useful for Tegra. It's not at
>> all clear it will be accepted.
>
> Surely it's useful for any SoC that has multiple USB controllers, and
> where the user may plug peripherals into more than 1 of them. I assume
> that's common. Or am I misunderstanding what those patches do?

I don't believe it has been an issue with other SOCs, but I don't know
for sure. Anyway, it is sideways to this issue. I agree it should be
upstreamed but a separate series IMO.

>
>>>>> I'm still not convinced why U-Boot cares about this (as opposed to the
>>>>> user using U-Boot).
>>>>
>>>> Well if U-Boot presents the ports in the wrong order, the user's
>>>> scripts will fail.
>>>>
>>>> Also, what about the console UART problem? Surely the kernel provides
>>>> a way to select the ordering of those? How do I know what UART I am
>>>> getting on /dev/ttyS0?
>>>
>>> That's a question my subconscious has been asking me for a while to. The
>>> answer is that it's all very accidental...
>>>
>>> The kernel serial driver needs a clock-frequency property. If it isn't
>>> present, the driver won't initialize. The .dts files in the kernel only
>>> have this property for serial ports that are hooked up on the given
>>> board. In the case (Paz00 a/k/a Toshiba AC100) where multiple serial
>>> ports have this property, the useful one just happens to be the one the
>>> kernel processes first. So, it all just happens to work out. I have
>>> since at least posted patches to add explicit status = "disabled" for
>>> the ports that aren't hooked up, but we should start thinking about how
>>> to use /aliases to force a particular enumeration order rather than
>>> relying on whatever is making it work accidentally.
>>
>> Ickity ick. I think I'll keep my aliases if it's ok with you?
>
> Having aliases is fine.
>
> Using aliases to name the devices which get instantiated through
> standardized enumeration mechanisms is fine.
>
> To the best of my knowledge, restricting device enumeration based on the
> aliases is non-standard, hence wrong.

OK, so is your objection that we ignore a peripheral that has no
alias? If I change the code to locate these and add them at the end
would that be better?

>
> As I mentioned elsewhere, the patches only allow one to actually use usb
> controller 0; ehci-tegra.c's ehci_hcd_init() hard-codes port 0 when
> calling tegrausb_start_port(). Rather than relying on non-standard
> aliases usage to restrict the set of USB devices that get instantiated,
> why not just add status = "disabled" to all but one USB host's node in
> each board's .dts file; that's the standard way to disable devices.

I can do that, but how do I solve the ordering problem?

Regards,
Simon

>
> --
> nvpublic
Stephen Warren - Dec. 7, 2011, 11:46 p.m.
On 12/06/2011 02:23 PM, Simon Glass wrote:
> Hi Stephen,
> 
> On Tue, Dec 6, 2011 at 12:42 PM, Stephen Warren <swarren@nvidia.com> wrote:
>> On 12/05/2011 06:14 PM, Simon Glass wrote:
>>> Hi Stephen,
>>>
>>> On Mon, Dec 5, 2011 at 4:17 PM, Stephen Warren <swarren@nvidia.com> wrote:
>>>> On 12/05/2011 04:35 PM, Simon Glass wrote:
...
>>>>> Also the only way I can see it being hard-coded is by the kernel
>>>>> looking at the peripheral address and converting this to an ID. That
>>>>> seems really ugly to me. Or am I missing something?
>>>>
>>>> Well, the Tegra SD/MMC driver works exactly that way (well, mapping an
>>>> instance ID to both base address and periph ID), so there's certainly
>>>> precedent for this. And that driver is not unique.
>>>
>>> I don't know if I can NAK a comment but I would like to NAK this one.
>>
>> I don't know what that means; that you believe my statement is
>> incorrect, or you don't like the argument I'm basing on it or ...?
> 
> What happens is that the SD/MMC driver (dating from pre-FDT days) has
> a hard-coded base address and peripheral ID, based on an instance ID
> (0, 1, 2).

That's basically the exact same thing, it's just the exact fields that
are the key into and output from the table are different.

> I would expect that we want the FDT to control all of this - it
> already has the base address, can have the peripheral ID, and the
> instance ID (ordering) should be set by the FDT not hard-coded IMO.
> That's the reason for my NAK comment. It just seems completely wrong
> to duplicate this information in the driver and require the instance
> ordering to be hard-coded in the driver. It means that boards that
> want to change this ordering must fiddle around in the driver to make
> this work.
> 
> Also this is U-Boot, not the kernel. Commands like 'ext2load' require
> that you pass the instance ID to indicate which device to use.

SD/MMC is a very different use-case, and not a good analogy to USB.

With SD, the user always wants to identify a specific device that they
know contains their files.

With USB, the user doesn't care that there are multiple USB host
controllers in the SoC; they just want to plug in their device somewhere
and have it work. Having to decide which USB controller to enable at a
time is pretty hokey, given there's unlikely to be any indication at all
on the PCB or case which ports map to which USB controllers.

What the user might care about is selecting a enumerated particular USB
device. They'd only know which one after looking at some "lsusb" command
(or whatever it's called in U-Boot) in the general case.

Hence, I assert that USB host controller number is completely
irrelevant, and all should be active at once.

This of course is all somewhat moot given that I pointed out
ehci-tegra.c only supports one of the hosts anyway...

> OK, so is your objection that we ignore a peripheral that has no
> alias?

Yes.

And that enumeration is based on alias nodes not enumerating all nodes
that match the compatible flag.

> If I change the code to locate these and add them at the end
> would that be better?

Sure.

I think the best implementation would be to enumerate everything solely
based on compatible flags, and allowing "usb start" to accept either an
alias name (which would be fixed) or a DT unit address or node name
(which would be fixed) or a controller index (which might vary based on
enumeration order) to select the controller.

The next best implementation would be to enumerate solely based on
compatible flags, then sort the list based on alias, thus allowing alias
to cause a static order.

However, enumerating based on alias, then enumerating based on
compatible flags and adding any missing nodes would be fine.

>> As I mentioned elsewhere, the patches only allow one to actually use usb
>> controller 0; ehci-tegra.c's ehci_hcd_init() hard-codes port 0 when
>> calling tegrausb_start_port(). Rather than relying on non-standard
>> aliases usage to restrict the set of USB devices that get instantiated,
>> why not just add status = "disabled" to all but one USB host's node in
>> each board's .dts file; that's the standard way to disable devices.
> 
> I can do that, but how do I solve the ordering problem?

If you only have one enabled controller in the .dts file, there can't be
any ordering issue since there is always only 1 controller.
Simon Glass - Dec. 8, 2011, 9:24 p.m.
Hi Stephen,

On Wed, Dec 7, 2011 at 3:46 PM, Stephen Warren <swarren@nvidia.com> wrote:
> On 12/06/2011 02:23 PM, Simon Glass wrote:
>> Hi Stephen,
>>
>> On Tue, Dec 6, 2011 at 12:42 PM, Stephen Warren <swarren@nvidia.com> wrote:
>>> On 12/05/2011 06:14 PM, Simon Glass wrote:
>>>> Hi Stephen,
>>>>
>>>> On Mon, Dec 5, 2011 at 4:17 PM, Stephen Warren <swarren@nvidia.com> wrote:
>>>>> On 12/05/2011 04:35 PM, Simon Glass wrote:
> ...
>>>>>> Also the only way I can see it being hard-coded is by the kernel
>>>>>> looking at the peripheral address and converting this to an ID. That
>>>>>> seems really ugly to me. Or am I missing something?
>>>>>
>>>>> Well, the Tegra SD/MMC driver works exactly that way (well, mapping an
>>>>> instance ID to both base address and periph ID), so there's certainly
>>>>> precedent for this. And that driver is not unique.
>>>>
>>>> I don't know if I can NAK a comment but I would like to NAK this one.
>>>
>>> I don't know what that means; that you believe my statement is
>>> incorrect, or you don't like the argument I'm basing on it or ...?
>>
>> What happens is that the SD/MMC driver (dating from pre-FDT days) has
>> a hard-coded base address and peripheral ID, based on an instance ID
>> (0, 1, 2).
>
> That's basically the exact same thing, it's just the exact fields that
> are the key into and output from the table are different.
>
>> I would expect that we want the FDT to control all of this - it
>> already has the base address, can have the peripheral ID, and the
>> instance ID (ordering) should be set by the FDT not hard-coded IMO.
>> That's the reason for my NAK comment. It just seems completely wrong
>> to duplicate this information in the driver and require the instance
>> ordering to be hard-coded in the driver. It means that boards that
>> want to change this ordering must fiddle around in the driver to make
>> this work.
>>
>> Also this is U-Boot, not the kernel. Commands like 'ext2load' require
>> that you pass the instance ID to indicate which device to use.
>
> SD/MMC is a very different use-case, and not a good analogy to USB.
>
> With SD, the user always wants to identify a specific device that they
> know contains their files.
>
> With USB, the user doesn't care that there are multiple USB host
> controllers in the SoC; they just want to plug in their device somewhere
> and have it work. Having to decide which USB controller to enable at a
> time is pretty hokey, given there's unlikely to be any indication at all
> on the PCB or case which ports map to which USB controllers.
>
> What the user might care about is selecting a enumerated particular USB
> device. They'd only know which one after looking at some "lsusb" command
> (or whatever it's called in U-Boot) in the general case.
>
> Hence, I assert that USB host controller number is completely
> irrelevant, and all should be active at once.

In our case we do not want to look at the USB port the contains the 3G
modem, for example, just the external one which can contain a USB
stick.

>
> This of course is all somewhat moot given that I pointed out
> ehci-tegra.c only supports one of the hosts anyway...
>
>> OK, so is your objection that we ignore a peripheral that has no
>> alias?
>
> Yes.

OK. We will ignore it anyway since USB2 is marked as disabled, but I
agree that isn't true in general.

>
> And that enumeration is based on alias nodes not enumerating all nodes
> that match the compatible flag.
>
>> If I change the code to locate these and add them at the end
>> would that be better?
>
> Sure.
>
> I think the best implementation would be to enumerate everything solely
> based on compatible flags, and allowing "usb start" to accept either an
> alias name (which would be fixed) or a DT unit address or node name
> (which would be fixed) or a controller index (which might vary based on
> enumeration order) to select the controller.
>
> The next best implementation would be to enumerate solely based on
> compatible flags, then sort the list based on alias, thus allowing alias
> to cause a static order.
>
> However, enumerating based on alias, then enumerating based on
> compatible flags and adding any missing nodes would be fine.

Well ok. Since this is basically a small *addition* to the code
(scanning things that don't have an alias), and will have no effect
with the device tree as included in this series, I would like to do
this as a follow-on patch after the series. I hope you can live with
that also?

>
>>> As I mentioned elsewhere, the patches only allow one to actually use usb
>>> controller 0; ehci-tegra.c's ehci_hcd_init() hard-codes port 0 when
>>> calling tegrausb_start_port(). Rather than relying on non-standard
>>> aliases usage to restrict the set of USB devices that get instantiated,
>>> why not just add status = "disabled" to all but one USB host's node in
>>> each board's .dts file; that's the standard way to disable devices.
>>
>> I can do that, but how do I solve the ordering problem?
>
> If you only have one enabled controller in the .dts file, there can't be
> any ordering issue since there is always only 1 controller.

I really was referring to how it should be done. We will enable two
points. Only one is currently accessible due to us needing either a
parameter to 'usb start' or the virtual ehci hub code. But USB
upstreaming is not complete after this series - it is only a step in
the process. I feel that 14 patches is big enough for a series :-)

Regards,
Simon

>
> --
> nvpublic
Stephen Warren - Dec. 12, 2011, 6:18 p.m.
On 12/08/2011 02:24 PM, Simon Glass wrote:
> On Wed, Dec 7, 2011 at 3:46 PM, Stephen Warren <swarren@nvidia.com> wrote:
>> On 12/06/2011 02:23 PM, Simon Glass wrote:
...
>> I think the best implementation would be to enumerate everything solely
>> based on compatible flags, and allowing "usb start" to accept either an
>> alias name (which would be fixed) or a DT unit address or node name
>> (which would be fixed) or a controller index (which might vary based on
>> enumeration order) to select the controller.
>>
>> The next best implementation would be to enumerate solely based on
>> compatible flags, then sort the list based on alias, thus allowing alias
>> to cause a static order.
>>
>> However, enumerating based on alias, then enumerating based on
>> compatible flags and adding any missing nodes would be fine.
> 
> Well ok. Since this is basically a small *addition* to the code
> (scanning things that don't have an alias), and will have no effect
> with the device tree as included in this series, I would like to do
> this as a follow-on patch after the series. I hope you can live with
> that also?

I suppose it'll have to do.

It's totally the wrong way to go about it though, and will provide a bad
example that'll probably end up proliferating itself through the code
since it's the first example.

In other words rather than:

Now: Scan /aliases for USB, add then all.

Later: Scan device nodes for any that weren't in /aliases, add them all

I'd prefer to see:

Now: Scan /aliases for USB, add then all.

Later: Remove all the /aliases scanning code, fix the code to scan all
child nodes of the SoC node, find all nodes matching the USB compatible
flag, add them all. While adding a USB controller, check the /alias node
and honor any alias there if there is one.
Simon Glass - Dec. 12, 2011, 6:42 p.m.
Hi Stephen,

On Mon, Dec 12, 2011 at 10:18 AM, Stephen Warren <swarren@nvidia.com> wrote:
> On 12/08/2011 02:24 PM, Simon Glass wrote:
>> On Wed, Dec 7, 2011 at 3:46 PM, Stephen Warren <swarren@nvidia.com> wrote:
>>> On 12/06/2011 02:23 PM, Simon Glass wrote:
> ...
>>> I think the best implementation would be to enumerate everything solely
>>> based on compatible flags, and allowing "usb start" to accept either an
>>> alias name (which would be fixed) or a DT unit address or node name
>>> (which would be fixed) or a controller index (which might vary based on
>>> enumeration order) to select the controller.
>>>
>>> The next best implementation would be to enumerate solely based on
>>> compatible flags, then sort the list based on alias, thus allowing alias
>>> to cause a static order.
>>>
>>> However, enumerating based on alias, then enumerating based on
>>> compatible flags and adding any missing nodes would be fine.
>>
>> Well ok. Since this is basically a small *addition* to the code
>> (scanning things that don't have an alias), and will have no effect
>> with the device tree as included in this series, I would like to do
>> this as a follow-on patch after the series. I hope you can live with
>> that also?
>
> I suppose it'll have to do.
>
> It's totally the wrong way to go about it though, and will provide a bad
> example that'll probably end up proliferating itself through the code
> since it's the first example.
>
> In other words rather than:
>
> Now: Scan /aliases for USB, add then all.
>
> Later: Scan device nodes for any that weren't in /aliases, add them all
>
> I'd prefer to see:
>
> Now: Scan /aliases for USB, add then all.
>
> Later: Remove all the /aliases scanning code, fix the code to scan all
> child nodes of the SoC node, find all nodes matching the USB compatible
> flag, add them all. While adding a USB controller, check the /alias node
> and honor any alias there if there is one.

OK, perhaps I am thinking too closely about an efficient algorithm as
separate from the required function. This patch series does the 'Now'
but, and the 'Later' bit can be done as you say I think. Issues that
come include someone having an alias for port 2 but not 1, and having
to detect this and move things down at the end. I will need to think
about support in fdtdec to make this easy. That's why I want to do it
later as this patch series is already large and we are well aware of
its limitations in several areas (e.g. there is no way to use port 1
in U-Boot yet).

Regards,
Simon

>
> --
> nvpublic

Patch

diff --git a/arch/arm/cpu/armv7/tegra2/Makefile b/arch/arm/cpu/armv7/tegra2/Makefile
index 955c3b6..70e7abd 100644
--- a/arch/arm/cpu/armv7/tegra2/Makefile
+++ b/arch/arm/cpu/armv7/tegra2/Makefile
@@ -33,8 +33,10 @@  include $(TOPDIR)/config.mk
 LIB	=  $(obj)lib$(SOC).o
 
 SOBJS	:= lowlevel_init.o
-COBJS	:= ap20.o board.o clock.o pinmux.o sys_info.o timer.o
+COBJS-y	:= ap20.o board.o clock.o pinmux.o sys_info.o timer.o
+COBJS-$(CONFIG_USB_EHCI_TEGRA) += usb.o
 
+COBJS	:= $(COBJS-y)
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
 
diff --git a/arch/arm/cpu/armv7/tegra2/usb.c b/arch/arm/cpu/armv7/tegra2/usb.c
new file mode 100644
index 0000000..311c0ca
--- /dev/null
+++ b/arch/arm/cpu/armv7/tegra2/usb.c
@@ -0,0 +1,494 @@ 
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * (C) Copyright 2010,2011 NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm-generic/gpio.h>
+#include <asm/arch/tegra2.h>
+#include <asm/arch/clk_rst.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/uart.h>
+#include <asm/arch/usb.h>
+#include <libfdt.h>
+#include <fdtdec.h>
+
+enum {
+	USB_PORTS_MAX	= 4,			/* Maximum ports we allow */
+};
+
+struct usb_port {
+	struct usb_ctlr *reg;
+};
+
+static struct usb_port port[USB_PORTS_MAX];	/* List of valid USB ports */
+static unsigned port_count;			/* Number of available ports */
+static int port_current;			/* Current port (-1 = none) */
+
+/* Record which controller can switch from host to device mode */
+static struct usb_ctlr *host_dev_ctlr;
+
+/* Parameters we need for USB */
+enum {
+	PARAM_DIVN,                     /* PLL FEEDBACK DIVIDer */
+	PARAM_DIVM,                     /* PLL INPUT DIVIDER */
+	PARAM_DIVP,                     /* POST DIVIDER (2^N) */
+	PARAM_CPCON,                    /* BASE PLLC CHARGE Pump setup ctrl */
+	PARAM_LFCON,                    /* BASE PLLC LOOP FILter setup ctrl */
+	PARAM_ENABLE_DELAY_COUNT,       /* PLL-U Enable Delay Count */
+	PARAM_STABLE_COUNT,             /* PLL-U STABLE count */
+	PARAM_ACTIVE_DELAY_COUNT,       /* PLL-U Active delay count */
+	PARAM_XTAL_FREQ_COUNT,          /* PLL-U XTAL frequency count */
+	PARAM_DEBOUNCE_A_TIME,          /* 10MS DELAY for BIAS_DEBOUNCE_A */
+	PARAM_BIAS_TIME,                /* 20US DELAY AFter bias cell op */
+
+	PARAM_COUNT
+};
+
+/* Information about USB */
+struct fdt_usb {
+	struct usb_ctlr *reg;   /* address of registers in physical memory */
+	int params[PARAM_COUNT]; /* timing parameters */
+	int host_mode;          /* 1 if port has host mode, else 0 */
+	int utmi;               /* 1 if port has external tranceiver, else 0 */
+	int enabled;            /* 1 to enable, 0 to disable */
+	enum periph_id periph_id;/* peripheral id */
+};
+
+#ifndef CONFIG_OF_CONTROL
+/*
+ * This table has USB timing parameters for each Oscillator frequency we
+ * support. There are four sets of values:
+ *
+ * 1. PLLU configuration information (reference clock is osc/clk_m and
+ * PLLU-FOs are fixed at 12MHz/60MHz/480MHz).
+ *
+ *  Reference frequency     13.0MHz      19.2MHz      12.0MHz      26.0MHz
+ *  ----------------------------------------------------------------------
+ *      DIVN                960 (0x3c0)  200 (0c8)    960 (3c0h)   960 (3c0)
+ *      DIVM                13 (0d)      4 (04)       12 (0c)      26 (1a)
+ * Filter frequency (MHz)   1            4.8          6            2
+ * CPCON                    1100b        0011b        1100b        1100b
+ * LFCON0                   0            0            0            0
+ *
+ * 2. PLL CONFIGURATION & PARAMETERS for different clock generators:
+ *
+ * Reference frequency     13.0MHz         19.2MHz         12.0MHz     26.0MHz
+ * ---------------------------------------------------------------------------
+ * PLLU_ENABLE_DLY_COUNT   02 (0x02)       03 (03)         02 (02)     04 (04)
+ * PLLU_STABLE_COUNT       51 (33)         75 (4B)         47 (2F)    102 (66)
+ * PLL_ACTIVE_DLY_COUNT    05 (05)         06 (06)         04 (04)     09 (09)
+ * XTAL_FREQ_COUNT        127 (7F)        187 (BB)        118 (76)    254 (FE)
+ *
+ * 3. Debounce values IdDig, Avalid, Bvalid, VbusValid, VbusWakeUp, and
+ * SessEnd. Each of these signals have their own debouncer and for each of
+ * those one out of two debouncing times can be chosen (BIAS_DEBOUNCE_A or
+ * BIAS_DEBOUNCE_B).
+ *
+ * The values of DEBOUNCE_A and DEBOUNCE_B are calculated as follows:
+ *    0xffff -> No debouncing at all
+ *    <n> ms = <n> *1000 / (1/19.2MHz) / 4
+ *
+ * So to program a 1 ms debounce for BIAS_DEBOUNCE_A, we have:
+ * BIAS_DEBOUNCE_A[15:0] = 1000 * 19.2 / 4  = 4800 = 0x12c0
+ *
+ * We need to use only DebounceA for BOOTROM. We don't need the DebounceB
+ * values, so we can keep those to default.
+ *
+ * 4. The 20 microsecond delay after bias cell operation.
+ */
+static const int usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = {
+	/* DivN, DivM, DivP, CPCON, LFCON, Delays             Debounce, Bias */
+	{ 0x3C0, 0x0D, 0x00, 0xC,   0,  0x02, 0x33, 0x05, 0x7F, 0x7EF4, 5 },
+	{ 0x0C8, 0x04, 0x00, 0x3,   0,  0x03, 0x4B, 0x06, 0xBB, 0xBB80, 7 },
+	{ 0x3C0, 0x0C, 0x00, 0xC,   0,  0x02, 0x2F, 0x04, 0x76, 0x7530, 5 },
+	{ 0x3C0, 0x1A, 0x00, 0xC,   0,  0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 }
+};
+#endif
+
+/* UTMIP Idle Wait Delay */
+static const u8 utmip_idle_wait_delay = 17;
+
+/* UTMIP Elastic limit */
+static const u8 utmip_elastic_limit = 16;
+
+/* UTMIP High Speed Sync Start Delay */
+static const u8 utmip_hs_sync_start_delay = 9;
+
+/* Put the port into host mode (this only works for USB1) */
+static void set_host_mode(struct usb_ctlr *usbctlr)
+{
+	/* Check whether remote host from USB1 is driving VBus */
+	if (readl(&usbctlr->phy_vbus_sensors) & VBUS_VLD_STS)
+		return;
+
+	/*
+	 * If not driving, we set GPIO USB1_VBus_En. Seaboard platform uses
+	 * PAD SLXK (GPIO D.00) as USB1_VBus_En Config as GPIO
+	 */
+	gpio_direction_output(GPIO_PD0, 1);
+
+	/* Z_SLXK = 0, normal, not tristate */
+	pinmux_tristate_disable(PINGRP_SLXK);
+}
+
+/* Put our ports into host mode */
+void usb_set_host_mode(void)
+{
+	if (host_dev_ctlr)
+		set_host_mode(host_dev_ctlr);
+}
+
+void usbf_reset_controller(enum periph_id id, struct usb_ctlr *usbctlr)
+{
+	/* Reset the USB controller with 2us delay */
+	reset_periph(id, 2);
+
+	/*
+	 * Set USB1_NO_LEGACY_MODE to 1, Registers are accessible under
+	 * base address
+	 */
+	if (id == PERIPH_ID_USBD)
+		setbits_le32(&usbctlr->usb1_legacy_ctrl, USB1_NO_LEGACY_MODE);
+
+	/* Put UTMIP1/3 in reset */
+	setbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET);
+
+	/* Set USB3 to use UTMIP PHY */
+	if (id == PERIPH_ID_USB3)
+		setbits_le32(&usbctlr->susp_ctrl, UTMIP_PHY_ENB);
+
+	/*
+	 * TODO: where do we take the USB1 out of reset? The old code would
+	 * take USB3 out of reset, but not USB1. This code doesn't do either.
+	 */
+}
+
+/* set up the USB controller with the parameters provided */
+static void init_usb_controller(enum periph_id id, struct usb_ctlr *usbctlr,
+		const int *params)
+{
+	u32 val;
+	int loop_count;
+
+	clock_enable(id);
+
+	/* Reset the usb controller */
+	usbf_reset_controller(id, usbctlr);
+
+	/* Stop crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN low */
+	clrbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN);
+
+	/* Follow the crystal clock disable by >100ns delay */
+	udelay(1);
+
+	/*
+	 * To Use the A Session Valid for cable detection logic, VBUS_WAKEUP
+	 * mux must be switched to actually use a_sess_vld threshold.
+	 */
+	if (id == PERIPH_ID_USBD) {
+		clrsetbits_le32(&usbctlr->usb1_legacy_ctrl,
+			VBUS_SENSE_CTL_MASK, VBUS_SENSE_CTL_A_SESS_VLD);
+	}
+
+	/*
+	 * PLL Delay CONFIGURATION settings. The following parameters control
+	 * the bring up of the plls.
+	 */
+	val = readl(&usbctlr->utmip_misc_cfg1);
+	clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK,
+		params[PARAM_STABLE_COUNT] << UTMIP_PLLU_STABLE_COUNT_SHIFT);
+	clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK,
+		params[PARAM_ACTIVE_DELAY_COUNT] <<
+			UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT);
+	writel(val, &usbctlr->utmip_misc_cfg1);
+
+	/* Set PLL enable delay count and crystal frequency count */
+	val = readl(&usbctlr->utmip_pll_cfg1);
+	clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK,
+		params[PARAM_ENABLE_DELAY_COUNT] <<
+			UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT);
+	clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK,
+		params[PARAM_XTAL_FREQ_COUNT] <<
+			UTMIP_XTAL_FREQ_COUNT_SHIFT);
+	writel(val, &usbctlr->utmip_pll_cfg1);
+
+	/* Setting the tracking length time */
+	clrsetbits_le32(&usbctlr->utmip_bias_cfg1,
+		UTMIP_BIAS_PDTRK_COUNT_MASK,
+		params[PARAM_BIAS_TIME] << UTMIP_BIAS_PDTRK_COUNT_SHIFT);
+
+	/* Program debounce time for VBUS to become valid */
+	clrsetbits_le32(&usbctlr->utmip_debounce_cfg0,
+		UTMIP_DEBOUNCE_CFG0_MASK,
+		params[PARAM_DEBOUNCE_A_TIME] << UTMIP_DEBOUNCE_CFG0_SHIFT);
+
+	setbits_le32(&usbctlr->utmip_tx_cfg0, UTMIP_FS_PREAMBLE_J);
+
+	/* Disable battery charge enabling bit */
+	setbits_le32(&usbctlr->utmip_bat_chrg_cfg0, UTMIP_PD_CHRG);
+
+	clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_XCVR_LSBIAS_SE);
+	setbits_le32(&usbctlr->utmip_spare_cfg0, FUSE_SETUP_SEL);
+
+	/*
+	 * Configure the UTMIP_IDLE_WAIT and UTMIP_ELASTIC_LIMIT
+	 * Setting these fields, together with default values of the
+	 * other fields, results in programming the registers below as
+	 * follows:
+	 *         UTMIP_HSRX_CFG0 = 0x9168c000
+	 *         UTMIP_HSRX_CFG1 = 0x13
+	 */
+
+	/* Set PLL enable delay count and Crystal frequency count */
+	val = readl(&usbctlr->utmip_hsrx_cfg0);
+	clrsetbits_le32(&val, UTMIP_IDLE_WAIT_MASK,
+		utmip_idle_wait_delay << UTMIP_IDLE_WAIT_SHIFT);
+	clrsetbits_le32(&val, UTMIP_ELASTIC_LIMIT_MASK,
+		utmip_elastic_limit << UTMIP_ELASTIC_LIMIT_SHIFT);
+	writel(val, &usbctlr->utmip_hsrx_cfg0);
+
+	/* Configure the UTMIP_HS_SYNC_START_DLY */
+	clrsetbits_le32(&usbctlr->utmip_hsrx_cfg1,
+		UTMIP_HS_SYNC_START_DLY_MASK,
+		utmip_hs_sync_start_delay << UTMIP_HS_SYNC_START_DLY_SHIFT);
+
+	/* Preceed the crystal clock disable by >100ns delay. */
+	udelay(1);
+
+	/* Resuscitate crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN */
+	setbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN);
+
+	/* Finished the per-controller init. */
+
+	/* De-assert UTMIP_RESET to bring out of reset. */
+	clrbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET);
+
+	/* Wait for the phy clock to become valid in 100 ms */
+	for (loop_count = 100000; loop_count != 0; loop_count--) {
+		if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID)
+			break;
+		udelay(1);
+	}
+}
+
+static void power_up_port(struct usb_ctlr *usbctlr)
+{
+	/* Deassert power down state */
+	clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_FORCE_PD_POWERDOWN |
+		UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN);
+	clrbits_le32(&usbctlr->utmip_xcvr_cfg1, UTMIP_FORCE_PDDISC_POWERDOWN |
+		UTMIP_FORCE_PDCHRP_POWERDOWN | UTMIP_FORCE_PDDR_POWERDOWN);
+}
+
+static void config_clock(const int params[])
+{
+	clock_start_pll(CLOCK_ID_USB,
+		params[PARAM_DIVM], params[PARAM_DIVN], params[PARAM_DIVP],
+		params[PARAM_CPCON], params[PARAM_LFCON]);
+}
+
+/**
+ * Add a new USB port to the list of available ports
+ *
+ * @param id		peripheral id of port (PERIPH_ID_USB3, for example)
+ * @param usbctlr	register address of controller
+ * @param params	timing parameters
+ * @param utmi		1 if it has an external UTMI transceiver
+ * @return 0 if ok, -1 if error (too many ports)
+ */
+static int add_port(enum periph_id id, struct usb_ctlr *usbctlr,
+		const int params[], int utmi)
+{
+	if (port_count == USB_PORTS_MAX) {
+		debug("tegrausb: Cannot register more than %d ports\n",
+		      USB_PORTS_MAX);
+		return -1;
+	}
+	init_usb_controller(id, usbctlr, params);
+	if (utmi) {
+		/* Disable ICUSB FS/LS transceiver */
+		clrbits_le32(&usbctlr->icusb_ctrl, IC_ENB1);
+
+		/* Select UTMI parallel interface */
+		clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK,
+				PTS_UTMI << PTS_SHIFT);
+		clrbits_le32(&usbctlr->port_sc1, STS);
+		power_up_port(usbctlr);
+	}
+	port[port_count++].reg = usbctlr;
+	return 0;
+}
+
+#ifndef CONFIG_OF_CONTROL
+static int probe_port(struct usb_ctlr *usbctlr, const int params[])
+{
+	enum periph_id id;
+	int utmi = 0;
+
+	/*
+	 * Get the periph id. Port 1 has an internal transceiver, port 3 is
+	 * external
+	 */
+	switch ((u32)usbctlr) {
+	case TEGRA_USB1_BASE:
+		id = PERIPH_ID_USBD;
+		break;
+
+	case TEGRA_USB3_BASE:
+		id = PERIPH_ID_USB3;
+		utmi = 1;
+		break;
+
+	default:
+		printf("tegrausb: probe_port: no such port %p\n", usbctlr);
+		return -1;
+	}
+
+	return add_port(id, usbctlr, params, utmi);
+}
+#endif
+
+int tegrausb_start_port(unsigned portnum, u32 *hccr, u32 *hcor)
+{
+	struct usb_ctlr *usbctlr;
+
+	if (portnum >= port_count)
+		return -1;
+	tegrausb_stop_port();
+
+	usbctlr = port[portnum].reg;
+	*hccr = (u32)&usbctlr->cap_length;
+	*hcor = (u32)&usbctlr->usb_cmd;
+	port_current = portnum;
+	return 0;
+}
+
+int tegrausb_stop_port(void)
+{
+	struct usb_ctlr *usbctlr;
+
+	if (port_current == -1)
+		return -1;
+
+	usbctlr = port[port_current].reg;
+
+	/* Stop controller */
+	writel(0, &usbctlr->usb_cmd);
+	udelay(1000);
+
+	/* Initiate controller reset */
+	writel(2, &usbctlr->usb_cmd);
+	udelay(1000);
+	port_current = -1;
+	return 0;
+}
+
+#ifdef CONFIG_OF_CONTROL
+int fdt_decode_usb(const void *blob, int node, unsigned osc_frequency_mhz,
+		   struct fdt_usb *config)
+{
+	int clk_node = 0, rate;
+
+	/* Find the parameters for our oscillator frequency */
+	do {
+		clk_node = fdt_node_offset_by_compatible(blob, clk_node,
+					"nvidia,tegra20-usbparams");
+		if (clk_node < 0) {
+			debug("Cannot find USB params for clock %u",
+			      osc_frequency_mhz);
+			return -FDT_ERR_NOTFOUND;
+		}
+		rate = fdtdec_get_int(blob, clk_node, "osc-frequency", 0);
+	} while (rate != osc_frequency_mhz);
+
+	config->reg = (struct usb_ctlr *)fdtdec_get_addr(blob, node, "reg");
+	config->host_mode = fdtdec_get_bool(blob, node, "support-host-mode");
+	config->utmi = fdtdec_lookup_phandle(blob, node, "utmi") >= 0;
+	config->enabled = fdtdec_get_is_enabled(blob, node);
+	config->periph_id = fdtdec_get_int(blob, node, "periph-id", -1);
+	if (config->periph_id == -1)
+		return -FDT_ERR_NOTFOUND;
+
+	return fdtdec_get_int_array(blob, clk_node, "params", config->params,
+			PARAM_COUNT);
+}
+#endif
+
+int board_usb_init(const void *blob)
+{
+#ifdef CONFIG_OF_CONTROL
+	struct fdt_usb config;
+	int clk_done = 0;
+	int node, upto = 0;
+	unsigned osc_freq = clock_get_rate(CLOCK_ID_OSC);
+
+	do {
+		node = fdtdec_next_alias(blob, "usb",
+					 COMPAT_NVIDIA_TEGRA20_USB, &upto);
+		if (node < 0)
+			break;
+		if (fdt_decode_usb(blob, node, osc_freq, &config))
+			return -1;
+		if (!config.enabled)
+			continue;
+
+		/* The first port we find gets to set the clocks */
+		if (!clk_done) {
+			config_clock(config.params);
+			clk_done = 1;
+		}
+		if (config.host_mode) {
+			/* Only one host-dev port is supported */
+			if (host_dev_ctlr)
+				return -1;
+			host_dev_ctlr = config.reg;
+		}
+		if (add_port(config.periph_id, config.reg, config.params,
+			    config.utmi))
+			return -1;
+	} while (node);
+#else
+	enum clock_osc_freq freq;
+	const int *params;
+
+	/* Get the Oscillator frequency */
+	freq = clock_get_osc_freq();
+
+	/* Enable PLL U for USB */
+	params = &usb_pll[freq][0];
+	config_clock(params);
+
+	/* Set up our two ports */
+#ifdef CONFIG_TEGRA_USB1_HOST
+	host_dev_ctlr = (struct usb_ctlr *)TEGRA_USB1_BASE;
+#endif
+	probe_port((struct usb_ctlr *)CONFIG_TEGRA_USB0, params);
+	probe_port((struct usb_ctlr *)CONFIG_TEGRA_USB1, params);
+#endif /* CONFIG_OF_CONTROL */
+	usb_set_host_mode();
+	port_current = -1;
+	return 0;
+}
diff --git a/arch/arm/include/asm/arch-tegra2/tegra2.h b/arch/arm/include/asm/arch-tegra2/tegra2.h
index 8941443..baae2eb 100644
--- a/arch/arm/include/asm/arch-tegra2/tegra2.h
+++ b/arch/arm/include/asm/arch-tegra2/tegra2.h
@@ -41,6 +41,8 @@ 
 #define TEGRA2_SPI_BASE		(NV_PA_APB_MISC_BASE + 0xC380)
 #define NV_PA_PMC_BASE		0x7000E400
 #define NV_PA_CSITE_BASE	0x70040000
+#define TEGRA_USB1_BASE		0xC5000000
+#define TEGRA_USB3_BASE		0xC5008000
 
 #define TEGRA2_SDRC_CS0		NV_PA_SDRAM_BASE
 #define LOW_LEVEL_SRAM_STACK	0x4000FFFC
diff --git a/arch/arm/include/asm/arch-tegra2/usb.h b/arch/arm/include/asm/arch-tegra2/usb.h
new file mode 100644
index 0000000..0a3056d
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra2/usb.h
@@ -0,0 +1,255 @@ 
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _TEGRA_USB_H_
+#define _TEGRA_USB_H_
+
+
+/* USB Controller (USBx_CONTROLLER_) regs */
+struct usb_ctlr {
+	/* 0x000 */
+	uint id;
+	uint reserved0;
+	uint host;
+	uint device;
+
+	/* 0x010 */
+	uint txbuf;
+	uint rxbuf;
+	uint reserved1[2];
+
+	/* 0x020 */
+	uint reserved2[56];
+
+	/* 0x100 */
+	u16 cap_length;
+	u16 hci_version;
+	uint hcs_params;
+	uint hcc_params;
+	uint reserved3[5];
+
+	/* 0x120 */
+	uint dci_version;
+	uint dcc_params;
+	uint reserved4[6];
+
+	/* 0x140 */
+	uint usb_cmd;
+	uint usb_sts;
+	uint usb_intr;
+	uint frindex;
+
+	/* 0x150 */
+	uint reserved5;
+	uint periodic_list_base;
+	uint async_list_addr;
+	uint async_tt_sts;
+
+	/* 0x160 */
+	uint burst_size;
+	uint tx_fill_tuning;
+	uint reserved6;   /* is this port_sc1 on some controllers? */
+	uint icusb_ctrl;
+
+	/* 0x170 */
+	uint ulpi_viewport;
+	uint reserved7;
+	uint endpt_nak;
+	uint endpt_nak_enable;
+
+	/* 0x180 */
+	uint reserved;
+	uint port_sc1;
+	uint reserved8[6];
+
+	/* 0x1a0 */
+	uint reserved9;
+	uint otgsc;
+	uint usb_mode;
+	uint endpt_setup_stat;
+
+	/* 0x1b0 */
+	uint reserved10[20];
+
+	/* 0x200 */
+	uint reserved11[0x80];
+
+	/* 0x400 */
+	uint susp_ctrl;
+	uint phy_vbus_sensors;
+	uint phy_vbus_wakeup_id;
+	uint phy_alt_vbus_sys;
+
+	/* 0x410 */
+	uint usb1_legacy_ctrl;
+	uint reserved12[3];
+
+	/* 0x420 */
+	uint reserved13[56];
+
+	/* 0x500 */
+	uint reserved14[64 * 3];
+
+	/* 0x800 */
+	uint utmip_pll_cfg0;
+	uint utmip_pll_cfg1;
+	uint utmip_xcvr_cfg0;
+	uint utmip_bias_cfg0;
+
+	/* 0x810 */
+	uint utmip_hsrx_cfg0;
+	uint utmip_hsrx_cfg1;
+	uint utmip_fslsrx_cfg0;
+	uint utmip_fslsrx_cfg1;
+
+	/* 0x820 */
+	uint utmip_tx_cfg0;
+	uint utmip_misc_cfg0;
+	uint utmip_misc_cfg1;
+	uint utmip_debounce_cfg0;
+
+	/* 0x830 */
+	uint utmip_bat_chrg_cfg0;
+	uint utmip_spare_cfg0;
+	uint utmip_xcvr_cfg1;
+	uint utmip_bias_cfg1;
+};
+
+
+/* USB1_LEGACY_CTRL */
+#define USB1_NO_LEGACY_MODE		1
+
+#define VBUS_SENSE_CTL_SHIFT			1
+#define VBUS_SENSE_CTL_MASK			(3 << VBUS_SENSE_CTL_SHIFT)
+#define VBUS_SENSE_CTL_VBUS_WAKEUP		0
+#define VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP	1
+#define VBUS_SENSE_CTL_AB_SESS_VLD		2
+#define VBUS_SENSE_CTL_A_SESS_VLD		3
+
+/* USBx_IF_USB_SUSP_CTRL_0 */
+#define UTMIP_PHY_ENB			        (1 << 12)
+#define UTMIP_RESET			        (1 << 11)
+#define USB_PHY_CLK_VALID			(1 << 7)
+
+/* USBx_UTMIP_MISC_CFG1 */
+#define UTMIP_PLLU_STABLE_COUNT_SHIFT		6
+#define UTMIP_PLLU_STABLE_COUNT_MASK		\
+				(0xfff << UTMIP_PLLU_STABLE_COUNT_SHIFT)
+#define UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT	18
+#define UTMIP_PLL_ACTIVE_DLY_COUNT_MASK		\
+				(0x1f << UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT)
+#define UTMIP_PHY_XTAL_CLOCKEN			(1 << 30)
+
+/* USBx_UTMIP_PLL_CFG1_0 */
+#define UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT	27
+#define UTMIP_PLLU_ENABLE_DLY_COUNT_MASK	\
+				(0xf << UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT)
+#define UTMIP_XTAL_FREQ_COUNT_SHIFT		0
+#define UTMIP_XTAL_FREQ_COUNT_MASK		0xfff
+
+/* USBx_UTMIP_BIAS_CFG1_0 */
+#define UTMIP_BIAS_PDTRK_COUNT_SHIFT		3
+#define UTMIP_BIAS_PDTRK_COUNT_MASK		\
+				(0x1f << UTMIP_BIAS_PDTRK_COUNT_SHIFT)
+#define UTMIP_BIAS_PDTRK_COUNT_SHIFT		3
+#define UTMIP_BIAS_PDTRK_COUNT_MASK		\
+				(0x1f << UTMIP_BIAS_PDTRK_COUNT_SHIFT)
+
+#define UTMIP_DEBOUNCE_CFG0_SHIFT		0
+#define UTMIP_DEBOUNCE_CFG0_MASK		0xffff
+
+/* USBx_UTMIP_TX_CFG0_0 */
+#define UTMIP_FS_PREAMBLE_J			(1 << 19)
+
+/* USBx_UTMIP_BAT_CHRG_CFG0_0 */
+#define UTMIP_PD_CHRG				1
+
+/* USBx_UTMIP_XCVR_CFG0_0 */
+#define UTMIP_XCVR_LSBIAS_SE			(1 << 21)
+
+/* USBx_UTMIP_SPARE_CFG0_0 */
+#define FUSE_SETUP_SEL				(1 << 3)
+
+/* USBx_UTMIP_HSRX_CFG0_0 */
+#define UTMIP_IDLE_WAIT_SHIFT			15
+#define UTMIP_IDLE_WAIT_MASK			(0x1f << UTMIP_IDLE_WAIT_SHIFT)
+#define UTMIP_ELASTIC_LIMIT_SHIFT		10
+#define UTMIP_ELASTIC_LIMIT_MASK		\
+				(0x1f << UTMIP_ELASTIC_LIMIT_SHIFT)
+
+/* USBx_UTMIP_HSRX_CFG0_1 */
+#define UTMIP_HS_SYNC_START_DLY_SHIFT		1
+#define UTMIP_HS_SYNC_START_DLY_MASK		\
+				(0xf << UTMIP_HS_SYNC_START_DLY_SHIFT)
+
+/* USBx_CONTROLLER_2_USB2D_ICUSB_CTRL_0 */
+#define IC_ENB1					(1 << 3)
+
+/* SB2_CONTROLLER_2_USB2D_PORTSC1_0 */
+#define PTS_SHIFT				30
+#define PTS_MASK				(3 << PTS_SHIFT)
+#define PTS_UTMI	0
+#define PTS_RESERVED	1
+#define PTS_ULP		2
+#define PTS_ICUSB_SER	3
+
+#define STS					(1 << 29)
+
+/* USBx_UTMIP_XCVR_CFG0_0 */
+#define UTMIP_FORCE_PD_POWERDOWN		(1 << 14)
+#define UTMIP_FORCE_PD2_POWERDOWN		(1 << 16)
+#define UTMIP_FORCE_PDZI_POWERDOWN		(1 << 18)
+
+/* USBx_UTMIP_XCVR_CFG1_0 */
+#define UTMIP_FORCE_PDDISC_POWERDOWN		(1 << 0)
+#define UTMIP_FORCE_PDCHRP_POWERDOWN		(1 << 2)
+#define UTMIP_FORCE_PDDR_POWERDOWN		(1 << 4)
+
+/* USB3_IF_USB_PHY_VBUS_SENSORS_0 */
+#define VBUS_VLD_STS			(1 << 26)
+
+
+/* Change the USB host port into host mode */
+void usb_set_host_mode(void);
+
+/* Setup USB on the board */
+int board_usb_init(const void *blob);
+
+/**
+ * Start up the given port number (ports are numbered from 0 on each board).
+ * This returns values for the appropriate hccr and hcor addresses to use for
+ * USB EHCI operations.
+ *
+ * @param portnum	port number to start
+ * @param hccr		returns start address of EHCI HCCR registers
+ * @param hcor		returns start address of EHCI HCOR registers
+ * @return 0 if ok, -1 on error (generally invalid port number)
+ */
+int tegrausb_start_port(unsigned portnum, u32 *hccr, u32 *hcor);
+
+/**
+ * Stop the current port
+ *
+ * @return 0 if ok, -1 if no port was active
+ */
+int tegrausb_stop_port(void);
+
+#endif	/* _TEGRA_USB_H_ */
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 09abb75..39134ff 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -46,6 +46,7 @@  COBJS-$(CONFIG_USB_EHCI_PPC4XX) += ehci-ppc4xx.o
 COBJS-$(CONFIG_USB_EHCI_IXP4XX) += ehci-ixp.o
 COBJS-$(CONFIG_USB_EHCI_KIRKWOOD) += ehci-kirkwood.o
 COBJS-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o
+COBJS-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o
 COBJS-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o
 
 COBJS	:= $(COBJS-y)
diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c
new file mode 100644
index 0000000..3a48c26
--- /dev/null
+++ b/drivers/usb/host/ehci-tegra.c
@@ -0,0 +1,63 @@ 
+/*
+ * Copyright (c) 2009 NVIDIA Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <usb.h>
+
+#include "ehci.h"
+#include "ehci-core.h"
+
+#include <asm/errno.h>
+#include <asm/arch/usb.h>
+
+
+/*
+ * Create the appropriate control structures to manage
+ * a new EHCI host controller.
+ */
+int ehci_hcd_init(void)
+{
+	u32 our_hccr, our_hcor;
+
+	/*
+	 * Select the first port, as we don't have a way of selecting others
+	 * yet
+	 */
+	if (tegrausb_start_port(0, &our_hccr, &our_hcor))
+		return -1;
+
+	hccr = (struct ehci_hccr *)our_hccr;
+	hcor = (struct ehci_hcor *)our_hcor;
+
+	return 0;
+}
+
+/*
+ * Destroy the appropriate control structures corresponding
+ * the the EHCI host controller.
+ */
+int ehci_hcd_stop(void)
+{
+	usb_set_host_mode();
+	tegrausb_stop_port();
+	return 0;
+}
diff --git a/include/fdtdec.h b/include/fdtdec.h
index 9ecb6ab..f1734c4 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -57,6 +57,7 @@  struct fdt_memory {
  */
 enum fdt_compat_id {
 	COMPAT_UNKNOWN,
+	COMPAT_NVIDIA_TEGRA20_USB,	/* Tegra2 USB port */
 
 	COMPAT_COUNT,
 };
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 613547a..0213f08 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -34,6 +34,7 @@  DECLARE_GLOBAL_DATA_PTR;
 #define COMPAT(id, name) name
 static const char * const compat_names[COMPAT_COUNT] = {
 	COMPAT(UNKNOWN, "<none>"),
+	COMPAT(NVIDIA_TEGRA20_USB, "nvidia,tegra20-usb"),
 };
 
 /**