From patchwork Tue Nov 22 16:31:58 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Benoit Canet X-Patchwork-Id: 127123 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 74E4E1007D1 for ; Wed, 23 Nov 2011 03:33:01 +1100 (EST) Received: from localhost ([::1]:58273 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RStHD-0003e2-Lp for incoming@patchwork.ozlabs.org; Tue, 22 Nov 2011 11:32:55 -0500 Received: from eggs.gnu.org ([140.186.70.92]:53831) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RStGd-0002Kb-7x for qemu-devel@nongnu.org; Tue, 22 Nov 2011 11:32:25 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RStGY-0003wS-ET for qemu-devel@nongnu.org; Tue, 22 Nov 2011 11:32:19 -0500 Received: from mail-fx0-f45.google.com ([209.85.161.45]:43544) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RStGY-0003vV-4J for qemu-devel@nongnu.org; Tue, 22 Nov 2011 11:32:14 -0500 Received: by mail-fx0-f45.google.com with SMTP id s14so658323faa.4 for ; Tue, 22 Nov 2011 08:32:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :mime-version:content-type:content-transfer-encoding; bh=m36o8d3xTQmxl6mJXjj03SziD03hPh0PwWLTckxT+c4=; b=JDyI/3AFH/9US/MBj2ezNUgc1QzgEc1tXotsLOcVRJZFmqL8okWDUJpL6ue7UV6Zn9 26BHEQzyHrSmEI3fZpja4fCgDtSE0FoiGKY9vFZ0S/7Z55IcJiG19xedDAemDLB2665N OJaWWmq7mfA+BrMzg/A9PvtX8HrPzprq5t7OI= Received: by 10.180.90.148 with SMTP id bw20mr23987016wib.33.1321979533452; Tue, 22 Nov 2011 08:32:13 -0800 (PST) Received: from Laure.box.in.chocolate-blue.net ([109.190.18.76]) by mx.google.com with ESMTPS id z3sm5677843wid.11.2011.11.22.08.32.12 (version=SSLv3 cipher=OTHER); Tue, 22 Nov 2011 08:32:12 -0800 (PST) From: =?UTF-8?q?Beno=C3=AEt=20Canet?= To: qemu-devel@nongnu.org Date: Tue, 22 Nov 2011 17:31:58 +0100 Message-Id: <1321979527-23921-3-git-send-email-benoit.canet@gmail.com> X-Mailer: git-send-email 1.7.7.3 In-Reply-To: <1321979527-23921-1-git-send-email-benoit.canet@gmail.com> References: <1321979527-23921-1-git-send-email-benoit.canet@gmail.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 209.85.161.45 Cc: =?UTF-8?q?Beno=C3=AEt=20Canet?= , avi@redhat.com Subject: [Qemu-devel] [PATCH v2 02/11] mcf_uart: convert to memory API X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Benoît Canet --- hw/mcf.h | 11 +++++++---- hw/mcf5206.c | 25 +++++++++++++------------ hw/mcf5208.c | 6 +++--- hw/mcf_uart.c | 34 +++++++++++++++------------------- 4 files changed, 38 insertions(+), 38 deletions(-) diff --git a/hw/mcf.h b/hw/mcf.h index 572424d..e2f6727 100644 --- a/hw/mcf.h +++ b/hw/mcf.h @@ -5,11 +5,14 @@ struct MemoryRegion; /* mcf_uart.c */ -uint32_t mcf_uart_read(void *opaque, target_phys_addr_t addr); -void mcf_uart_write(void *opaque, target_phys_addr_t addr, uint32_t val); +uint64_t mcf_uart_read(void *opaque, target_phys_addr_t addr, + unsigned size); +void mcf_uart_write(void *opaque, target_phys_addr_t addr, + uint64_t val, unsigned size); void *mcf_uart_init(qemu_irq irq, CharDriverState *chr); -void mcf_uart_mm_init(target_phys_addr_t base, qemu_irq irq, - CharDriverState *chr); +void mcf_uart_mm_init(struct MemoryRegion *sysmem, + target_phys_addr_t base, + qemu_irq irq, CharDriverState *chr); /* mcf_intc.c */ qemu_irq *mcf_intc_init(target_phys_addr_t base, CPUState *env); diff --git a/hw/mcf5206.c b/hw/mcf5206.c index 987687d..7b6d501 100644 --- a/hw/mcf5206.c +++ b/hw/mcf5206.c @@ -263,16 +263,17 @@ static void m5206_mbar_reset(m5206_mbar_state *s) s->par = 0; } -static uint32_t m5206_mbar_read(m5206_mbar_state *s, uint32_t offset) +static uint64_t m5206_mbar_read(m5206_mbar_state *s, + uint64_t offset, unsigned size) { if (offset >= 0x100 && offset < 0x120) { return m5206_timer_read(s->timer[0], offset - 0x100); } else if (offset >= 0x120 && offset < 0x140) { return m5206_timer_read(s->timer[1], offset - 0x120); } else if (offset >= 0x140 && offset < 0x160) { - return mcf_uart_read(s->uart[0], offset - 0x140); + return mcf_uart_read(s->uart[0], offset - 0x140, size); } else if (offset >= 0x180 && offset < 0x1a0) { - return mcf_uart_read(s->uart[1], offset - 0x180); + return mcf_uart_read(s->uart[1], offset - 0x180, size); } switch (offset) { case 0x03: return s->scr; @@ -301,7 +302,7 @@ static uint32_t m5206_mbar_read(m5206_mbar_state *s, uint32_t offset) } static void m5206_mbar_write(m5206_mbar_state *s, uint32_t offset, - uint32_t value) + uint64_t value, unsigned size) { if (offset >= 0x100 && offset < 0x120) { m5206_timer_write(s->timer[0], offset - 0x100, value); @@ -310,10 +311,10 @@ static void m5206_mbar_write(m5206_mbar_state *s, uint32_t offset, m5206_timer_write(s->timer[1], offset - 0x120, value); return; } else if (offset >= 0x140 && offset < 0x160) { - mcf_uart_write(s->uart[0], offset - 0x140, value); + mcf_uart_write(s->uart[0], offset - 0x140, value, size); return; } else if (offset >= 0x180 && offset < 0x1a0) { - mcf_uart_write(s->uart[1], offset - 0x180, value); + mcf_uart_write(s->uart[1], offset - 0x180, value, size); return; } switch (offset) { @@ -387,7 +388,7 @@ static uint32_t m5206_mbar_readb(void *opaque, target_phys_addr_t offset) } return val & 0xff; } - return m5206_mbar_read(s, offset); + return m5206_mbar_read(s, offset, 1); } static uint32_t m5206_mbar_readw(void *opaque, target_phys_addr_t offset) @@ -411,7 +412,7 @@ static uint32_t m5206_mbar_readw(void *opaque, target_phys_addr_t offset) val |= m5206_mbar_readb(opaque, offset + 1); return val; } - return m5206_mbar_read(s, offset); + return m5206_mbar_read(s, offset, 2); } static uint32_t m5206_mbar_readl(void *opaque, target_phys_addr_t offset) @@ -429,7 +430,7 @@ static uint32_t m5206_mbar_readl(void *opaque, target_phys_addr_t offset) val |= m5206_mbar_readw(opaque, offset + 2); return val; } - return m5206_mbar_read(s, offset); + return m5206_mbar_read(s, offset, 4); } static void m5206_mbar_writew(void *opaque, target_phys_addr_t offset, @@ -458,7 +459,7 @@ static void m5206_mbar_writeb(void *opaque, target_phys_addr_t offset, m5206_mbar_writew(opaque, offset & ~1, tmp); return; } - m5206_mbar_write(s, offset, value); + m5206_mbar_write(s, offset, value, 1); } static void m5206_mbar_writew(void *opaque, target_phys_addr_t offset, @@ -486,7 +487,7 @@ static void m5206_mbar_writew(void *opaque, target_phys_addr_t offset, m5206_mbar_writeb(opaque, offset + 1, value & 0xff); return; } - m5206_mbar_write(s, offset, value); + m5206_mbar_write(s, offset, value, 2); } static void m5206_mbar_writel(void *opaque, target_phys_addr_t offset, @@ -504,7 +505,7 @@ static void m5206_mbar_writel(void *opaque, target_phys_addr_t offset, m5206_mbar_writew(opaque, offset + 2, value & 0xffff); return; } - m5206_mbar_write(s, offset, value); + m5206_mbar_write(s, offset, value, 4); } static const MemoryRegionOps m5206_mbar_ops = { diff --git a/hw/mcf5208.c b/hw/mcf5208.c index 1c2c0c4..0119430 100644 --- a/hw/mcf5208.c +++ b/hw/mcf5208.c @@ -223,9 +223,9 @@ static void mcf5208evb_init(ram_addr_t ram_size, /* Internal peripherals. */ pic = mcf_intc_init(0xfc048000, env); - mcf_uart_mm_init(0xfc060000, pic[26], serial_hds[0]); - mcf_uart_mm_init(0xfc064000, pic[27], serial_hds[1]); - mcf_uart_mm_init(0xfc068000, pic[28], serial_hds[2]); + mcf_uart_mm_init(address_space_mem, 0xfc060000, pic[26], serial_hds[0]); + mcf_uart_mm_init(address_space_mem, 0xfc064000, pic[27], serial_hds[1]); + mcf_uart_mm_init(address_space_mem, 0xfc068000, pic[28], serial_hds[2]); mcf5208_sys_init(address_space_mem, pic); diff --git a/hw/mcf_uart.c b/hw/mcf_uart.c index e6b2ab0..ec6a87f 100644 --- a/hw/mcf_uart.c +++ b/hw/mcf_uart.c @@ -8,8 +8,10 @@ #include "hw.h" #include "mcf.h" #include "qemu-char.h" +#include "exec-memory.h" typedef struct { + MemoryRegion iomem; uint8_t mr[2]; uint8_t sr; uint8_t isr; @@ -64,7 +66,8 @@ static void mcf_uart_update(mcf_uart_state *s) qemu_set_irq(s->irq, (s->isr & s->imr) != 0); } -uint32_t mcf_uart_read(void *opaque, target_phys_addr_t addr) +uint64_t mcf_uart_read(void *opaque, target_phys_addr_t addr, + unsigned size) { mcf_uart_state *s = (mcf_uart_state *)opaque; switch (addr & 0x3f) { @@ -182,7 +185,8 @@ static void mcf_do_command(mcf_uart_state *s, uint8_t cmd) } } -void mcf_uart_write(void *opaque, target_phys_addr_t addr, uint32_t val) +void mcf_uart_write(void *opaque, target_phys_addr_t addr, + uint64_t val, unsigned size) { mcf_uart_state *s = (mcf_uart_state *)opaque; switch (addr & 0x3f) { @@ -283,28 +287,20 @@ void *mcf_uart_init(qemu_irq irq, CharDriverState *chr) return s; } - -static CPUReadMemoryFunc * const mcf_uart_readfn[] = { - mcf_uart_read, - mcf_uart_read, - mcf_uart_read -}; - -static CPUWriteMemoryFunc * const mcf_uart_writefn[] = { - mcf_uart_write, - mcf_uart_write, - mcf_uart_write +static const MemoryRegionOps mcf_uart_ops = { + .read = mcf_uart_read, + .write = mcf_uart_write, + .endianness = DEVICE_NATIVE_ENDIAN, }; -void mcf_uart_mm_init(target_phys_addr_t base, qemu_irq irq, +void mcf_uart_mm_init(MemoryRegion *sysmem, + target_phys_addr_t base, + qemu_irq irq, CharDriverState *chr) { mcf_uart_state *s; - int iomemtype; s = mcf_uart_init(irq, chr); - iomemtype = cpu_register_io_memory(mcf_uart_readfn, - mcf_uart_writefn, s, - DEVICE_NATIVE_ENDIAN); - cpu_register_physical_memory(base, 0x40, iomemtype); + memory_region_init_io(&s->iomem, &mcf_uart_ops, s, "uart", 0x40); + memory_region_add_subregion(sysmem, base, &s->iomem); }