diff mbox

[ARM] Fix sp804 dual-timer

Message ID w4aa7on8j4.wl%peter@chubb.wattle.id.au
State New
Headers show

Commit Message

Peter Chubb Nov. 22, 2011, 3:25 a.m. UTC 
Properly implement dual-timer read/write for the sp804 dual timer module.
Based on ARM specs at
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0271d/index.html

Signed-off-by: Hans Jang <hsjang@ok-labs.com>
Signed-off-by: David Mirabito <david.mirabito@nicta.com.au>
Signed-off-by: Peter Chubb <peter.chubb@nicta.com.au>

---
 hw/arm_timer.c |   41 +++++++++++++++++++++++++++++++++++------
 1 file changed, 35 insertions(+), 6 deletions(-)


--
Dr Peter Chubb  http://www.gelato.unsw.edu.au  peterc AT gelato.unsw.edu.au
http://www.ertos.nicta.com.au           ERTOS within National ICT Australia

Comments

Peter Maydell Nov. 24, 2011, 5:46 p.m. UTC | #1 
On 22 November 2011 03:25, Peter Chubb <peter.chubb@nicta.com.au> wrote:
> Properly implement dual-timer read/write for the sp804 dual timer module.
> Based on ARM specs at
> http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0271d/index.html
>
> Signed-off-by: Hans Jang <hsjang@ok-labs.com>
> Signed-off-by: David Mirabito <david.mirabito@nicta.com.au>
> Signed-off-by: Peter Chubb <peter.chubb@nicta.com.au>

I'm not hugely happy about the hw_error()s but it's not making the
problem worse and we don't really have anything better to use
instead, so I'll let that pass.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

(and put into my arm-devs.next queue)

-- PMM
diff mbox

Patch

Index: qemu-working/hw/arm_timer.c
===================================================================
--- qemu-working.orig/hw/arm_timer.c	2011-11-22 14:21:50.873221242 +1100
+++ qemu-working/hw/arm_timer.c	2011-11-22 14:22:21.986129734 +1100
@@ -163,64 +163,93 @@  static arm_timer_state *arm_timer_init(u
     s->freq = freq;
     s->control = TIMER_CTRL_IE;
 
     bh = qemu_bh_new(arm_timer_tick, s);
     s->timer = ptimer_init(bh);
     vmstate_register(NULL, -1, &vmstate_arm_timer, s);
     return s;
 }
 
 /* ARM PrimeCell SP804 dual timer module.
-   Docs for this device don't seem to be publicly available.  This
-   implementation is based on guesswork, the linux kernel sources and the
-   Integrator/CP timer modules.  */
+ * Docs at
+ * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0271d/index.html
+*/
 
 typedef struct {
     SysBusDevice busdev;
     MemoryRegion iomem;
     arm_timer_state *timer[2];
     int level[2];
     qemu_irq irq;
 } sp804_state;
 
+static const uint8_t sp804_ids[] = {
+    /* Timer ID */
+    0x04, 0x18, 0x14, 0,
+    /* PrimeCell ID */
+    0xd, 0xf0, 0x05, 0xb1
+};
+
 /* Merge the IRQs from the two component devices.  */
 static void sp804_set_irq(void *opaque, int irq, int level)
 {
     sp804_state *s = (sp804_state *)opaque;
 
     s->level[irq] = level;
     qemu_set_irq(s->irq, s->level[0] || s->level[1]);
 }
 
 static uint64_t sp804_read(void *opaque, target_phys_addr_t offset,
                            unsigned size)
 {
     sp804_state *s = (sp804_state *)opaque;
 
-    /* ??? Don't know the PrimeCell ID for this device.  */
     if (offset < 0x20) {
         return arm_timer_read(s->timer[0], offset);
-    } else {
+    }
+    if (offset < 0x40) {
         return arm_timer_read(s->timer[1], offset - 0x20);
     }
+
+    /* TimerPeriphID */
+    if (offset >= 0xfe0 && offset <= 0xffc) {
+        return sp804_ids[(offset - 0xfe0) >> 2];
+    }
+
+    switch (offset) {
+    /* Integration Test control registers, which we won't support */
+    case 0xf00: /* TimerITCR */
+    case 0xf04: /* TimerITOP (strictly write only but..) */
+        return 0;
+    }
+
+    hw_error("%s: Bad offset %x\n", __func__, (int)offset);
+    return 0;
 }
 
 static void sp804_write(void *opaque, target_phys_addr_t offset,
                         uint64_t value, unsigned size)
 {
     sp804_state *s = (sp804_state *)opaque;
 
     if (offset < 0x20) {
         arm_timer_write(s->timer[0], offset, value);
-    } else {
+        return;
+    }
+
+    if (offset < 0x40) {
         arm_timer_write(s->timer[1], offset - 0x20, value);
+        return;
     }
+
+    /* Technically we could be writing to the Test Registers, but not likely */
+    hw_error("%s: Bad offset %x\n", __func__, (int)offset);
 }
 
 static const MemoryRegionOps sp804_ops = {
     .read = sp804_read,
     .write = sp804_write,
     .endianness = DEVICE_NATIVE_ENDIAN,
 };
 
 static const VMStateDescription vmstate_sp804 = {
     .name = "sp804",