Patchwork [U-Boot] powerpc/85xx: Add workaround for erratum A-003474

login
register
mail settings
Submitter York Sun
Date Nov. 20, 2011, 6:01 p.m.
Message ID <1321812095-22119-1-git-send-email-yorksun@freescale.com>
Download mbox | patch
Permalink /patch/126657/
State Accepted
Delegated to: Kumar Gala
Headers show

Comments

York Sun - Nov. 20, 2011, 6:01 p.m.
Erratum A-003474: Internal DDR calibration circuit is not supported

Impact:
Experience shows no significant benefit to device operation with
auto-calibration enabled versus it disabled. To ensure consistent timing
results, Freescale recommends this feature be disabled in future customer
products. There should be no impact to parts that are already operating
in the field.

Workaround:
Prior to setting DDR_SDRAM_CFG[MEM_EN]=1, do the following:
1. Write a value of 0x0000_0015 to the register at offset
	CCSRBAR + DDR OFFSET + 0xf30
2. Write a value of 0x2400_0000 to the register at offset
	CCSRBAR + DDR OFFSET + 0xf54

Signed-off-by: York Sun <yorksun@freescale.com>
---
 arch/powerpc/cpu/mpc85xx/cmd_errata.c     |    3 +++
 arch/powerpc/cpu/mpc85xx/ddr-gen3.c       |    5 +++++
 arch/powerpc/include/asm/config_mpc85xx.h |    7 +++++++
 3 files changed, 15 insertions(+), 0 deletions(-)
Kumar Gala - Nov. 29, 2011, 3:06 p.m.
On Nov 20, 2011, at 12:01 PM, York Sun wrote:

> Erratum A-003474: Internal DDR calibration circuit is not supported
> 
> Impact:
> Experience shows no significant benefit to device operation with
> auto-calibration enabled versus it disabled. To ensure consistent timing
> results, Freescale recommends this feature be disabled in future customer
> products. There should be no impact to parts that are already operating
> in the field.
> 
> Workaround:
> Prior to setting DDR_SDRAM_CFG[MEM_EN]=1, do the following:
> 1. Write a value of 0x0000_0015 to the register at offset
> 	CCSRBAR + DDR OFFSET + 0xf30
> 2. Write a value of 0x2400_0000 to the register at offset
> 	CCSRBAR + DDR OFFSET + 0xf54
> 
> Signed-off-by: York Sun <yorksun@freescale.com>
> ---
> arch/powerpc/cpu/mpc85xx/cmd_errata.c     |    3 +++
> arch/powerpc/cpu/mpc85xx/ddr-gen3.c       |    5 +++++
> arch/powerpc/include/asm/config_mpc85xx.h |    7 +++++++
> 3 files changed, 15 insertions(+), 0 deletions(-)

applied to 85xx

- k

Patch

diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index f7c0934..1da5fe4 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -56,6 +56,9 @@  static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 #if defined(CONFIG_SYS_FSL_ERRATUM_CPU_A003999)
 	puts("Work-around for Erratum CPU-A003999 enabled\n");
 #endif
+#if defined(CONFIG_SYS_FSL_ERRATUM_DDR_A003474)
+	puts("Work-around for Erratum DDR-A003473 enabled\n");
+#endif
 #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN)
 	puts("Work-around for DDR MSYNC_IN Erratum enabled\n");
 #endif
diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
index c8c84a1..18e9cc5 100644
--- a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
+++ b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
@@ -115,6 +115,11 @@  void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 	for (i = 0; i < 32; i++)
 		out_be32(&ddr->debug[i], regs->debug[i]);
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003474
+	out_be32(&ddr->debug[12], 0x00000015);
+	out_be32(&ddr->debug[21], 0x24000000);
+#endif /* CONFIG_SYS_FSL_ERRATUM_DDR_A003474 */
+
 	/* Set, but do not enable the memory */
 	temp_sdram_cfg = regs->ddr_sdram_cfg;
 	temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN);
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index dba9eda..2d73458 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -317,6 +317,7 @@ 
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_SYS_FSL_ERRATUM_USB138
 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
+#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
 
 #elif defined(CONFIG_PPC_P2041)
 #define CONFIG_MAX_CPUS			4
@@ -337,6 +338,7 @@ 
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_SYS_FSL_ERRATUM_USB138
 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
+#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
 
 #elif defined(CONFIG_PPC_P3041)
 #define CONFIG_MAX_CPUS			4
@@ -357,6 +359,7 @@ 
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_SYS_FSL_ERRATUM_USB138
 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
+#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
 
 #elif defined(CONFIG_PPC_P3060)
 #define CONFIG_MAX_CPUS			8
@@ -384,6 +387,7 @@ 
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,p4080-pcie"
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
+#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
 
 #elif defined(CONFIG_PPC_P4080)
 #define CONFIG_MAX_CPUS			8
@@ -413,6 +417,7 @@ 
 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A001
 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005
 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
+#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
 
 /* P5010 is single core version of P5020 */
 #elif defined(CONFIG_PPC_P5010)
@@ -433,6 +438,7 @@ 
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_SYS_FSL_ERRATUM_USB138
+#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
 
 #elif defined(CONFIG_PPC_P5020)
 #define CONFIG_MAX_CPUS			2
@@ -452,6 +458,7 @@ 
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_SYS_FSL_ERRATUM_USB138
+#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
 
 #else
 #error Processor type not defined for this platform