| Message ID | 20200401210941.GM2212@tucnak |
|---|---|
| State | New |
| Headers | show |
| Series | aarch64: Fix ICE due to aarch64_gen_compare_reg_maybe_ze [PR94435] | expand |
Jakub Jelinek <jakub@redhat.com> writes: > Hi! > > The following testcase ICEs, because aarch64_gen_compare_reg_maybe_ze emits > invalid RTL. > For y_mode [QH]Imode it expects y to be of that mode (or CONST_INT that fits > into that mode) and x being SImode; for non-CONST_INT y it zero extends y > into SImode and compares that against x, for CONST_INT y it zero extends y > into SImode. The problem is that when the zero extended constant isn't > usable directly, it forces it into a REG, but with y_mode mode, and then > compares against y. That is wrong, because it should force it into a SImode > REG and compare that way. > > The following patch fixes that, bootstrapped/regtested on aarch64-linux, ok > for trunk? > > 2020-04-01 Jakub Jelinek <jakub@redhat.com> > > PR target/94435 > * config/aarch64/aarch64.c (aarch64_gen_compare_reg_maybe_ze): For > y_mode E_[QH]Imode and y being a CONST_INT, change y_mode to SImode. > > * gcc.target/aarch64/pr94435.c: New test. OK, thanks. Richard > > --- gcc/config/aarch64/aarch64.c.jj 2020-03-30 17:02:28.000000000 +0200 > +++ gcc/config/aarch64/aarch64.c 2020-04-01 11:32:48.877900235 +0200 > @@ -2371,7 +2371,10 @@ aarch64_gen_compare_reg_maybe_ze (RTX_CO > if (y_mode == E_QImode || y_mode == E_HImode) > { > if (CONST_INT_P (y)) > - y = GEN_INT (INTVAL (y) & GET_MODE_MASK (y_mode)); > + { > + y = GEN_INT (INTVAL (y) & GET_MODE_MASK (y_mode)); > + y_mode = SImode; > + } > else > { > rtx t, cc_reg; > --- gcc/testsuite/gcc.target/aarch64/pr94435.c.jj 2020-04-01 11:36:21.172797217 +0200 > +++ gcc/testsuite/gcc.target/aarch64/pr94435.c 2020-04-01 11:36:36.493573280 +0200 > @@ -0,0 +1,25 @@ > +/* PR target/94435 */ > +/* { dg-do compile } */ > +/* { dg-options "-march=armv8-a+nolse -moutline-atomics" } */ > + > +int b, c, d, e, f, h; > +short g; > +int foo (int) __attribute__ ((__const__)); > + > +void > +bar (void) > +{ > + while (1) > + { > + while (1) > + { > + __atomic_load_n (&e, 0); > + if (foo (2)) > + __sync_val_compare_and_swap (&c, 0, f); > + b = 1; > + if (h == e) > + break; > + } > + __sync_val_compare_and_swap (&g, -1, f); > + } > +} > > Jakub
--- gcc/config/aarch64/aarch64.c.jj 2020-03-30 17:02:28.000000000 +0200 +++ gcc/config/aarch64/aarch64.c 2020-04-01 11:32:48.877900235 +0200 @@ -2371,7 +2371,10 @@ aarch64_gen_compare_reg_maybe_ze (RTX_CO if (y_mode == E_QImode || y_mode == E_HImode) { if (CONST_INT_P (y)) - y = GEN_INT (INTVAL (y) & GET_MODE_MASK (y_mode)); + { + y = GEN_INT (INTVAL (y) & GET_MODE_MASK (y_mode)); + y_mode = SImode; + } else { rtx t, cc_reg; --- gcc/testsuite/gcc.target/aarch64/pr94435.c.jj 2020-04-01 11:36:21.172797217 +0200 +++ gcc/testsuite/gcc.target/aarch64/pr94435.c 2020-04-01 11:36:36.493573280 +0200 @@ -0,0 +1,25 @@ +/* PR target/94435 */ +/* { dg-do compile } */ +/* { dg-options "-march=armv8-a+nolse -moutline-atomics" } */ + +int b, c, d, e, f, h; +short g; +int foo (int) __attribute__ ((__const__)); + +void +bar (void) +{ + while (1) + { + while (1) + { + __atomic_load_n (&e, 0); + if (foo (2)) + __sync_val_compare_and_swap (&c, 0, f); + b = 1; + if (h == e) + break; + } + __sync_val_compare_and_swap (&g, -1, f); + } +}