From patchwork Fri Nov 18 22:48:07 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tom Rini X-Patchwork-Id: 126498 X-Patchwork-Delegate: s-paulraj@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 7D58DB721A for ; Sat, 19 Nov 2011 09:51:52 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id C754D28A93; Fri, 18 Nov 2011 23:51:31 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id jJTYOhDRwx0o; Fri, 18 Nov 2011 23:51:31 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 7DFBF289F2; Fri, 18 Nov 2011 23:50:32 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 342472894F for ; Fri, 18 Nov 2011 23:50:14 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id tOOEO05TuGxB for ; Fri, 18 Nov 2011 23:50:13 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from devils.ext.ti.com (devils.ext.ti.com [198.47.26.153]) by theia.denx.de (Postfix) with ESMTPS id DE73828905 for ; Fri, 18 Nov 2011 23:50:00 +0100 (CET) Received: from dbdp20.itg.ti.com ([172.24.170.38]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id pAIMnuuM020085 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Fri, 18 Nov 2011 16:49:58 -0600 Received: from DBDE71.ent.ti.com (localhost [127.0.0.1]) by dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id pAIMnuOk004813 for ; Sat, 19 Nov 2011 04:19:56 +0530 (IST) Received: from dbdp31.itg.ti.com (172.24.170.98) by DBDE71.ent.ti.com (172.24.170.149) with Microsoft SMTP Server id 14.1.323.3; Sat, 19 Nov 2011 04:19:56 +0530 Received: from localhost.localdomain (dbdp20.itg.ti.com [172.24.170.38]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id pAIMnaCk017687 for ; Sat, 19 Nov 2011 04:19:55 +0530 (IST) From: Tom Rini To: Date: Fri, 18 Nov 2011 15:48:07 -0700 Message-ID: <1321656491-19874-11-git-send-email-trini@ti.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1321656491-19874-1-git-send-email-trini@ti.com> References: <1321656491-19874-1-git-send-email-trini@ti.com> MIME-Version: 1.0 Subject: [U-Boot] [PATCH v4 10/14] OMAP3 SPL: Add identify_nand_chip function X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de A number of boards are populated with a PoP chip for both DDR and NAND memory. Other boards may simply use this as an easy way to identify board revs. So we provide a function that can be called early to reset the NAND chip and return the result of NAND_CMD_READID. All of this code is put into spl_id_nand.c and controlled via CONFIG_SPL_OMAP3_ID_NAND. Signed-off-by: Tom Rini --- arch/arm/cpu/armv7/omap3/Makefile | 3 + arch/arm/cpu/armv7/omap3/spl_id_nand.c | 87 +++++++++++++++++++++++++++ arch/arm/include/asm/arch-omap3/sys_proto.h | 1 + 3 files changed, 91 insertions(+), 0 deletions(-) create mode 100644 arch/arm/cpu/armv7/omap3/spl_id_nand.c diff --git a/arch/arm/cpu/armv7/omap3/Makefile b/arch/arm/cpu/armv7/omap3/Makefile index 8e85891..4b38e45 100644 --- a/arch/arm/cpu/armv7/omap3/Makefile +++ b/arch/arm/cpu/armv7/omap3/Makefile @@ -31,6 +31,9 @@ COBJS += board.o COBJS += clock.o COBJS += mem.o COBJS += sys_info.o +ifdef CONFIG_SPL_BUILD +COBJS-$(CONFIG_SPL_OMAP3_ID_NAND) += spl_id_nand.o +endif COBJS-$(CONFIG_EMIF4) += emif4.o COBJS-$(CONFIG_SDRC) += sdrc.o diff --git a/arch/arm/cpu/armv7/omap3/spl_id_nand.c b/arch/arm/cpu/armv7/omap3/spl_id_nand.c new file mode 100644 index 0000000..0871fc9 --- /dev/null +++ b/arch/arm/cpu/armv7/omap3/spl_id_nand.c @@ -0,0 +1,87 @@ +/* + * (C) Copyright 2011 + * Texas Instruments, + * + * Author : + * Tom Rini + * + * Initial Code from: + * Richard Woodruff + * Jian Zhang + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +static struct gpmc *gpmc_config = (struct gpmc *)GPMC_BASE; + +/* nand_command: Send a flash command to the flash chip */ +static void nand_command(u8 command) +{ + writeb(command, &gpmc_config->cs[0].nand_cmd); + + if (command == NAND_CMD_RESET) { + unsigned char ret_val; + writeb(NAND_CMD_STATUS, &gpmc_config->cs[0].nand_cmd); + do { + /* Wait until ready */ + ret_val = readl(&gpmc_config->cs[0].nand_dat); + } while ((ret_val & NAND_STATUS_READY) != NAND_STATUS_READY); + } +} + +/* + * Many boards will want to know the results of the NAND_CMD_READID command + * in order to decide what to do about DDR initialization. This function + * allows us to do that very early and to pass those results back to the + * board so it can make whatever decisions need to be made. + */ +void identify_nand_chip(int *mfr, int *id) +{ + /* Make sure that we have setup GPMC for NAND correctly. */ + writel(M_NAND_GPMC_CONFIG1, &gpmc_config->cs[0].config1); + writel(M_NAND_GPMC_CONFIG2, &gpmc_config->cs[0].config2); + writel(M_NAND_GPMC_CONFIG3, &gpmc_config->cs[0].config3); + writel(M_NAND_GPMC_CONFIG4, &gpmc_config->cs[0].config4); + writel(M_NAND_GPMC_CONFIG5, &gpmc_config->cs[0].config5); + writel(M_NAND_GPMC_CONFIG6, &gpmc_config->cs[0].config6); + + /* + * Enable the config. The CS size goes in bits 11:8. We set + * bit 6 to enable the CS and the base address goes into bits 5:0. + */ + writel((GPMC_SIZE_128M << 8) | (GPMC_CS_ENABLE << 6) | + ((NAND_BASE >> 24) & GPMC_BASEADDR_MASK), + &gpmc_config->cs[0].config7); + + sdelay(2000); + + /* Issue a RESET and then READID */ + nand_command(NAND_CMD_RESET); + nand_command(NAND_CMD_READID); + + /* Set the address to read to 0x0 */ + writeb(0x0, &gpmc_config->cs[0].nand_adr); + + /* Read off the manufacturer and device id. */ + *mfr = readb(&gpmc_config->cs[0].nand_dat); + *id = readb(&gpmc_config->cs[0].nand_dat); +} diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h index 80e167b..e5031d5 100644 --- a/arch/arm/include/asm/arch-omap3/sys_proto.h +++ b/arch/arm/include/asm/arch-omap3/sys_proto.h @@ -40,6 +40,7 @@ void sdrc_init(void); void do_sdrc_init(u32, u32); void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, u32 *mr); +void identify_nand_chip(int *mfr, int *id); void emif4_init(void); void gpmc_init(void); void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,