From patchwork Thu Nov 17 13:22:59 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benoit Canet X-Patchwork-Id: 126218 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id B4015B71F0 for ; Fri, 18 Nov 2011 00:23:44 +1100 (EST) Received: from localhost ([::1]:60087 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RR1wE-0006ho-8y for incoming@patchwork.ozlabs.org; Thu, 17 Nov 2011 08:23:34 -0500 Received: from eggs.gnu.org ([140.186.70.92]:58478) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RR1vu-00066Y-QN for qemu-devel@nongnu.org; Thu, 17 Nov 2011 08:23:20 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RR1vo-00061n-Vp for qemu-devel@nongnu.org; Thu, 17 Nov 2011 08:23:14 -0500 Received: from mail-wy0-f173.google.com ([74.125.82.173]:35854) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RR1vo-00061W-O6 for qemu-devel@nongnu.org; Thu, 17 Nov 2011 08:23:08 -0500 Received: by mail-wy0-f173.google.com with SMTP id 34so2173730wyg.4 for ; Thu, 17 Nov 2011 05:23:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=Xs9U7k3xbEsvLnm2sp9wt+sMQR7waxV5LrSKhgBnr0Q=; b=f2i8uwbnUc6f2as1J60WSV9DDrCdl2J7ZkPd1oX3F7EBpKYWdt4I+toaTmzglpWRPG cv94Agf1aLKs7RYjjALz6jB2sBCCnyJZmII9i23k3ILkBB8hJoD0PO4rxvggk5OYxI50 xz3NZQbLjZugOX122A1AD5G4ce69Aj9P/MdVs= Received: by 10.180.95.132 with SMTP id dk4mr41997793wib.30.1321536188386; Thu, 17 Nov 2011 05:23:08 -0800 (PST) Received: from Laure.box.in.chocolate-blue.net ([109.190.18.76]) by mx.google.com with ESMTPS id i8sm18349631wie.11.2011.11.17.05.23.07 (version=SSLv3 cipher=OTHER); Thu, 17 Nov 2011 05:23:07 -0800 (PST) From: =?UTF-8?q?Beno=C3=AEt=20Canet?= To: qemu-devel@nongnu.org Date: Thu, 17 Nov 2011 14:22:59 +0100 Message-Id: <1321536182-10150-3-git-send-email-benoit.canet@gmail.com> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1321536182-10150-1-git-send-email-benoit.canet@gmail.com> References: <1321536182-10150-1-git-send-email-benoit.canet@gmail.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 74.125.82.173 Cc: =?UTF-8?q?Beno=C3=AEt=20Canet?= , avi@redhat.com Subject: [Qemu-devel] [[PATCH V2] 2/5] sh7750: convert cache and tlb to memory API X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Benoit Canet --- hw/sh7750.c | 43 ++++++++++++++++++++++--------------------- 1 files changed, 22 insertions(+), 21 deletions(-) diff --git a/hw/sh7750.c b/hw/sh7750.c index 3bf568d..6ad76df 100644 --- a/hw/sh7750.c +++ b/hw/sh7750.c @@ -42,6 +42,7 @@ typedef struct SH7750State { MemoryRegion iomem_ff8; MemoryRegion iomem_1fc; MemoryRegion iomem_ffc; + MemoryRegion mmct_iomem; /* CPU */ CPUSH4State *cpu; /* Peripheral frequency in Hz */ @@ -623,18 +624,23 @@ static struct intc_group groups_irl[] = { #define MM_UTLB_DATA (7) #define MM_REGION_TYPE(addr) ((addr & MM_REGION_MASK) >> 24) -static uint32_t invalid_read(void *opaque, target_phys_addr_t addr) +static uint64_t invalid_read(void *opaque, target_phys_addr_t addr) { abort(); return 0; } -static uint32_t sh7750_mmct_readl(void *opaque, target_phys_addr_t addr) +static uint64_t sh7750_mmct_read(void *opaque, target_phys_addr_t addr, + unsigned size) { SH7750State *s = opaque; uint32_t ret = 0; + if (size != 4) { + return invalid_read(opaque, addr); + } + switch (MM_REGION_TYPE(addr)) { case MM_ICACHE_ADDR: case MM_ICACHE_DATA: @@ -664,16 +670,20 @@ static uint32_t sh7750_mmct_readl(void *opaque, target_phys_addr_t addr) } static void invalid_write(void *opaque, target_phys_addr_t addr, - uint32_t mem_value) + uint64_t mem_value) { abort(); } -static void sh7750_mmct_writel(void *opaque, target_phys_addr_t addr, - uint32_t mem_value) +static void sh7750_mmct_write(void *opaque, target_phys_addr_t addr, + uint64_t mem_value, unsigned size) { SH7750State *s = opaque; + if (size != 4) { + invalid_write(opaque, addr, mem_value); + } + switch (MM_REGION_TYPE(addr)) { case MM_ICACHE_ADDR: case MM_ICACHE_DATA: @@ -702,22 +712,15 @@ static void sh7750_mmct_writel(void *opaque, target_phys_addr_t addr, } } -static CPUReadMemoryFunc * const sh7750_mmct_read[] = { - invalid_read, - invalid_read, - sh7750_mmct_readl -}; - -static CPUWriteMemoryFunc * const sh7750_mmct_write[] = { - invalid_write, - invalid_write, - sh7750_mmct_writel +static const struct MemoryRegionOps sh7750_mmct_ops = { + .read = sh7750_mmct_read, + .write = sh7750_mmct_write, + .endianness = DEVICE_NATIVE_ENDIAN, }; SH7750State *sh7750_init(CPUSH4State * cpu, MemoryRegion *sysmem) { SH7750State *s; - int sh7750_mm_cache_and_tlb; /* memory mapped cache and tlb */ s = g_malloc0(sizeof(SH7750State)); s->cpu = cpu; @@ -749,11 +752,9 @@ SH7750State *sh7750_init(CPUSH4State * cpu, MemoryRegion *sysmem) &s->iomem, 0x1fc00000, 0x1000); memory_region_add_subregion(sysmem, 0xffc00000, &s->iomem_ffc); - sh7750_mm_cache_and_tlb = cpu_register_io_memory(sh7750_mmct_read, - sh7750_mmct_write, s, - DEVICE_NATIVE_ENDIAN); - cpu_register_physical_memory(0xf0000000, 0x08000000, - sh7750_mm_cache_and_tlb); + memory_region_init_io(&s->mmct_iomem, &sh7750_mmct_ops, s, + "cache-and-tlb", 0x08000000); + memory_region_add_subregion(sysmem, 0xf0000000, &s->mmct_iomem); sh_intc_init(&s->intc, NR_SOURCES, _INTC_ARRAY(mask_registers),