| Message ID | 1585105663-199127-1-git-send-email-chenxiang66@hisilicon.com |
|---|---|
| State | Superseded |
| Delegated to: | Ambarus Tudor |
| Headers | show |
| Series | mtd: spi-nor: Enable locking for n25q128a11 | expand |
Ping... 在 2020/3/25 11:07, chenxiang 写道: > From: Xiang Chen <chenxiang66@hisilicon.com> > > As 4bit block protection pathset for some micron models are merged, > n25q128a11 also uses 4 bit Block Protection scheme, so enable locking > for it. Tested it on n25q128a11, the locking functions work well. > > Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com> > --- > drivers/mtd/spi-nor/micron-st.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c > index 6c034b9..02c0b53 100644 > --- a/drivers/mtd/spi-nor/micron-st.c > +++ b/drivers/mtd/spi-nor/micron-st.c > @@ -29,7 +29,9 @@ static const struct flash_info st_parts[] = { > { "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128, > SECT_4K | SPI_NOR_QUAD_READ) }, > { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, > - SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, > + SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | > + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | > + SPI_NOR_4BIT_BP | SPI_NOR_BP3_SR_BIT6) }, > { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, > SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, > { "mt25ql256a", INFO6(0x20ba19, 0x104400, 64 * 1024, 512,
Hi, chenxiang On Tue, 2020-04-14 at 09:16 +0800, chenxiang (M) wrote: > Ping... > > 在 2020/3/25 11:07, chenxiang 写道: > > From: Xiang Chen <chenxiang66@hisilicon.com> > > > > As 4bit block protection pathset for some micron models are merged, you mean patchset? > > n25q128a11 also uses 4 bit Block Protection scheme, so enable > > locking > > for it. Tested it on n25q128a11, the locking functions work well. > > > > Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com> > > --- > > drivers/mtd/spi-nor/micron-st.c | 4 +++- > > 1 file changed, 3 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi- > > nor/micron-st.c > > index 6c034b9..02c0b53 100644 > > --- a/drivers/mtd/spi-nor/micron-st.c > > +++ b/drivers/mtd/spi-nor/micron-st.c > > @@ -29,7 +29,9 @@ static const struct flash_info st_parts[] = { > > { "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128, > > SECT_4K | SPI_NOR_QUAD_READ) }, > > { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, > > - SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, > > + SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | > > + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | > > + SPI_NOR_4BIT_BP | SPI_NOR_BP3_SR_BIT6) }, > > { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, > > SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, > > { "mt25ql256a", INFO6(0x20ba19, 0x104400, 64 * 1024, 512, I've checked the flags according to it's datasheet. It seems good. You can add my review tag after update the typo. Reviewed-by: Jungseung Lee <js07.lee@samsung.com> Thanks, > >
Hi Jungseung, 在 2020/4/16 18:43, Jungseung Lee 写道: > Hi, chenxiang > > On Tue, 2020-04-14 at 09:16 +0800, chenxiang (M) wrote: >> Ping... >> >> 在 2020/3/25 11:07, chenxiang 写道: >>> From: Xiang Chen <chenxiang66@hisilicon.com> >>> >>> As 4bit block protection pathset for some micron models are merged, > you mean patchset? Right, i will fix it on next version. > >>> n25q128a11 also uses 4 bit Block Protection scheme, so enable >>> locking >>> for it. Tested it on n25q128a11, the locking functions work well. >>> >>> Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com> >>> --- >>> drivers/mtd/spi-nor/micron-st.c | 4 +++- >>> 1 file changed, 3 insertions(+), 1 deletion(-) >>> >>> diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi- >>> nor/micron-st.c >>> index 6c034b9..02c0b53 100644 >>> --- a/drivers/mtd/spi-nor/micron-st.c >>> +++ b/drivers/mtd/spi-nor/micron-st.c >>> @@ -29,7 +29,9 @@ static const struct flash_info st_parts[] = { >>> { "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128, >>> SECT_4K | SPI_NOR_QUAD_READ) }, >>> { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, >>> - SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, >>> + SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | >>> + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | >>> + SPI_NOR_4BIT_BP | SPI_NOR_BP3_SR_BIT6) }, >>> { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, >>> SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, >>> { "mt25ql256a", INFO6(0x20ba19, 0x104400, 64 * 1024, 512, > I've checked the flags according to it's datasheet. It seems good. > You can add my review tag after update the typo. > > Reviewed-by: Jungseung Lee <js07.lee@samsung.com> > > Thanks, Ok, thanks. >> > > . >
diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c index 6c034b9..02c0b53 100644 --- a/drivers/mtd/spi-nor/micron-st.c +++ b/drivers/mtd/spi-nor/micron-st.c @@ -29,7 +29,9 @@ static const struct flash_info st_parts[] = { { "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) }, { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, - SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, + SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | + SPI_NOR_4BIT_BP | SPI_NOR_BP3_SR_BIT6) }, { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, { "mt25ql256a", INFO6(0x20ba19, 0x104400, 64 * 1024, 512,