| Message ID | 20200323092430.1466234-6-tudor.ambarus@microchip.com |
|---|---|
| State | Superseded |
| Delegated to: | Ambarus Tudor |
| Headers | show |
| Series | None | expand |
Hi, On Mon, 2020-03-23 at 09:24 +0000, Tudor.Ambarus@microchip.com wrote: > From: Jungseung Lee <js07.lee@samsung.com> > > Currently, we are supporting block protection only for flash chips > with > 3 block protection bits (BP0-2) in the SR register. > > Enable block protection support for flashes with 4 block protection > bits > (BP0-3). > > Add a flash_info flag for flashes that describe 4 block protection > bits. > Add another flash_info flag for flashes in which BP3 bit is not > adjacent > to the BP0-2 bits. > > Signed-off-by: Jungseung Lee <js07.lee@samsung.com> > Reviewed-by: Michael Walle <michael@walle.cc> > Tested-by: Michael Walle <michael@walle.cc> > [ta: > - introduce spi_nor_get_sr_bp_mask(), spi_nor_get_sr_tb_mask() > - drop Micron n25q512ax3 / BP0-3) boilerplate description > - be explicit in spi_nor_get_locked_range_sr aboyt SR_BP3 as Michael > suggested, > - amend commit description] > Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> > --- > drivers/mtd/spi-nor/core.c | 66 +++++++++++++++++++++++++++------ > ---- > drivers/mtd/spi-nor/core.h | 10 ++++++ > include/linux/mtd/spi-nor.h | 2 ++ > 3 files changed, 60 insertions(+), 18 deletions(-) > > diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c > index c0d186f417d8..b70c0b2e0958 100644 > --- a/drivers/mtd/spi-nor/core.c > +++ b/drivers/mtd/spi-nor/core.c > @@ -1514,13 +1514,34 @@ static int spi_nor_erase(struct mtd_info > *mtd, struct erase_info *instr) > return ret; > } > > +static u8 spi_nor_get_sr_bp_mask(struct spi_nor *nor) > +{ > + u8 mask = SR_BP2 | SR_BP1 | SR_BP0; > + > + if (nor->flags & SNOR_F_HAS_SR_BP3_BIT6) > + return mask | SR_BP3_BIT6; > + > + if (nor->flags & SNOR_F_HAS_4BIT_BP) > + return mask | SR_BP3; > + > + return mask; > +} > + > +static u8 spi_nor_get_sr_tb_mask(struct spi_nor *nor) > +{ > + if (nor->flags & SNOR_F_HAS_SR_TB_BIT6) > + return SR_TB_BIT6; > + else > + return SR_TB_BIT5; > +} > + > static u64 spi_nor_get_min_prot_length_sr(struct spi_nor *nor) > { > unsigned int bp_slots, bp_slots_needed; > - u8 mask = SR_BP2 | SR_BP1 | SR_BP0; > + u8 mask = spi_nor_get_sr_bp_mask(nor); > > /* Reserved one for "protect none" and one for "protect all". > */ > - bp_slots = (mask >> SR_BP_SHIFT) + 1 - 2; > + bp_slots = (1 << hweight8(mask)) - 2; > bp_slots_needed = ilog2(nor->info->n_sectors); > > if (bp_slots_needed > bp_slots) > @@ -1535,12 +1556,14 @@ static void > spi_nor_get_locked_range_sr(struct spi_nor *nor, u8 sr, loff_t *ofs, > { > struct mtd_info *mtd = &nor->mtd; > u64 min_prot_len; > - u8 mask = SR_BP2 | SR_BP1 | SR_BP0; > - u8 tb_mask = SR_TB_BIT5; > - u8 bp = (sr & mask) >> SR_BP_SHIFT; > + u8 mask = spi_nor_get_sr_bp_mask(nor); > + u8 tb_mask = spi_nor_get_sr_tb_mask(nor); > + u8 bp, val = sr & mask; > > - if (nor->flags & SNOR_F_HAS_SR_TB_BIT6) > - tb_mask = SR_TB_BIT6; > + if (nor->flags & SNOR_F_HAS_SR_BP3_BIT6 && val & SR_BP3_BIT6) > + val = (val & ~SR_BP3_BIT6) | SR_BP3; > + > + bp = val >> SR_BP_SHIFT; > > if (!bp) { > /* No protection */ > @@ -1598,7 +1621,8 @@ static int spi_nor_is_unlocked_sr(struct > spi_nor *nor, loff_t ofs, uint64_t len, > > /* > * Lock a region of the flash. Compatible with ST Micro and similar > flash. > - * Supports the block protection bits BP{0,1,2} in the status > register > + * Supports the block protection bits BP{0,1,2}/BP{0,1,2,3} in the > status > + * register > * (SR). Does not support these features found in newer SR > bitfields: > * - SEC: sector/block protect - only handle SEC=0 (block protect) > * - CMP: complement protect - only support CMP=0 (range is not > complemented) > @@ -1633,8 +1657,8 @@ static int spi_nor_sr_lock(struct spi_nor *nor, > loff_t ofs, uint64_t len) > struct mtd_info *mtd = &nor->mtd; > u64 min_prot_len; > int ret, status_old, status_new; > - u8 mask = SR_BP2 | SR_BP1 | SR_BP0; > - u8 tb_mask = SR_TB_BIT5; > + u8 mask = spi_nor_get_sr_bp_mask(nor); > + u8 tb_mask = spi_nor_get_sr_tb_mask(nor); > u8 pow, val; > loff_t lock_len; > bool can_be_top = true, can_be_bottom = nor->flags & > SNOR_F_HAS_SR_TB; > @@ -1671,9 +1695,6 @@ static int spi_nor_sr_lock(struct spi_nor *nor, > loff_t ofs, uint64_t len) > else > lock_len = ofs + len; > > - if (nor->flags & SNOR_F_HAS_SR_TB_BIT6) > - tb_mask = SR_TB_BIT6; > - > if (lock_len == mtd->size) { > val = mask; > } else { > @@ -1681,6 +1702,9 @@ static int spi_nor_sr_lock(struct spi_nor *nor, > loff_t ofs, uint64_t len) > pow = ilog2(lock_len) - ilog2(min_prot_len) + 1; > val = pow << SR_BP_SHIFT; > > + if (nor->flags & SNOR_F_HAS_SR_BP3_BIT6 && val & > SR_BP3) > + val = (val & ~SR_BP3) | SR_BP3_BIT6; > + > if (val & ~mask) > return -EINVAL; > > @@ -1718,8 +1742,8 @@ static int spi_nor_sr_unlock(struct spi_nor > *nor, loff_t ofs, uint64_t len) > struct mtd_info *mtd = &nor->mtd; > u64 min_prot_len; > int ret, status_old, status_new; > - u8 mask = SR_BP2 | SR_BP1 | SR_BP0; > - u8 tb_mask = SR_TB_BIT5; > + u8 mask = spi_nor_get_sr_bp_mask(nor); > + u8 tb_mask = spi_nor_get_sr_tb_mask(nor); > u8 pow, val; > loff_t lock_len; > bool can_be_top = true, can_be_bottom = nor->flags & > SNOR_F_HAS_SR_TB; > @@ -1756,9 +1780,6 @@ static int spi_nor_sr_unlock(struct spi_nor > *nor, loff_t ofs, uint64_t len) > else > lock_len = ofs; > > - if (nor->flags & SNOR_F_HAS_SR_TB_BIT6) > - tb_mask = SR_TB_BIT6; > - > if (lock_len == 0) { > val = 0; /* fully unlocked */ > } else { > @@ -1766,6 +1787,9 @@ static int spi_nor_sr_unlock(struct spi_nor > *nor, loff_t ofs, uint64_t len) > pow = ilog2(lock_len) - ilog2(min_prot_len) + 1; > val = pow << SR_BP_SHIFT; > > + if (nor->flags & SNOR_F_HAS_SR_BP3_BIT6 && val & > SR_BP3) > + val = (val & ~SR_BP3) | SR_BP3_BIT6; > + > /* Some power-of-two sizes are not supported */ > if (val & ~mask) > return -EINVAL; > @@ -3125,6 +3149,12 @@ int spi_nor_scan(struct spi_nor *nor, const > char *name, > if (info->flags & USE_CLSR) > nor->flags |= SNOR_F_USE_CLSR; > > + if (info->flags & SPI_NOR_4BIT_BP) { > + nor->flags |= SNOR_F_HAS_4BIT_BP; > + if (info->flags & SPI_NOR_BP3_SR_BIT6) > + nor->flags |= SNOR_F_HAS_SR_BP3_BIT6; > + } > + > if (info->flags & SPI_NOR_NO_ERASE) > mtd->flags |= MTD_NO_ERASE; > > diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h > index 3ce826b35ad1..6f2f6b27173f 100644 > --- a/drivers/mtd/spi-nor/core.h > +++ b/drivers/mtd/spi-nor/core.h > @@ -24,6 +24,8 @@ enum spi_nor_option_flags { > SNOR_F_HAS_16BIT_SR = BIT(9), > SNOR_F_NO_READ_CR = BIT(10), > SNOR_F_HAS_SR_TB_BIT6 = BIT(11), > + SNOR_F_HAS_4BIT_BP = BIT(12), > + SNOR_F_HAS_SR_BP3_BIT6 = BIT(13), > }; > > struct spi_nor_read_command { > @@ -301,6 +303,14 @@ struct flash_info { > * status register. Must be > used with > * SPI_NOR_HAS_TB. > */ > +#define SPI_NOR_4BIT_BP BIT(17) /* > + * Flash SR has 4 bit fields > (BP0-3) > + * for block protection. > + */ > +#define SPI_NOR_BP3_SR_BIT6 BIT(18) /* > + * BP3 is bit 6 of status > register. > + * Must be used with > SPI_NOR_4BIT_BP. > + */ > > /* Part specific fixup hooks. */ > const struct spi_nor_fixups *fixups; > diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi- > nor.h > index e656858b50a5..1e2af0ec1f03 100644 > --- a/include/linux/mtd/spi-nor.h > +++ b/include/linux/mtd/spi-nor.h > @@ -111,7 +111,9 @@ > #define SR_BP0 BIT(2) /* Block protect 0 */ > #define SR_BP1 BIT(3) /* Block protect 1 */ > #define SR_BP2 BIT(4) /* Block protect 2 */ > +#define SR_BP3 BIT(5) /* Block protect 3 */ > #define SR_TB_BIT5 BIT(5) /* Top/Bottom protect */ > +#define SR_BP3_BIT6 BIT(6) /* Block protect 3 */ > #define SR_TB_BIT6 BIT(6) /* Top/Bottom protect */ > #define SR_SRWD BIT(7) /* SR write protect > */ > /* Spansion/Cypress specific status bits */ Tested with a n25q512ax3 (bp0-3) and w25q128 (bp0-2). It passed all of my test cases. Tested-by: Jungseung Lee <js07.lee@samsung.com>
On Monday, March 23, 2020 2:43:09 PM EET Jungseung Lee wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the > content is safe > > Hi, Hi, Jungseung, > > On Mon, 2020-03-23 at 09:24 +0000, Tudor.Ambarus@microchip.com wrote: > > From: Jungseung Lee <js07.lee@samsung.com> > > > > Currently, we are supporting block protection only for flash chips > > with > > 3 block protection bits (BP0-2) in the SR register. > > > > Enable block protection support for flashes with 4 block protection > > bits > > (BP0-3). > > > > Add a flash_info flag for flashes that describe 4 block protection > > bits. > > Add another flash_info flag for flashes in which BP3 bit is not > > adjacent > > to the BP0-2 bits. > > > > Signed-off-by: Jungseung Lee <js07.lee@samsung.com> > > Reviewed-by: Michael Walle <michael@walle.cc> > > Tested-by: Michael Walle <michael@walle.cc> > > [ta: > > - introduce spi_nor_get_sr_bp_mask(), spi_nor_get_sr_tb_mask() from the previous patch set > > - drop Micron n25q512ax3 / BP0-3) boilerplate description > > - be explicit in spi_nor_get_locked_range_sr aboyt SR_BP3 as Michael > > suggested, > > - amend commit description] I'll drop these comments when/if applying. Let me know if you're ok with the changes that I did. Please do the same for patches 3/5 and 5/5. > > Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> > > --- > > > > drivers/mtd/spi-nor/core.c | 66 +++++++++++++++++++++++++++------ > > > > ---- > > > > drivers/mtd/spi-nor/core.h | 10 ++++++ > > include/linux/mtd/spi-nor.h | 2 ++ > > 3 files changed, 60 insertions(+), 18 deletions(-) cut > Tested with a n25q512ax3 (bp0-3) and w25q128 (bp0-2). > It passed all of my test cases. > > Tested-by: Jungseung Lee <js07.lee@samsung.com> Great! Since you are the author of the patch, it's not necessary to add your T-b tag, but I'll amend the commit description to say that it was tested on n25q512ax3 (bp0-3) and w25q128 (bp0-2). Also, would you please review patches 1 and 2 from the series? Cheers, ta
Hi, On Mon, 2020-03-23 at 12:55 +0000, Tudor.Ambarus@microchip.com wrote: > On Monday, March 23, 2020 2:43:09 PM EET Jungseung Lee wrote: > > EXTERNAL EMAIL: Do not click links or open attachments unless you > > know the > > content is safe > > > > Hi, > > Hi, Jungseung, > > > > On Mon, 2020-03-23 at 09:24 +0000, Tudor.Ambarus@microchip.com > > wrote: > > > From: Jungseung Lee <js07.lee@samsung.com> > > > > > > Currently, we are supporting block protection only for flash > > > chips > > > with > > > 3 block protection bits (BP0-2) in the SR register. > > > > > > Enable block protection support for flashes with 4 block > > > protection > > > bits > > > (BP0-3). > > > > > > Add a flash_info flag for flashes that describe 4 block > > > protection > > > bits. > > > Add another flash_info flag for flashes in which BP3 bit is not > > > adjacent > > > to the BP0-2 bits. > > > > > > Signed-off-by: Jungseung Lee <js07.lee@samsung.com> > > > Reviewed-by: Michael Walle <michael@walle.cc> > > > Tested-by: Michael Walle <michael@walle.cc> > > > [ta: > > > - introduce spi_nor_get_sr_bp_mask(), spi_nor_get_sr_tb_mask() > > from the previous patch set > > > - drop Micron n25q512ax3 / BP0-3) boilerplate description > > > - be explicit in spi_nor_get_locked_range_sr aboyt SR_BP3 as > > > Michael > > > suggested, > > > - amend commit description] > > I'll drop these comments when/if applying. Let me know if you're ok > with the > changes that I did. Please do the same for patches 3/5 and 5/5. > It looks much better. All the parts you modified are those that I thought were ambiguous. now it's ok. Thanks, > > > Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> > > > --- > > > > > > drivers/mtd/spi-nor/core.c | 66 +++++++++++++++++++++++++++-- > > > ---- > > > > > > ---- > > > > > > drivers/mtd/spi-nor/core.h | 10 ++++++ > > > include/linux/mtd/spi-nor.h | 2 ++ > > > 3 files changed, 60 insertions(+), 18 deletions(-) > > cut > > > Tested with a n25q512ax3 (bp0-3) and w25q128 (bp0-2). > > It passed all of my test cases. > > > > Tested-by: Jungseung Lee <js07.lee@samsung.com> > > Great! Since you are the author of the patch, it's not necessary to > add your > T-b tag, but I'll amend the commit description to say that it was > tested on > n25q512ax3 (bp0-3) and w25q128 (bp0-2). > > Also, would you please review patches 1 and 2 from the series? > > Cheers, > ta > >
Am 2020-03-23 10:24, schrieb Tudor.Ambarus@microchip.com: > From: Jungseung Lee <js07.lee@samsung.com> > > Currently, we are supporting block protection only for flash chips with > 3 block protection bits (BP0-2) in the SR register. > > Enable block protection support for flashes with 4 block protection > bits > (BP0-3). > > Add a flash_info flag for flashes that describe 4 block protection > bits. > Add another flash_info flag for flashes in which BP3 bit is not > adjacent > to the BP0-2 bits. > > Signed-off-by: Jungseung Lee <js07.lee@samsung.com> > Reviewed-by: Michael Walle <michael@walle.cc> > Tested-by: Michael Walle <michael@walle.cc> > [ta: > - introduce spi_nor_get_sr_bp_mask(), spi_nor_get_sr_tb_mask() > - drop Micron n25q512ax3 / BP0-3) boilerplate description that was actually a comment on my side some time ago. Because the current example isn't really good and lacks the second case (which is added by this patch). -michael > - be explicit in spi_nor_get_locked_range_sr aboyt SR_BP3 as Michael > suggested, > - amend commit description] > Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> > --- > drivers/mtd/spi-nor/core.c | 66 +++++++++++++++++++++++++++---------- > drivers/mtd/spi-nor/core.h | 10 ++++++ > include/linux/mtd/spi-nor.h | 2 ++ > 3 files changed, 60 insertions(+), 18 deletions(-) > > diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c > index c0d186f417d8..b70c0b2e0958 100644 > --- a/drivers/mtd/spi-nor/core.c > +++ b/drivers/mtd/spi-nor/core.c > @@ -1514,13 +1514,34 @@ static int spi_nor_erase(struct mtd_info *mtd, > struct erase_info *instr) > return ret; > } > > +static u8 spi_nor_get_sr_bp_mask(struct spi_nor *nor) > +{ > + u8 mask = SR_BP2 | SR_BP1 | SR_BP0; > + > + if (nor->flags & SNOR_F_HAS_SR_BP3_BIT6) > + return mask | SR_BP3_BIT6; > + > + if (nor->flags & SNOR_F_HAS_4BIT_BP) > + return mask | SR_BP3; > + > + return mask; > +} > + > +static u8 spi_nor_get_sr_tb_mask(struct spi_nor *nor) > +{ > + if (nor->flags & SNOR_F_HAS_SR_TB_BIT6) > + return SR_TB_BIT6; > + else > + return SR_TB_BIT5; > +} > + > static u64 spi_nor_get_min_prot_length_sr(struct spi_nor *nor) > { > unsigned int bp_slots, bp_slots_needed; > - u8 mask = SR_BP2 | SR_BP1 | SR_BP0; > + u8 mask = spi_nor_get_sr_bp_mask(nor); > > /* Reserved one for "protect none" and one for "protect all". */ > - bp_slots = (mask >> SR_BP_SHIFT) + 1 - 2; > + bp_slots = (1 << hweight8(mask)) - 2; > bp_slots_needed = ilog2(nor->info->n_sectors); > > if (bp_slots_needed > bp_slots) > @@ -1535,12 +1556,14 @@ static void spi_nor_get_locked_range_sr(struct > spi_nor *nor, u8 sr, loff_t *ofs, > { > struct mtd_info *mtd = &nor->mtd; > u64 min_prot_len; > - u8 mask = SR_BP2 | SR_BP1 | SR_BP0; > - u8 tb_mask = SR_TB_BIT5; > - u8 bp = (sr & mask) >> SR_BP_SHIFT; > + u8 mask = spi_nor_get_sr_bp_mask(nor); > + u8 tb_mask = spi_nor_get_sr_tb_mask(nor); > + u8 bp, val = sr & mask; > > - if (nor->flags & SNOR_F_HAS_SR_TB_BIT6) > - tb_mask = SR_TB_BIT6; > + if (nor->flags & SNOR_F_HAS_SR_BP3_BIT6 && val & SR_BP3_BIT6) > + val = (val & ~SR_BP3_BIT6) | SR_BP3; > + > + bp = val >> SR_BP_SHIFT; > > if (!bp) { > /* No protection */ > @@ -1598,7 +1621,8 @@ static int spi_nor_is_unlocked_sr(struct spi_nor > *nor, loff_t ofs, uint64_t len, > > /* > * Lock a region of the flash. Compatible with ST Micro and similar > flash. > - * Supports the block protection bits BP{0,1,2} in the status register > + * Supports the block protection bits BP{0,1,2}/BP{0,1,2,3} in the > status > + * register > * (SR). Does not support these features found in newer SR bitfields: > * - SEC: sector/block protect - only handle SEC=0 (block protect) > * - CMP: complement protect - only support CMP=0 (range is not > complemented) > @@ -1633,8 +1657,8 @@ static int spi_nor_sr_lock(struct spi_nor *nor, > loff_t ofs, uint64_t len) > struct mtd_info *mtd = &nor->mtd; > u64 min_prot_len; > int ret, status_old, status_new; > - u8 mask = SR_BP2 | SR_BP1 | SR_BP0; > - u8 tb_mask = SR_TB_BIT5; > + u8 mask = spi_nor_get_sr_bp_mask(nor); > + u8 tb_mask = spi_nor_get_sr_tb_mask(nor); > u8 pow, val; > loff_t lock_len; > bool can_be_top = true, can_be_bottom = nor->flags & > SNOR_F_HAS_SR_TB; > @@ -1671,9 +1695,6 @@ static int spi_nor_sr_lock(struct spi_nor *nor, > loff_t ofs, uint64_t len) > else > lock_len = ofs + len; > > - if (nor->flags & SNOR_F_HAS_SR_TB_BIT6) > - tb_mask = SR_TB_BIT6; > - > if (lock_len == mtd->size) { > val = mask; > } else { > @@ -1681,6 +1702,9 @@ static int spi_nor_sr_lock(struct spi_nor *nor, > loff_t ofs, uint64_t len) > pow = ilog2(lock_len) - ilog2(min_prot_len) + 1; > val = pow << SR_BP_SHIFT; > > + if (nor->flags & SNOR_F_HAS_SR_BP3_BIT6 && val & SR_BP3) > + val = (val & ~SR_BP3) | SR_BP3_BIT6; > + > if (val & ~mask) > return -EINVAL; > > @@ -1718,8 +1742,8 @@ static int spi_nor_sr_unlock(struct spi_nor > *nor, loff_t ofs, uint64_t len) > struct mtd_info *mtd = &nor->mtd; > u64 min_prot_len; > int ret, status_old, status_new; > - u8 mask = SR_BP2 | SR_BP1 | SR_BP0; > - u8 tb_mask = SR_TB_BIT5; > + u8 mask = spi_nor_get_sr_bp_mask(nor); > + u8 tb_mask = spi_nor_get_sr_tb_mask(nor); > u8 pow, val; > loff_t lock_len; > bool can_be_top = true, can_be_bottom = nor->flags & > SNOR_F_HAS_SR_TB; > @@ -1756,9 +1780,6 @@ static int spi_nor_sr_unlock(struct spi_nor > *nor, loff_t ofs, uint64_t len) > else > lock_len = ofs; > > - if (nor->flags & SNOR_F_HAS_SR_TB_BIT6) > - tb_mask = SR_TB_BIT6; > - > if (lock_len == 0) { > val = 0; /* fully unlocked */ > } else { > @@ -1766,6 +1787,9 @@ static int spi_nor_sr_unlock(struct spi_nor > *nor, loff_t ofs, uint64_t len) > pow = ilog2(lock_len) - ilog2(min_prot_len) + 1; > val = pow << SR_BP_SHIFT; > > + if (nor->flags & SNOR_F_HAS_SR_BP3_BIT6 && val & SR_BP3) > + val = (val & ~SR_BP3) | SR_BP3_BIT6; > + > /* Some power-of-two sizes are not supported */ > if (val & ~mask) > return -EINVAL; > @@ -3125,6 +3149,12 @@ int spi_nor_scan(struct spi_nor *nor, const char > *name, > if (info->flags & USE_CLSR) > nor->flags |= SNOR_F_USE_CLSR; > > + if (info->flags & SPI_NOR_4BIT_BP) { > + nor->flags |= SNOR_F_HAS_4BIT_BP; > + if (info->flags & SPI_NOR_BP3_SR_BIT6) > + nor->flags |= SNOR_F_HAS_SR_BP3_BIT6; > + } > + > if (info->flags & SPI_NOR_NO_ERASE) > mtd->flags |= MTD_NO_ERASE; > > diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h > index 3ce826b35ad1..6f2f6b27173f 100644 > --- a/drivers/mtd/spi-nor/core.h > +++ b/drivers/mtd/spi-nor/core.h > @@ -24,6 +24,8 @@ enum spi_nor_option_flags { > SNOR_F_HAS_16BIT_SR = BIT(9), > SNOR_F_NO_READ_CR = BIT(10), > SNOR_F_HAS_SR_TB_BIT6 = BIT(11), > + SNOR_F_HAS_4BIT_BP = BIT(12), > + SNOR_F_HAS_SR_BP3_BIT6 = BIT(13), > }; > > struct spi_nor_read_command { > @@ -301,6 +303,14 @@ struct flash_info { > * status register. Must be used with > * SPI_NOR_HAS_TB. > */ > +#define SPI_NOR_4BIT_BP BIT(17) /* > + * Flash SR has 4 bit fields (BP0-3) > + * for block protection. > + */ > +#define SPI_NOR_BP3_SR_BIT6 BIT(18) /* > + * BP3 is bit 6 of status register. > + * Must be used with SPI_NOR_4BIT_BP. > + */ > > /* Part specific fixup hooks. */ > const struct spi_nor_fixups *fixups; > diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h > index e656858b50a5..1e2af0ec1f03 100644 > --- a/include/linux/mtd/spi-nor.h > +++ b/include/linux/mtd/spi-nor.h > @@ -111,7 +111,9 @@ > #define SR_BP0 BIT(2) /* Block protect 0 */ > #define SR_BP1 BIT(3) /* Block protect 1 */ > #define SR_BP2 BIT(4) /* Block protect 2 */ > +#define SR_BP3 BIT(5) /* Block protect 3 */ > #define SR_TB_BIT5 BIT(5) /* Top/Bottom protect */ > +#define SR_BP3_BIT6 BIT(6) /* Block protect 3 */ > #define SR_TB_BIT6 BIT(6) /* Top/Bottom protect */ > #define SR_SRWD BIT(7) /* SR write protect */ > /* Spansion/Cypress specific status bits */
On Monday, March 23, 2020 8:33:19 PM EET Michael Walle wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the > content is safe > Am 2020-03-23 10:24, schrieb Tudor.Ambarus@microchip.com: > > From: Jungseung Lee <js07.lee@samsung.com> > > > > Currently, we are supporting block protection only for flash chips with > > 3 block protection bits (BP0-2) in the SR register. > > > > Enable block protection support for flashes with 4 block protection > > bits > > (BP0-3). > > > > Add a flash_info flag for flashes that describe 4 block protection > > bits. > > Add another flash_info flag for flashes in which BP3 bit is not > > adjacent > > to the BP0-2 bits. > > > > Signed-off-by: Jungseung Lee <js07.lee@samsung.com> > > Reviewed-by: Michael Walle <michael@walle.cc> > > Tested-by: Michael Walle <michael@walle.cc> > > [ta: > > - introduce spi_nor_get_sr_bp_mask(), spi_nor_get_sr_tb_mask() > > - drop Micron n25q512ax3 / BP0-3) boilerplate description > > that was actually a comment on my side some time ago. Because the > current > example isn't really good and lacks the second case (which is added by > this patch). > I didn't like the example that was introduced by Jungseung because of the last column, the "Protected Portion" -> it focuses on Upper/Lower 1/pow(2, n). I think it is better to replace the "Protected Portion" column with a "Protected Block(s)" column (see a winbond datasheet), in order to be in sync with how the code looks now. It's true that the current example has the same problem. Would you care to send a patch to replace the current example? (keeping two examples would be too much). Or maybe remove the example entirely? Also, would you please review 1/5 as well? I need an agreement on that before applying the series. Cheers, ta
diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index c0d186f417d8..b70c0b2e0958 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -1514,13 +1514,34 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr) return ret; } +static u8 spi_nor_get_sr_bp_mask(struct spi_nor *nor) +{ + u8 mask = SR_BP2 | SR_BP1 | SR_BP0; + + if (nor->flags & SNOR_F_HAS_SR_BP3_BIT6) + return mask | SR_BP3_BIT6; + + if (nor->flags & SNOR_F_HAS_4BIT_BP) + return mask | SR_BP3; + + return mask; +} + +static u8 spi_nor_get_sr_tb_mask(struct spi_nor *nor) +{ + if (nor->flags & SNOR_F_HAS_SR_TB_BIT6) + return SR_TB_BIT6; + else + return SR_TB_BIT5; +} + static u64 spi_nor_get_min_prot_length_sr(struct spi_nor *nor) { unsigned int bp_slots, bp_slots_needed; - u8 mask = SR_BP2 | SR_BP1 | SR_BP0; + u8 mask = spi_nor_get_sr_bp_mask(nor); /* Reserved one for "protect none" and one for "protect all". */ - bp_slots = (mask >> SR_BP_SHIFT) + 1 - 2; + bp_slots = (1 << hweight8(mask)) - 2; bp_slots_needed = ilog2(nor->info->n_sectors); if (bp_slots_needed > bp_slots) @@ -1535,12 +1556,14 @@ static void spi_nor_get_locked_range_sr(struct spi_nor *nor, u8 sr, loff_t *ofs, { struct mtd_info *mtd = &nor->mtd; u64 min_prot_len; - u8 mask = SR_BP2 | SR_BP1 | SR_BP0; - u8 tb_mask = SR_TB_BIT5; - u8 bp = (sr & mask) >> SR_BP_SHIFT; + u8 mask = spi_nor_get_sr_bp_mask(nor); + u8 tb_mask = spi_nor_get_sr_tb_mask(nor); + u8 bp, val = sr & mask; - if (nor->flags & SNOR_F_HAS_SR_TB_BIT6) - tb_mask = SR_TB_BIT6; + if (nor->flags & SNOR_F_HAS_SR_BP3_BIT6 && val & SR_BP3_BIT6) + val = (val & ~SR_BP3_BIT6) | SR_BP3; + + bp = val >> SR_BP_SHIFT; if (!bp) { /* No protection */ @@ -1598,7 +1621,8 @@ static int spi_nor_is_unlocked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len, /* * Lock a region of the flash. Compatible with ST Micro and similar flash. - * Supports the block protection bits BP{0,1,2} in the status register + * Supports the block protection bits BP{0,1,2}/BP{0,1,2,3} in the status + * register * (SR). Does not support these features found in newer SR bitfields: * - SEC: sector/block protect - only handle SEC=0 (block protect) * - CMP: complement protect - only support CMP=0 (range is not complemented) @@ -1633,8 +1657,8 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_t ofs, uint64_t len) struct mtd_info *mtd = &nor->mtd; u64 min_prot_len; int ret, status_old, status_new; - u8 mask = SR_BP2 | SR_BP1 | SR_BP0; - u8 tb_mask = SR_TB_BIT5; + u8 mask = spi_nor_get_sr_bp_mask(nor); + u8 tb_mask = spi_nor_get_sr_tb_mask(nor); u8 pow, val; loff_t lock_len; bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB; @@ -1671,9 +1695,6 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_t ofs, uint64_t len) else lock_len = ofs + len; - if (nor->flags & SNOR_F_HAS_SR_TB_BIT6) - tb_mask = SR_TB_BIT6; - if (lock_len == mtd->size) { val = mask; } else { @@ -1681,6 +1702,9 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_t ofs, uint64_t len) pow = ilog2(lock_len) - ilog2(min_prot_len) + 1; val = pow << SR_BP_SHIFT; + if (nor->flags & SNOR_F_HAS_SR_BP3_BIT6 && val & SR_BP3) + val = (val & ~SR_BP3) | SR_BP3_BIT6; + if (val & ~mask) return -EINVAL; @@ -1718,8 +1742,8 @@ static int spi_nor_sr_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len) struct mtd_info *mtd = &nor->mtd; u64 min_prot_len; int ret, status_old, status_new; - u8 mask = SR_BP2 | SR_BP1 | SR_BP0; - u8 tb_mask = SR_TB_BIT5; + u8 mask = spi_nor_get_sr_bp_mask(nor); + u8 tb_mask = spi_nor_get_sr_tb_mask(nor); u8 pow, val; loff_t lock_len; bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB; @@ -1756,9 +1780,6 @@ static int spi_nor_sr_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len) else lock_len = ofs; - if (nor->flags & SNOR_F_HAS_SR_TB_BIT6) - tb_mask = SR_TB_BIT6; - if (lock_len == 0) { val = 0; /* fully unlocked */ } else { @@ -1766,6 +1787,9 @@ static int spi_nor_sr_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len) pow = ilog2(lock_len) - ilog2(min_prot_len) + 1; val = pow << SR_BP_SHIFT; + if (nor->flags & SNOR_F_HAS_SR_BP3_BIT6 && val & SR_BP3) + val = (val & ~SR_BP3) | SR_BP3_BIT6; + /* Some power-of-two sizes are not supported */ if (val & ~mask) return -EINVAL; @@ -3125,6 +3149,12 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, if (info->flags & USE_CLSR) nor->flags |= SNOR_F_USE_CLSR; + if (info->flags & SPI_NOR_4BIT_BP) { + nor->flags |= SNOR_F_HAS_4BIT_BP; + if (info->flags & SPI_NOR_BP3_SR_BIT6) + nor->flags |= SNOR_F_HAS_SR_BP3_BIT6; + } + if (info->flags & SPI_NOR_NO_ERASE) mtd->flags |= MTD_NO_ERASE; diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index 3ce826b35ad1..6f2f6b27173f 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -24,6 +24,8 @@ enum spi_nor_option_flags { SNOR_F_HAS_16BIT_SR = BIT(9), SNOR_F_NO_READ_CR = BIT(10), SNOR_F_HAS_SR_TB_BIT6 = BIT(11), + SNOR_F_HAS_4BIT_BP = BIT(12), + SNOR_F_HAS_SR_BP3_BIT6 = BIT(13), }; struct spi_nor_read_command { @@ -301,6 +303,14 @@ struct flash_info { * status register. Must be used with * SPI_NOR_HAS_TB. */ +#define SPI_NOR_4BIT_BP BIT(17) /* + * Flash SR has 4 bit fields (BP0-3) + * for block protection. + */ +#define SPI_NOR_BP3_SR_BIT6 BIT(18) /* + * BP3 is bit 6 of status register. + * Must be used with SPI_NOR_4BIT_BP. + */ /* Part specific fixup hooks. */ const struct spi_nor_fixups *fixups; diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index e656858b50a5..1e2af0ec1f03 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -111,7 +111,9 @@ #define SR_BP0 BIT(2) /* Block protect 0 */ #define SR_BP1 BIT(3) /* Block protect 1 */ #define SR_BP2 BIT(4) /* Block protect 2 */ +#define SR_BP3 BIT(5) /* Block protect 3 */ #define SR_TB_BIT5 BIT(5) /* Top/Bottom protect */ +#define SR_BP3_BIT6 BIT(6) /* Block protect 3 */ #define SR_TB_BIT6 BIT(6) /* Top/Bottom protect */ #define SR_SRWD BIT(7) /* SR write protect */ /* Spansion/Cypress specific status bits */