| Message ID | d3d40a1b-4bca-10b2-b253-46df6bc725bb@arm.com |
|---|---|
| State | New |
| Headers | show |
| Series | [Arm] : Revert changes to {get, set}_fpscr | expand |
Hi Andre, > -----Original Message----- > From: Andre Vieira (lists) <andre.simoesdiasvieira@arm.com> > Sent: 20 March 2020 08:53 > To: gcc-patches@gcc.gnu.org > Cc: Kyrylo Tkachov <Kyrylo.Tkachov@arm.com> > Subject: [PATCH][GCC][Arm]: Revert changes to {get, set}_fpscr > > Hi, > > MVE made changes to {get,set}_fpscr to enable the compiler to optimize > unneccesary gets and sets when using these for intrinsics that use and/or > write the carry bit. However, these actually get and set the full FPSCR register > and are used by fp env intrinsics to modify the fp context. So MVE should > not be using these. > > This fixes regressions for gcc.dg/atomic/c11-atomic-exec-5.c > > Bootstrapped and tested arm-linux-gnueabihf. > > Is this OK for trunk? Ok. Thanks, Kyrill > > gcc/ChangeLog: > 2020-03-20 Andre Vieira <andre.simoesdiasvieira@arm.com> > > * config/arm/unspecs.md (UNSPEC_GET_FPSCR): Rename this to ... > (VUNSPEC_GET_FPSCR): ... this, and move it to vunspec. > * config/arm/vfp.md: (get_fpscr, set_fpscr): Revert to old patterns.
diff --git a/gcc/config/arm/unspecs.md b/gcc/config/arm/unspecs.md index e76609f79418af38b70746336dd43592a1dc8713..f0b1f465de4b63d624510783576700519044717d 100644 --- a/gcc/config/arm/unspecs.md +++ b/gcc/config/arm/unspecs.md @@ -170,7 +170,6 @@ (define_c_enum "unspec" [ UNSPEC_TORC ; Used by the intrinsic form of the iWMMXt TORC instruction. UNSPEC_TORVSC ; Used by the intrinsic form of the iWMMXt TORVSC instruction. UNSPEC_TEXTRC ; Used by the intrinsic form of the iWMMXt TEXTRC instruction. - UNSPEC_GET_FPSCR ; Represent fetch of FPSCR content. ]) @@ -217,6 +216,7 @@ (define_c_enum "unspecv" [ VUNSPEC_SLX ; Represent a store-register-release-exclusive. VUNSPEC_LDA ; Represent a store-register-acquire. VUNSPEC_STL ; Represent a store-register-release. + VUNSPEC_GET_FPSCR ; Represent fetch of FPSCR content. VUNSPEC_SET_FPSCR ; Represent assign of FPSCR content. VUNSPEC_PROBE_STACK_RANGE ; Represent stack range probing. VUNSPEC_CDP ; Represent the coprocessor cdp instruction. diff --git a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md index eb6ae7bea7927c666f36219797d54c0127001bc1..dfb1031431af3ec87d9cccdee35db04e0adffe04 100644 --- a/gcc/config/arm/vfp.md +++ b/gcc/config/arm/vfp.md @@ -2096,9 +2096,8 @@ (define_insn "<fmaxmin><mode>3" ;; Write Floating-point Status and Control Register. (define_insn "set_fpscr" - [(set (reg:SI VFPCC_REGNUM) - (unspec_volatile:SI - [(match_operand:SI 0 "register_operand" "r")] VUNSPEC_SET_FPSCR))] + [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")] + VUNSPEC_SET_FPSCR)] "TARGET_VFP_BASE" "mcr\\tp10, 7, %0, cr1, cr0, 0\\t @SET_FPSCR" [(set_attr "type" "mrs")]) @@ -2106,7 +2105,7 @@ (define_insn "set_fpscr" ;; Read Floating-point Status and Control Register. (define_insn "get_fpscr" [(set (match_operand:SI 0 "register_operand" "=r") - (unspec:SI [(reg:SI VFPCC_REGNUM)] UNSPEC_GET_FPSCR))] + (unspec_volatile:SI [(const_int 0)] VUNSPEC_GET_FPSCR))] "TARGET_VFP_BASE" "mrc\\tp10, 7, %0, cr1, cr0, 0\\t @GET_FPSCR" [(set_attr "type" "mrs")])
Hi, MVE made changes to {get,set}_fpscr to enable the compiler to optimize unneccesary gets and sets when using these for intrinsics that use and/or write the carry bit. However, these actually get and set the full FPSCR register and are used by fp env intrinsics to modify the fp context. So MVE should not be using these. This fixes regressions for gcc.dg/atomic/c11-atomic-exec-5.c Bootstrapped and tested arm-linux-gnueabihf. Is this OK for trunk? gcc/ChangeLog: 2020-03-20 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/arm/unspecs.md (UNSPEC_GET_FPSCR): Rename this to ... (VUNSPEC_GET_FPSCR): ... this, and move it to vunspec. * config/arm/vfp.md: (get_fpscr, set_fpscr): Revert to old patterns.