[8/9] pinctrl: tegra: Renumber the GG.0 and GG.1 pins
diff mbox series

Message ID 20200319122737.3063291-9-thierry.reding@gmail.com
State New
Headers show
Series
  • pinctrl: tegra: Support SFIO/GPIO programming
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Commit Message

Thierry Reding March 19, 2020, 12:27 p.m. UTC
From: Thierry Reding <treding@nvidia.com>

There is no need to define these at a specific offset since they are the
only pins defined for this SoC generation. Begin numbering them at 0.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 drivers/pinctrl/tegra/pinctrl-tegra194.c | 11 ++++-------
 1 file changed, 4 insertions(+), 7 deletions(-)

Comments

Vidya Sagar March 19, 2020, 5:08 p.m. UTC | #1
On 3/19/2020 5:57 PM, Thierry Reding wrote:
> External email: Use caution opening links or attachments
> 
> 
> From: Thierry Reding <treding@nvidia.com>
> 
> There is no need to define these at a specific offset since they are the
> only pins defined for this SoC generation. Begin numbering them at 0.
> 
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
>   drivers/pinctrl/tegra/pinctrl-tegra194.c | 11 ++++-------
>   1 file changed, 4 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/pinctrl/tegra/pinctrl-tegra194.c b/drivers/pinctrl/tegra/pinctrl-tegra194.c
> index 61fc7e680788..61afe5fe9dec 100644
> --- a/drivers/pinctrl/tegra/pinctrl-tegra194.c
> +++ b/drivers/pinctrl/tegra/pinctrl-tegra194.c
> @@ -24,17 +24,14 @@
> 
>   /* Define unique ID for each pins */
>   enum pin_id {
> -       TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0 = 256,
> -       TEGRA_PIN_PEX_L5_RST_N_PGG1 = 257,
> -       TEGRA_PIN_NUM_GPIOS = 258,
> +       TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0,
> +       TEGRA_PIN_PEX_L5_RST_N_PGG1,
>   };
> 
>   /* Table for pin descriptor */
>   static const struct pinctrl_pin_desc tegra194_pins[] = {
> -       PINCTRL_PIN(TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0,
> -                   "TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0"),
> -       PINCTRL_PIN(TEGRA_PIN_PEX_L5_RST_N_PGG1,
> -                   "TEGRA_PIN_PEX_L5_RST_N_PGG1"),
> +       PINCTRL_PIN(TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0, "PEX_L5_CLKREQ_N_PGG0"),
> +       PINCTRL_PIN(TEGRA_PIN_PEX_L5_RST_N_PGG1, "PEX_L5_RST_N_PGG1"),
>   };
> 
>   static const unsigned int pex_l5_clkreq_n_pgg0_pins[] = {
> --
> 2.24.1
> 
Tested-by: Vidya Sagar <vidyas@nvidia.com>
Linus Walleij March 27, 2020, 10:45 a.m. UTC | #2
On Thu, Mar 19, 2020 at 1:28 PM Thierry Reding <thierry.reding@gmail.com> wrote:

> From: Thierry Reding <treding@nvidia.com>
>
> There is no need to define these at a specific offset since they are the
> only pins defined for this SoC generation. Begin numbering them at 0.
>
> Signed-off-by: Thierry Reding <treding@nvidia.com>

Patch applied!

Yours,
Linus Walleij

Patch
diff mbox series

diff --git a/drivers/pinctrl/tegra/pinctrl-tegra194.c b/drivers/pinctrl/tegra/pinctrl-tegra194.c
index 61fc7e680788..61afe5fe9dec 100644
--- a/drivers/pinctrl/tegra/pinctrl-tegra194.c
+++ b/drivers/pinctrl/tegra/pinctrl-tegra194.c
@@ -24,17 +24,14 @@ 
 
 /* Define unique ID for each pins */
 enum pin_id {
-	TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0 = 256,
-	TEGRA_PIN_PEX_L5_RST_N_PGG1 = 257,
-	TEGRA_PIN_NUM_GPIOS = 258,
+	TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0,
+	TEGRA_PIN_PEX_L5_RST_N_PGG1,
 };
 
 /* Table for pin descriptor */
 static const struct pinctrl_pin_desc tegra194_pins[] = {
-	PINCTRL_PIN(TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0,
-		    "TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0"),
-	PINCTRL_PIN(TEGRA_PIN_PEX_L5_RST_N_PGG1,
-		    "TEGRA_PIN_PEX_L5_RST_N_PGG1"),
+	PINCTRL_PIN(TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0, "PEX_L5_CLKREQ_N_PGG0"),
+	PINCTRL_PIN(TEGRA_PIN_PEX_L5_RST_N_PGG1, "PEX_L5_RST_N_PGG1"),
 };
 
 static const unsigned int pex_l5_clkreq_n_pgg0_pins[] = {