[7/9] pinctrl: tegra: Do not add default pin range on Tegra194
diff mbox series

Message ID 20200319122737.3063291-8-thierry.reding@gmail.com
State New
Headers show
Series
  • pinctrl: tegra: Support SFIO/GPIO programming
Related show

Commit Message

Thierry Reding March 19, 2020, 12:27 p.m. UTC
From: Thierry Reding <treding@nvidia.com>

On Tegra194, almost all of the pin control programming happens in early
boot firmware, so there is no use in having a pin range defined for all
the pins.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 drivers/pinctrl/tegra/pinctrl-tegra.c    | 2 +-
 drivers/pinctrl/tegra/pinctrl-tegra194.c | 1 -
 2 files changed, 1 insertion(+), 2 deletions(-)

Comments

Vidya Sagar March 19, 2020, 5:08 p.m. UTC | #1
On 3/19/2020 5:57 PM, Thierry Reding wrote:
> External email: Use caution opening links or attachments
> 
> 
> From: Thierry Reding <treding@nvidia.com>
> 
> On Tegra194, almost all of the pin control programming happens in early
> boot firmware, so there is no use in having a pin range defined for all
> the pins.
> 
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
>   drivers/pinctrl/tegra/pinctrl-tegra.c    | 2 +-
>   drivers/pinctrl/tegra/pinctrl-tegra194.c | 1 -
>   2 files changed, 1 insertion(+), 2 deletions(-)
> 
> diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c
> index c8246cc2c4fd..65511bf27d34 100644
> --- a/drivers/pinctrl/tegra/pinctrl-tegra.c
> +++ b/drivers/pinctrl/tegra/pinctrl-tegra.c
> @@ -794,7 +794,7 @@ int tegra_pinctrl_probe(struct platform_device *pdev,
> 
>          tegra_pinctrl_clear_parked_bits(pmx);
> 
> -       if (!tegra_pinctrl_gpio_node_has_range(pmx))
> +       if (pmx->soc->ngpios > 0 && !tegra_pinctrl_gpio_node_has_range(pmx))
>                  pinctrl_add_gpio_range(pmx->pctl, &tegra_pinctrl_gpio_range);
> 
>          platform_set_drvdata(pdev, pmx);
> diff --git a/drivers/pinctrl/tegra/pinctrl-tegra194.c b/drivers/pinctrl/tegra/pinctrl-tegra194.c
> index d4e84530158c..61fc7e680788 100644
> --- a/drivers/pinctrl/tegra/pinctrl-tegra194.c
> +++ b/drivers/pinctrl/tegra/pinctrl-tegra194.c
> @@ -134,7 +134,6 @@ static const struct tegra_pingroup tegra194_groups[] = {
>   };
> 
>   static const struct tegra_pinctrl_soc_data tegra194_pinctrl = {
> -       .ngpios = TEGRA_PIN_NUM_GPIOS,
>          .pins = tegra194_pins,
>          .npins = ARRAY_SIZE(tegra194_pins),
>          .functions = tegra194_functions,
> --
> 2.24.1
> 
Tested-by: Vidya Sagar <vidyas@nvidia.com>
Linus Walleij March 27, 2020, 10:44 a.m. UTC | #2
On Thu, Mar 19, 2020 at 1:28 PM Thierry Reding <thierry.reding@gmail.com> wrote:

> From: Thierry Reding <treding@nvidia.com>
>
> On Tegra194, almost all of the pin control programming happens in early
> boot firmware, so there is no use in having a pin range defined for all
> the pins.
>
> Signed-off-by: Thierry Reding <treding@nvidia.com>

Patch applied!

Yours,
Linus Walleij

Patch
diff mbox series

diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c
index c8246cc2c4fd..65511bf27d34 100644
--- a/drivers/pinctrl/tegra/pinctrl-tegra.c
+++ b/drivers/pinctrl/tegra/pinctrl-tegra.c
@@ -794,7 +794,7 @@  int tegra_pinctrl_probe(struct platform_device *pdev,
 
 	tegra_pinctrl_clear_parked_bits(pmx);
 
-	if (!tegra_pinctrl_gpio_node_has_range(pmx))
+	if (pmx->soc->ngpios > 0 && !tegra_pinctrl_gpio_node_has_range(pmx))
 		pinctrl_add_gpio_range(pmx->pctl, &tegra_pinctrl_gpio_range);
 
 	platform_set_drvdata(pdev, pmx);
diff --git a/drivers/pinctrl/tegra/pinctrl-tegra194.c b/drivers/pinctrl/tegra/pinctrl-tegra194.c
index d4e84530158c..61fc7e680788 100644
--- a/drivers/pinctrl/tegra/pinctrl-tegra194.c
+++ b/drivers/pinctrl/tegra/pinctrl-tegra194.c
@@ -134,7 +134,6 @@  static const struct tegra_pingroup tegra194_groups[] = {
 };
 
 static const struct tegra_pinctrl_soc_data tegra194_pinctrl = {
-	.ngpios = TEGRA_PIN_NUM_GPIOS,
 	.pins = tegra194_pins,
 	.npins = ARRAY_SIZE(tegra194_pins),
 	.functions = tegra194_functions,