[4/9] pinctrl: tegra: Fix whitespace issues for improved readability
diff mbox series

Message ID 20200319122737.3063291-5-thierry.reding@gmail.com
State New
Headers show
Series
  • pinctrl: tegra: Support SFIO/GPIO programming
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Commit Message

Thierry Reding March 19, 2020, 12:27 p.m. UTC
From: Thierry Reding <treding@nvidia.com>

Fix a few whitespace inconsistencies to make the code easier to read.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 drivers/pinctrl/tegra/pinctrl-tegra194.c | 33 ++++++++++++------------
 1 file changed, 17 insertions(+), 16 deletions(-)

Comments

Vidya Sagar March 19, 2020, 5:06 p.m. UTC | #1
On 3/19/2020 5:57 PM, Thierry Reding wrote:
> External email: Use caution opening links or attachments
> 
> 
> From: Thierry Reding <treding@nvidia.com>
> 
> Fix a few whitespace inconsistencies to make the code easier to read.
> 
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
>   drivers/pinctrl/tegra/pinctrl-tegra194.c | 33 ++++++++++++------------
>   1 file changed, 17 insertions(+), 16 deletions(-)
> 
> diff --git a/drivers/pinctrl/tegra/pinctrl-tegra194.c b/drivers/pinctrl/tegra/pinctrl-tegra194.c
> index daf44cf240c9..d4e84530158c 100644
> --- a/drivers/pinctrl/tegra/pinctrl-tegra194.c
> +++ b/drivers/pinctrl/tegra/pinctrl-tegra194.c
> @@ -59,6 +59,7 @@ enum tegra_mux_dt {
>          {                                       \
>                  .name = #lid,                   \
>          }
> +
>   static struct tegra_function tegra194_functions[] = {
>          TEGRA_PIN_FUNCTION(rsvd0),
>          TEGRA_PIN_FUNCTION(rsvd1),
> @@ -70,7 +71,7 @@ static struct tegra_function tegra194_functions[] = {
>   #define DRV_PINGROUP_ENTRY_Y(r, drvdn_b, drvdn_w, drvup_b,     \
>                               drvup_w, slwr_b, slwr_w, slwf_b,   \
>                               slwf_w, bank)                      \
> -               .drv_reg = ((r)),                       \
> +               .drv_reg = ((r)),                               \
>                  .drv_bank = bank,                               \
>                  .drvdn_bit = drvdn_b,                           \
>                  .drvdn_width = drvdn_w,                         \
> @@ -89,7 +90,7 @@ static struct tegra_function tegra194_functions[] = {
>                  .hsm_bit = -1,                                  \
>                  .mux_bank = bank,                               \
>                  .mux_bit = 0,                                   \
> -               .pupd_reg = ((r)),              \
> +               .pupd_reg = ((r)),                              \
>                  .pupd_bank = bank,                              \
>                  .pupd_bit = 2,                                  \
>                  .tri_reg = ((r)),                               \
> @@ -109,20 +110,20 @@ static struct tegra_function tegra194_functions[] = {
> 
>   #define PINGROUP(pg_name, f0, f1, f2, f3, r, bank, pupd, e_lpbk,       \
>                   e_input, e_lpdr, e_od, schmitt_b, drvtype, io_rail)    \
> -       {                                                       \
> -               .name = #pg_name,                               \
> -               .pins = pg_name##_pins,                         \
> -               .npins = ARRAY_SIZE(pg_name##_pins),            \
> -                       .funcs = {                              \
> -                               TEGRA_MUX_##f0,                 \
> -                               TEGRA_MUX_##f1,                 \
> -                               TEGRA_MUX_##f2,                 \
> -                               TEGRA_MUX_##f3,                 \
> -                       },                                      \
> -               PIN_PINGROUP_ENTRY_Y(r, bank, pupd, e_lpbk,     \
> -                                    e_input, e_od,             \
> -                                    schmitt_b, drvtype),       \
> -               drive_##pg_name,                                \
> +       {                                                               \
> +               .name = #pg_name,                                       \
> +               .pins = pg_name##_pins,                                 \
> +               .npins = ARRAY_SIZE(pg_name##_pins),                    \
> +                       .funcs = {                                      \
> +                               TEGRA_MUX_##f0,                         \
> +                               TEGRA_MUX_##f1,                         \
> +                               TEGRA_MUX_##f2,                         \
> +                               TEGRA_MUX_##f3,                         \
> +                       },                                              \
> +               PIN_PINGROUP_ENTRY_Y(r, bank, pupd, e_lpbk,             \
> +                                    e_input, e_od,                     \
> +                                    schmitt_b, drvtype),               \
> +               drive_##pg_name,                                        \
>          }
> 
>   static const struct tegra_pingroup tegra194_groups[] = {
> --
> 2.24.1
> 
Tested-by: Vidya Sagar <vidyas@nvidia.com>
Linus Walleij March 27, 2020, 10:40 a.m. UTC | #2
On Thu, Mar 19, 2020 at 1:27 PM Thierry Reding <thierry.reding@gmail.com> wrote:

> From: Thierry Reding <treding@nvidia.com>
>
> Fix a few whitespace inconsistencies to make the code easier to read.
>
> Signed-off-by: Thierry Reding <treding@nvidia.com>

Patch applied!

Yours,
Linus Walleij

Patch
diff mbox series

diff --git a/drivers/pinctrl/tegra/pinctrl-tegra194.c b/drivers/pinctrl/tegra/pinctrl-tegra194.c
index daf44cf240c9..d4e84530158c 100644
--- a/drivers/pinctrl/tegra/pinctrl-tegra194.c
+++ b/drivers/pinctrl/tegra/pinctrl-tegra194.c
@@ -59,6 +59,7 @@  enum tegra_mux_dt {
 	{					\
 		.name = #lid,			\
 	}
+
 static struct tegra_function tegra194_functions[] = {
 	TEGRA_PIN_FUNCTION(rsvd0),
 	TEGRA_PIN_FUNCTION(rsvd1),
@@ -70,7 +71,7 @@  static struct tegra_function tegra194_functions[] = {
 #define DRV_PINGROUP_ENTRY_Y(r, drvdn_b, drvdn_w, drvup_b,	\
 			     drvup_w, slwr_b, slwr_w, slwf_b,	\
 			     slwf_w, bank)			\
-		.drv_reg = ((r)),			\
+		.drv_reg = ((r)),				\
 		.drv_bank = bank,				\
 		.drvdn_bit = drvdn_b,				\
 		.drvdn_width = drvdn_w,				\
@@ -89,7 +90,7 @@  static struct tegra_function tegra194_functions[] = {
 		.hsm_bit = -1,					\
 		.mux_bank = bank,				\
 		.mux_bit = 0,					\
-		.pupd_reg = ((r)),		\
+		.pupd_reg = ((r)),				\
 		.pupd_bank = bank,				\
 		.pupd_bit = 2,					\
 		.tri_reg = ((r)),				\
@@ -109,20 +110,20 @@  static struct tegra_function tegra194_functions[] = {
 
 #define PINGROUP(pg_name, f0, f1, f2, f3, r, bank, pupd, e_lpbk,	\
 		 e_input, e_lpdr, e_od, schmitt_b, drvtype, io_rail)	\
-	{							\
-		.name = #pg_name,				\
-		.pins = pg_name##_pins,				\
-		.npins = ARRAY_SIZE(pg_name##_pins),		\
-			.funcs = {				\
-				TEGRA_MUX_##f0,			\
-				TEGRA_MUX_##f1,			\
-				TEGRA_MUX_##f2,			\
-				TEGRA_MUX_##f3,			\
-			},					\
-		PIN_PINGROUP_ENTRY_Y(r, bank, pupd, e_lpbk,	\
-				     e_input, e_od,		\
-				     schmitt_b, drvtype),	\
-		drive_##pg_name,				\
+	{								\
+		.name = #pg_name,					\
+		.pins = pg_name##_pins,					\
+		.npins = ARRAY_SIZE(pg_name##_pins),			\
+			.funcs = {					\
+				TEGRA_MUX_##f0,				\
+				TEGRA_MUX_##f1,				\
+				TEGRA_MUX_##f2,				\
+				TEGRA_MUX_##f3,				\
+			},						\
+		PIN_PINGROUP_ENTRY_Y(r, bank, pupd, e_lpbk,		\
+				     e_input, e_od,			\
+				     schmitt_b, drvtype),		\
+		drive_##pg_name,					\
 	}
 
 static const struct tegra_pingroup tegra194_groups[] = {