| Message ID | 1584598352.9256.15242.camel@hbabu-laptop (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | powerpc/vas: Page fault handling for user space NX requests | expand |
| Context | Check | Description |
|---|---|---|
| snowpatch_ozlabs/apply_patch | success | Successfully applied on branch powerpc/merge (8a445cbcb9f5090cb07ec6cbb89a8a1fc99a0ff7) |
| snowpatch_ozlabs/checkpatch | warning | total: 0 errors, 0 warnings, 1 checks, 49 lines checked |
| snowpatch_ozlabs/needsstable | success | Patch has no Fixes tags |
Haren Myneni's on March 19, 2020 4:12 pm: > > This function allocates IRQ on a specific chip. VAS needs per chip > IRQ allocation and will have IRQ handler per VAS instance. Can't see a problem, but don't really know the XIVE code. Cédric seems like an obvious omission from CC here. Thanks, Nick > > Signed-off-by: Haren Myneni <haren@linux.ibm.com> > --- > arch/powerpc/include/asm/xive.h | 9 ++++++++- > arch/powerpc/sysdev/xive/native.c | 6 +++--- > 2 files changed, 11 insertions(+), 4 deletions(-) > > diff --git a/arch/powerpc/include/asm/xive.h b/arch/powerpc/include/asm/xive.h > index 93f982db..d08ea11 100644 > --- a/arch/powerpc/include/asm/xive.h > +++ b/arch/powerpc/include/asm/xive.h > @@ -5,6 +5,8 @@ > #ifndef _ASM_POWERPC_XIVE_H > #define _ASM_POWERPC_XIVE_H > > +#include <asm/opal-api.h> > + > #define XIVE_INVALID_VP 0xffffffff > > #ifdef CONFIG_PPC_XIVE > @@ -108,7 +110,6 @@ struct xive_q { > int xive_native_populate_irq_data(u32 hw_irq, > struct xive_irq_data *data); > void xive_cleanup_irq_data(struct xive_irq_data *xd); > -u32 xive_native_alloc_irq(void); > void xive_native_free_irq(u32 irq); > int xive_native_configure_irq(u32 hw_irq, u32 target, u8 prio, u32 sw_irq); > > @@ -137,6 +138,12 @@ int xive_native_set_queue_state(u32 vp_id, uint32_t prio, u32 qtoggle, > u32 qindex); > int xive_native_get_vp_state(u32 vp_id, u64 *out_state); > bool xive_native_has_queue_state_support(void); > +extern u32 xive_native_alloc_irq_on_chip(u32 chip_id); > + > +static inline u32 xive_native_alloc_irq(void) > +{ > + return xive_native_alloc_irq_on_chip(OPAL_XIVE_ANY_CHIP); > +} > > #else > > diff --git a/arch/powerpc/sysdev/xive/native.c b/arch/powerpc/sysdev/xive/native.c > index 0ff6b73..14d4406 100644 > --- a/arch/powerpc/sysdev/xive/native.c > +++ b/arch/powerpc/sysdev/xive/native.c > @@ -279,12 +279,12 @@ static int xive_native_get_ipi(unsigned int cpu, struct xive_cpu *xc) > } > #endif /* CONFIG_SMP */ > > -u32 xive_native_alloc_irq(void) > +u32 xive_native_alloc_irq_on_chip(u32 chip_id) > { > s64 rc; > > for (;;) { > - rc = opal_xive_allocate_irq(OPAL_XIVE_ANY_CHIP); > + rc = opal_xive_allocate_irq(chip_id); > if (rc != OPAL_BUSY) > break; > msleep(OPAL_BUSY_DELAY_MS); > @@ -293,7 +293,7 @@ u32 xive_native_alloc_irq(void) > return 0; > return rc; > } > -EXPORT_SYMBOL_GPL(xive_native_alloc_irq); > +EXPORT_SYMBOL_GPL(xive_native_alloc_irq_on_chip); > > void xive_native_free_irq(u32 irq) > { > -- > 1.8.3.1 > > > >
On 3/19/20 7:12 AM, Haren Myneni wrote: > > This function allocates IRQ on a specific chip. VAS needs per chip > IRQ allocation and will have IRQ handler per VAS instance. The pool of generic interrupt source (IPI) numbers is generally used by user space application which generally do not care on which chip the interrupt is allocated. It's used by the CXL driver and KVM for the guest interrupts. The CPU IPI are the exceptions. The underlying FW call will try to allocate on the chip of the CPU first and then on the others. If you specify a chip id, there is no fallback. Is it what you want ? Why do you need to allocate a generic interrupt source (IPI) from a specific chip ? Is it a VAS requirement ? Could you explain a bit more how it is used because there might be similar request. The code is fine. Thanks, C. > Signed-off-by: Haren Myneni <haren@linux.ibm.com> > --- > arch/powerpc/include/asm/xive.h | 9 ++++++++- > arch/powerpc/sysdev/xive/native.c | 6 +++--- > 2 files changed, 11 insertions(+), 4 deletions(-) > > diff --git a/arch/powerpc/include/asm/xive.h b/arch/powerpc/include/asm/xive.h > index 93f982db..d08ea11 100644 > --- a/arch/powerpc/include/asm/xive.h > +++ b/arch/powerpc/include/asm/xive.h > @@ -5,6 +5,8 @@ > #ifndef _ASM_POWERPC_XIVE_H > #define _ASM_POWERPC_XIVE_H > > +#include <asm/opal-api.h> > + > #define XIVE_INVALID_VP 0xffffffff > > #ifdef CONFIG_PPC_XIVE > @@ -108,7 +110,6 @@ struct xive_q { > int xive_native_populate_irq_data(u32 hw_irq, > struct xive_irq_data *data); > void xive_cleanup_irq_data(struct xive_irq_data *xd); > -u32 xive_native_alloc_irq(void); > void xive_native_free_irq(u32 irq); > int xive_native_configure_irq(u32 hw_irq, u32 target, u8 prio, u32 sw_irq); > > @@ -137,6 +138,12 @@ int xive_native_set_queue_state(u32 vp_id, uint32_t prio, u32 qtoggle, > u32 qindex); > int xive_native_get_vp_state(u32 vp_id, u64 *out_state); > bool xive_native_has_queue_state_support(void); > +extern u32 xive_native_alloc_irq_on_chip(u32 chip_id); > + > +static inline u32 xive_native_alloc_irq(void) > +{ > + return xive_native_alloc_irq_on_chip(OPAL_XIVE_ANY_CHIP); > +} > > #else > > diff --git a/arch/powerpc/sysdev/xive/native.c b/arch/powerpc/sysdev/xive/native.c > index 0ff6b73..14d4406 100644 > --- a/arch/powerpc/sysdev/xive/native.c > +++ b/arch/powerpc/sysdev/xive/native.c > @@ -279,12 +279,12 @@ static int xive_native_get_ipi(unsigned int cpu, struct xive_cpu *xc) > } > #endif /* CONFIG_SMP */ > > -u32 xive_native_alloc_irq(void) > +u32 xive_native_alloc_irq_on_chip(u32 chip_id) > { > s64 rc; > > for (;;) { > - rc = opal_xive_allocate_irq(OPAL_XIVE_ANY_CHIP); > + rc = opal_xive_allocate_irq(chip_id); > if (rc != OPAL_BUSY) > break; > msleep(OPAL_BUSY_DELAY_MS); > @@ -293,7 +293,7 @@ u32 xive_native_alloc_irq(void) > return 0; > return rc; > } > -EXPORT_SYMBOL_GPL(xive_native_alloc_irq); > +EXPORT_SYMBOL_GPL(xive_native_alloc_irq_on_chip); > > void xive_native_free_irq(u32 irq) > { >
On 3/19/20 7:12 AM, Haren Myneni wrote: > > This function allocates IRQ on a specific chip. VAS needs per chip > IRQ allocation and will have IRQ handler per VAS instance. > > Signed-off-by: Haren Myneni <haren@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Thanks, C. > --- > arch/powerpc/include/asm/xive.h | 9 ++++++++- > arch/powerpc/sysdev/xive/native.c | 6 +++--- > 2 files changed, 11 insertions(+), 4 deletions(-) > > diff --git a/arch/powerpc/include/asm/xive.h b/arch/powerpc/include/asm/xive.h > index 93f982db..d08ea11 100644 > --- a/arch/powerpc/include/asm/xive.h > +++ b/arch/powerpc/include/asm/xive.h > @@ -5,6 +5,8 @@ > #ifndef _ASM_POWERPC_XIVE_H > #define _ASM_POWERPC_XIVE_H > > +#include <asm/opal-api.h> > + > #define XIVE_INVALID_VP 0xffffffff > > #ifdef CONFIG_PPC_XIVE > @@ -108,7 +110,6 @@ struct xive_q { > int xive_native_populate_irq_data(u32 hw_irq, > struct xive_irq_data *data); > void xive_cleanup_irq_data(struct xive_irq_data *xd); > -u32 xive_native_alloc_irq(void); > void xive_native_free_irq(u32 irq); > int xive_native_configure_irq(u32 hw_irq, u32 target, u8 prio, u32 sw_irq); > > @@ -137,6 +138,12 @@ int xive_native_set_queue_state(u32 vp_id, uint32_t prio, u32 qtoggle, > u32 qindex); > int xive_native_get_vp_state(u32 vp_id, u64 *out_state); > bool xive_native_has_queue_state_support(void); > +extern u32 xive_native_alloc_irq_on_chip(u32 chip_id); > + > +static inline u32 xive_native_alloc_irq(void) > +{ > + return xive_native_alloc_irq_on_chip(OPAL_XIVE_ANY_CHIP); > +} > > #else > > diff --git a/arch/powerpc/sysdev/xive/native.c b/arch/powerpc/sysdev/xive/native.c > index 0ff6b73..14d4406 100644 > --- a/arch/powerpc/sysdev/xive/native.c > +++ b/arch/powerpc/sysdev/xive/native.c > @@ -279,12 +279,12 @@ static int xive_native_get_ipi(unsigned int cpu, struct xive_cpu *xc) > } > #endif /* CONFIG_SMP */ > > -u32 xive_native_alloc_irq(void) > +u32 xive_native_alloc_irq_on_chip(u32 chip_id) > { > s64 rc; > > for (;;) { > - rc = opal_xive_allocate_irq(OPAL_XIVE_ANY_CHIP); > + rc = opal_xive_allocate_irq(chip_id); > if (rc != OPAL_BUSY) > break; > msleep(OPAL_BUSY_DELAY_MS); > @@ -293,7 +293,7 @@ u32 xive_native_alloc_irq(void) > return 0; > return rc; > } > -EXPORT_SYMBOL_GPL(xive_native_alloc_irq); > +EXPORT_SYMBOL_GPL(xive_native_alloc_irq_on_chip); > > void xive_native_free_irq(u32 irq) > { >
diff --git a/arch/powerpc/include/asm/xive.h b/arch/powerpc/include/asm/xive.h index 93f982db..d08ea11 100644 --- a/arch/powerpc/include/asm/xive.h +++ b/arch/powerpc/include/asm/xive.h @@ -5,6 +5,8 @@ #ifndef _ASM_POWERPC_XIVE_H #define _ASM_POWERPC_XIVE_H +#include <asm/opal-api.h> + #define XIVE_INVALID_VP 0xffffffff #ifdef CONFIG_PPC_XIVE @@ -108,7 +110,6 @@ struct xive_q { int xive_native_populate_irq_data(u32 hw_irq, struct xive_irq_data *data); void xive_cleanup_irq_data(struct xive_irq_data *xd); -u32 xive_native_alloc_irq(void); void xive_native_free_irq(u32 irq); int xive_native_configure_irq(u32 hw_irq, u32 target, u8 prio, u32 sw_irq); @@ -137,6 +138,12 @@ int xive_native_set_queue_state(u32 vp_id, uint32_t prio, u32 qtoggle, u32 qindex); int xive_native_get_vp_state(u32 vp_id, u64 *out_state); bool xive_native_has_queue_state_support(void); +extern u32 xive_native_alloc_irq_on_chip(u32 chip_id); + +static inline u32 xive_native_alloc_irq(void) +{ + return xive_native_alloc_irq_on_chip(OPAL_XIVE_ANY_CHIP); +} #else diff --git a/arch/powerpc/sysdev/xive/native.c b/arch/powerpc/sysdev/xive/native.c index 0ff6b73..14d4406 100644 --- a/arch/powerpc/sysdev/xive/native.c +++ b/arch/powerpc/sysdev/xive/native.c @@ -279,12 +279,12 @@ static int xive_native_get_ipi(unsigned int cpu, struct xive_cpu *xc) } #endif /* CONFIG_SMP */ -u32 xive_native_alloc_irq(void) +u32 xive_native_alloc_irq_on_chip(u32 chip_id) { s64 rc; for (;;) { - rc = opal_xive_allocate_irq(OPAL_XIVE_ANY_CHIP); + rc = opal_xive_allocate_irq(chip_id); if (rc != OPAL_BUSY) break; msleep(OPAL_BUSY_DELAY_MS); @@ -293,7 +293,7 @@ u32 xive_native_alloc_irq(void) return 0; return rc; } -EXPORT_SYMBOL_GPL(xive_native_alloc_irq); +EXPORT_SYMBOL_GPL(xive_native_alloc_irq_on_chip); void xive_native_free_irq(u32 irq) {
This function allocates IRQ on a specific chip. VAS needs per chip IRQ allocation and will have IRQ handler per VAS instance. Signed-off-by: Haren Myneni <haren@linux.ibm.com> --- arch/powerpc/include/asm/xive.h | 9 ++++++++- arch/powerpc/sysdev/xive/native.c | 6 +++--- 2 files changed, 11 insertions(+), 4 deletions(-)