From patchwork Tue Nov 15 11:14:03 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benoit Canet X-Patchwork-Id: 125776 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 996A9B6F6B for ; Tue, 15 Nov 2011 23:38:14 +1100 (EST) Received: from localhost ([::1]:59539 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RQGz7-0002WN-LH for incoming@patchwork.ozlabs.org; Tue, 15 Nov 2011 06:15:25 -0500 Received: from eggs.gnu.org ([140.186.70.92]:38739) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RQGyC-0008MJ-Lb for qemu-devel@nongnu.org; Tue, 15 Nov 2011 06:14:32 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RQGy8-0000ND-8K for qemu-devel@nongnu.org; Tue, 15 Nov 2011 06:14:28 -0500 Received: from mail-ww0-f41.google.com ([74.125.82.41]:54789) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RQGy7-0000K7-SO for qemu-devel@nongnu.org; Tue, 15 Nov 2011 06:14:24 -0500 Received: by mail-ww0-f41.google.com with SMTP id 25so6025521wwf.4 for ; Tue, 15 Nov 2011 03:14:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=4ALivAtu5k44YpouK835o+gRnZiH7gZaybTW0dW7YS0=; b=WtVmZu28ljERyBpSuIQa6mi8sQrs5bKzsJ5ZZPbc4aVX5Wsqg5af/6rEcCBJzcYqmE G8VttAOnIcoSq4FYmas719lBFILW2zTdsCg4ArWzbggySKQ8kl9H6RkKEAaO9tKJVOFi h7wAe773mb5r8YRtsO5tUwCBOCyH2p0zxQ7Wg= Received: by 10.216.80.39 with SMTP id j39mr4795546wee.61.1321355663553; Tue, 15 Nov 2011 03:14:23 -0800 (PST) Received: from Laure.box.in.chocolate-blue.net ([109.190.18.76]) by mx.google.com with ESMTPS id n18sm12476201wbm.19.2011.11.15.03.14.22 (version=SSLv3 cipher=OTHER); Tue, 15 Nov 2011 03:14:22 -0800 (PST) From: =?UTF-8?q?Beno=C3=AEt=20Canet?= To: qemu-devel@nongnu.org Date: Tue, 15 Nov 2011 12:14:03 +0100 Message-Id: <1321355644-1982-14-git-send-email-benoit.canet@gmail.com> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1321355644-1982-1-git-send-email-benoit.canet@gmail.com> References: <1321355644-1982-1-git-send-email-benoit.canet@gmail.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 74.125.82.41 Cc: blauwirbel@gmail.com, =?UTF-8?q?Beno=C3=AEt=20Canet?= , avi@redhat.com Subject: [Qemu-devel] [PATCH 13/14] sun4m_iommu: convert to memory API X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Benoit Canet --- hw/sun4m_iommu.c | 31 +++++++++++++++---------------- 1 files changed, 15 insertions(+), 16 deletions(-) diff --git a/hw/sun4m_iommu.c b/hw/sun4m_iommu.c index 6eeadfa..86d135a 100644 --- a/hw/sun4m_iommu.c +++ b/hw/sun4m_iommu.c @@ -128,13 +128,15 @@ typedef struct IOMMUState { SysBusDevice busdev; + MemoryRegion iomem; uint32_t regs[IOMMU_NREGS]; target_phys_addr_t iostart; qemu_irq irq; uint32_t version; } IOMMUState; -static uint32_t iommu_mem_readl(void *opaque, target_phys_addr_t addr) +static uint64_t iommu_mem_readl(void *opaque, target_phys_addr_t addr, + unsigned size) { IOMMUState *s = opaque; target_phys_addr_t saddr; @@ -156,7 +158,7 @@ static uint32_t iommu_mem_readl(void *opaque, target_phys_addr_t addr) } static void iommu_mem_writel(void *opaque, target_phys_addr_t addr, - uint32_t val) + uint64_t val, unsigned size) { IOMMUState *s = opaque; target_phys_addr_t saddr; @@ -237,16 +239,14 @@ static void iommu_mem_writel(void *opaque, target_phys_addr_t addr, } } -static CPUReadMemoryFunc * const iommu_mem_read[3] = { - NULL, - NULL, - iommu_mem_readl, -}; - -static CPUWriteMemoryFunc * const iommu_mem_write[3] = { - NULL, - NULL, - iommu_mem_writel, +static const MemoryRegionOps iommu_mem_ops = { + .read = iommu_mem_readl, + .write = iommu_mem_writel, + .endianness = DEVICE_NATIVE_ENDIAN, + .impl = { + .min_access_size = 4, + .max_access_size = 4, + }, }; static uint32_t iommu_page_get_flags(IOMMUState *s, target_phys_addr_t addr) @@ -347,13 +347,12 @@ static void iommu_reset(DeviceState *d) static int iommu_init1(SysBusDevice *dev) { IOMMUState *s = FROM_SYSBUS(IOMMUState, dev); - int io; sysbus_init_irq(dev, &s->irq); - io = cpu_register_io_memory(iommu_mem_read, iommu_mem_write, s, - DEVICE_NATIVE_ENDIAN); - sysbus_init_mmio(dev, IOMMU_NREGS * sizeof(uint32_t), io); + memory_region_init_io(&s->iomem, &iommu_mem_ops, s, + "iommu", IOMMU_NREGS * sizeof(uint32_t)); + sysbus_init_mmio_region(dev, &s->iomem); return 0; }