Patchwork LAN9118: Handling write to BYTE_TEST register

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Submitter bertrand.cachet@heig-vd.ch
Date Nov. 14, 2011, 9:39 a.m.
Message ID <1321263597-17479-1-git-send-email-bertrand.cachet@heig-vd.ch>
Download mbox | patch
Permalink /patch/125504/
State New
Headers show

Comments

bertrand.cachet@heig-vd.ch - Nov. 14, 2011, 9:39 a.m.
Prevent LAN9118 driver to finish in hardware error when writing
to the BYTE_TEST register.

This register (even if ReadOnly) is used to wake-up the device when it is in
low power consumption mode.

Add case for BYTE_TEST  in lan9118_writel method. Just write some documentation
explaining use its use.

Signed-off-by: Bertrand Cachet <bertrand.cachet@heig-vd.ch>
---
 hw/lan9118.c |    9 +++++++++
 1 files changed, 9 insertions(+), 0 deletions(-)
Peter Maydell - Nov. 17, 2011, 10:57 a.m.
On 14 November 2011 09:39, Bertrand Cachet <bertrand.cachet@heig-vd.ch> wrote:
> @@ -977,6 +977,15 @@ static void lan9118_writel(void *opaque, target_phys_addr_t offset,
>         s->pmt_ctrl &= ~0x34e;
>         s->pmt_ctrl |= (val & 0x34e);
>         break;
> +    case CSR_BYTE_TEST:
> +        /* Even if this register is marked ReadOnly in the datasheet,
> +           a write to this register will wake up the device when
> +           PM_MODE is currently in D1 or D2 mode.
> +
> +           As Power Modes are not handled in this driver, we will
> +           leave this case with no implementation.
> +         */
> +        break;
>     case CSR_GPIO_CFG:
>         /* Probably just enabling LEDs.  */
>         s->gpio_cfg = val & 0x7777071f;

Having thought about this a little, I think we should have the code
to modify the pmt_ctrl register here, but with a comment that explains
that this is currently a no-op since we are always in power mode D0.

There should also be a second patch in the series that corrects
the handling for the other RO and WO registers (which should
be read as zero and writes ignored, as per the datasheet).

-- PMM

Patch

diff --git a/hw/lan9118.c b/hw/lan9118.c
index f8149e6..65096d4 100644
--- a/hw/lan9118.c
+++ b/hw/lan9118.c
@@ -977,6 +977,15 @@  static void lan9118_writel(void *opaque, target_phys_addr_t offset,
         s->pmt_ctrl &= ~0x34e;
         s->pmt_ctrl |= (val & 0x34e);
         break;
+    case CSR_BYTE_TEST:
+        /* Even if this register is marked ReadOnly in the datasheet,
+           a write to this register will wake up the device when 
+           PM_MODE is currently in D1 or D2 mode.
+
+           As Power Modes are not handled in this driver, we will 
+           leave this case with no implementation.
+         */
+        break;
     case CSR_GPIO_CFG:
         /* Probably just enabling LEDs.  */
         s->gpio_cfg = val & 0x7777071f;