| Message ID | 20200312145900.2054-41-zhiwei_liu@c-sky.com |
|---|---|
| State | New |
| Headers | show |
| Series | target/riscv: support vector extension v0.7.1 | expand |
On 3/12/20 7:58 AM, LIU Zhiwei wrote: > + > +/* Vector Floating-Point Merge Instruction */ > +static bool opfvf_vfmerge_check(DisasContext *s, arg_rmrr *a) > +{ > + return (vext_check_isa_ill(s, RVV) && > + vext_check_overlap_mask(s, a->rd, a->vm, false) && > + vext_check_reg(s, a->rd, false) && > + vext_check_reg(s, a->rs2, false) && > + ((a->vm == 0) || (a->rs2 == 0)) && > + (s->sew != 0)); > +} > +GEN_OPFVF_TRANS(vfmerge_vfm, opfvf_vfmerge_check) Similar comments as for integer merge, using tcg_gen_gvec_dup_i64 for unpredicated merges. In fact, there's no reason at all to define a helper function for this one. I would expect you do be able to use the exact same helpers as for the integer merges. r~
On 2020/3/15 6:47, Richard Henderson wrote: > On 3/12/20 7:58 AM, LIU Zhiwei wrote: >> + >> +/* Vector Floating-Point Merge Instruction */ >> +static bool opfvf_vfmerge_check(DisasContext *s, arg_rmrr *a) >> +{ >> + return (vext_check_isa_ill(s, RVV) && >> + vext_check_overlap_mask(s, a->rd, a->vm, false) && >> + vext_check_reg(s, a->rd, false) && >> + vext_check_reg(s, a->rs2, false) && >> + ((a->vm == 0) || (a->rs2 == 0)) && >> + (s->sew != 0)); >> +} >> +GEN_OPFVF_TRANS(vfmerge_vfm, opfvf_vfmerge_check) > Similar comments as for integer merge, using tcg_gen_gvec_dup_i64 for > unpredicated merges. > > In fact, there's no reason at all to define a helper function for this one. I > would expect you do be able to use the exact same helpers as for the integer > merges. Do you mean that I should expands TCGv to TCGv_i64 for vmv.v.x in translation? So that I can reuse it. void gen_helper_vmv_v_x(TCG_ptr, TCGv_i64, TCGv_env, TCGv_i32); Zhiwei > > r~
On 3/15/20 8:41 PM, LIU Zhiwei wrote: > > > On 2020/3/15 6:47, Richard Henderson wrote: >> On 3/12/20 7:58 AM, LIU Zhiwei wrote: >>> + >>> +/* Vector Floating-Point Merge Instruction */ >>> +static bool opfvf_vfmerge_check(DisasContext *s, arg_rmrr *a) >>> +{ >>> + return (vext_check_isa_ill(s, RVV) && >>> + vext_check_overlap_mask(s, a->rd, a->vm, false) && >>> + vext_check_reg(s, a->rd, false) && >>> + vext_check_reg(s, a->rs2, false) && >>> + ((a->vm == 0) || (a->rs2 == 0)) && >>> + (s->sew != 0)); >>> +} >>> +GEN_OPFVF_TRANS(vfmerge_vfm, opfvf_vfmerge_check) >> Similar comments as for integer merge, using tcg_gen_gvec_dup_i64 for >> unpredicated merges. >> >> In fact, there's no reason at all to define a helper function for this one. I >> would expect you do be able to use the exact same helpers as for the integer >> merges. > > Do you mean that I should expands TCGv to TCGv_i64 for vmv.v.x in translation? > So that I can reuse it. > > void gen_helper_vmv_v_x(TCG_ptr, TCGv_i64, TCGv_env, TCGv_i32); Oh, I see, yes currently the integer helper is TCGv. Yes, it might be easiest to extend to TCGv_i64. r~
diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 86f1498c06..c02b207b44 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -982,3 +982,7 @@ DEF_HELPER_6(vmford_vf_d, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_5(vfclass_v_h, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfclass_v_w, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfclass_v_d, void, ptr, ptr, ptr, env, i32) + +DEF_HELPER_6(vfmerge_vfm_h, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfmerge_vfm_w, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfmerge_vfm_d, void, ptr, ptr, i64, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 18b78ed82d..41074f314a 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -508,6 +508,7 @@ vmfge_vf 011111 . ..... ..... 101 ..... 1010111 @r_vm vmford_vv 011010 . ..... ..... 001 ..... 1010111 @r_vm vmford_vf 011010 . ..... ..... 101 ..... 1010111 @r_vm vfclass_v 100011 . ..... 10000 001 ..... 1010111 @r2_vm +vfmerge_vfm 010111 . ..... ..... 101 ..... 1010111 @r_vm vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm vsetvl 1000000 ..... ..... 111 ..... 1010111 @r diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c index 3971c3ebdb..1ddaee6dab 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -1921,3 +1921,15 @@ GEN_OPFVF_TRANS(vmford_vf, opfvf_cmp_check) /* Vector Floating-Point Classify Instruction */ GEN_OPFV_TRANS(vfclass_v, opfv_check) + +/* Vector Floating-Point Merge Instruction */ +static bool opfvf_vfmerge_check(DisasContext *s, arg_rmrr *a) +{ + return (vext_check_isa_ill(s, RVV) && + vext_check_overlap_mask(s, a->rd, a->vm, false) && + vext_check_reg(s, a->rd, false) && + vext_check_reg(s, a->rs2, false) && + ((a->vm == 0) || (a->rs2 == 0)) && + (s->sew != 0)); +} +GEN_OPFVF_TRANS(vfmerge_vfm, opfvf_vfmerge_check) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index e9f278643f..00f8d9344f 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -3914,3 +3914,31 @@ RVVCALL(OPFVV1, vfclass_v_d, OP_UU_D, H8, H8, fclass_d) GEN_VEXT_V_ENV(vfclass_v_h, 2, 2, clearh) GEN_VEXT_V_ENV(vfclass_v_w, 4, 4, clearl) GEN_VEXT_V_ENV(vfclass_v_d, 8, 8, clearq) + +/* Vector Floating-Point Merge Instruction */ +#define GEN_VFMERGE_VF(NAME, ETYPE, H, CLEAR_FN) \ +void HELPER(NAME)(void *vd, void *v0, uint64_t s1, \ + void *vs2, CPURISCVState *env, uint32_t desc) \ +{ \ + uint32_t mlen = vext_mlen(desc); \ + uint32_t vm = vext_vm(desc); \ + uint32_t vl = env->vl; \ + uint32_t esz = sizeof(ETYPE); \ + uint32_t vlmax = vext_maxsz(desc) / esz; \ + uint32_t i; \ + \ + for (i = 0; i < vl; i++) { \ + if (!vm && !vext_elem_mask(v0, mlen, i)) { \ + ETYPE s2 = *((ETYPE *)vs2 + H(i)); \ + *((ETYPE *)vd + H1(i)) = s2; \ + } else { \ + *((ETYPE *)vd + H(i)) = (ETYPE)s1; \ + } \ + } \ + if (i != 0) { \ + CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \ + } \ +} +GEN_VFMERGE_VF(vfmerge_vfm_h, int16_t, H2, clearh) +GEN_VFMERGE_VF(vfmerge_vfm_w, int32_t, H4, clearl) +GEN_VFMERGE_VF(vfmerge_vfm_d, int64_t, H8, clearq)
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> --- target/riscv/helper.h | 4 ++++ target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvv.inc.c | 12 +++++++++++ target/riscv/vector_helper.c | 28 +++++++++++++++++++++++++ 4 files changed, 45 insertions(+)