| Message ID | 1583807731-16484-2-git-send-email-bmeng.cn@gmail.com |
|---|---|
| State | Accepted |
| Commit | 215c3a7701913a12ba6727efb83be80ad8ed659b |
| Delegated to: | Andes |
| Headers | show |
| Series | riscv: Add new SBI v0.2 extensions support | expand |
Hi, >-----Original Message----- >From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Bin Meng >Sent: 10 March 2020 08:05 >To: Rick Chen <rick@andestech.com>; Anup Patel <anup.patel@wdc.com>; >Atish Patra <atish.patra@wdc.com>; Lukas Auer ><lukas.auer@aisec.fraunhofer.de>; U-Boot Mailing List <u- >boot@lists.denx.de> >Subject: [PATCH 1/5] riscv: Mark existing SBI as v0.1 SBI > >As per the new SBI specification, current SBI implementation version is >defined as 0.1 and will be removed/replaced in future. Each of the function >call in 0.1 is defined as a separate extension which makes easier to replace >them one at a time. > >Rename existing implementation to reflect that. This patch is just a >preparatory patch for SBI v0.2 and doesn't introduce any functional changes. > >This commit is inspired from Linux kernel patch: >https://patchwork.kernel.org/patch/11407355/ > >Signed-off-by: Bin Meng <bmeng.cn@gmail.com> >--- > > arch/riscv/include/asm/sbi.h | 40 +++++++++++++++++++++------------------- > 1 file changed, 21 insertions(+), 19 deletions(-) > >diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index >d5081f9..187ca58 100644 >--- a/arch/riscv/include/asm/sbi.h >+++ b/arch/riscv/include/asm/sbi.h >@@ -1,6 +1,7 @@ > /* SPDX-License-Identifier: GPL-2.0 */ > /* > * Copyright (C) 2015 Regents of the University of California >+ * Copyright (c) 2020 Western Digital Corporation or its affiliates. > * > * Taken from Linux arch/riscv/include/asm/sbi.h > */ >@@ -10,15 +11,15 @@ > > #include <linux/types.h> > >-#define SBI_SET_TIMER 0 >-#define SBI_CONSOLE_PUTCHAR 1 >-#define SBI_CONSOLE_GETCHAR 2 >-#define SBI_CLEAR_IPI 3 >-#define SBI_SEND_IPI 4 >-#define SBI_REMOTE_FENCE_I 5 >-#define SBI_REMOTE_SFENCE_VMA 6 >-#define SBI_REMOTE_SFENCE_VMA_ASID 7 >-#define SBI_SHUTDOWN 8 >+#define SBI_EXT_0_1_SET_TIMER 0x0 >+#define SBI_EXT_0_1_CONSOLE_PUTCHAR 0x1 #define >+SBI_EXT_0_1_CONSOLE_GETCHAR 0x2 #define SBI_EXT_0_1_CLEAR_IPI 0x3 >+#define SBI_EXT_0_1_SEND_IPI 0x4 #define SBI_EXT_0_1_REMOTE_FENCE_I >0x5 >+#define SBI_EXT_0_1_REMOTE_SFENCE_VMA 0x6 #define >+SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID 0x7 #define >SBI_EXT_0_1_SHUTDOWN 0x8 > > #define SBI_CALL(which, arg0, arg1, arg2, arg3) ({ \ > register uintptr_t a0 asm ("a0") = (uintptr_t)(arg0); \ >@@ -44,48 +45,48 @@ > > static inline void sbi_console_putchar(int ch) { >- SBI_CALL_1(SBI_CONSOLE_PUTCHAR, ch); >+ SBI_CALL_1(SBI_EXT_0_1_CONSOLE_PUTCHAR, ch); > } > > static inline int sbi_console_getchar(void) { >- return SBI_CALL_0(SBI_CONSOLE_GETCHAR); >+ return SBI_CALL_0(SBI_EXT_0_1_CONSOLE_GETCHAR); > } > > static inline void sbi_set_timer(uint64_t stime_value) { #if __riscv_xlen == 32 >- SBI_CALL_2(SBI_SET_TIMER, stime_value, stime_value >> 32); >+ SBI_CALL_2(SBI_EXT_0_1_SET_TIMER, stime_value, stime_value >> >32); > #else >- SBI_CALL_1(SBI_SET_TIMER, stime_value); >+ SBI_CALL_1(SBI_EXT_0_1_SET_TIMER, stime_value); > #endif > } > > static inline void sbi_shutdown(void) > { >- SBI_CALL_0(SBI_SHUTDOWN); >+ SBI_CALL_0(SBI_EXT_0_1_SHUTDOWN); > } > > static inline void sbi_clear_ipi(void) > { >- SBI_CALL_0(SBI_CLEAR_IPI); >+ SBI_CALL_0(SBI_EXT_0_1_CLEAR_IPI); > } > > static inline void sbi_send_ipi(const unsigned long *hart_mask) { >- SBI_CALL_1(SBI_SEND_IPI, hart_mask); >+ SBI_CALL_1(SBI_EXT_0_1_SEND_IPI, hart_mask); > } > > static inline void sbi_remote_fence_i(const unsigned long *hart_mask) { >- SBI_CALL_1(SBI_REMOTE_FENCE_I, hart_mask); >+ SBI_CALL_1(SBI_EXT_0_1_REMOTE_FENCE_I, hart_mask); > } > > static inline void sbi_remote_sfence_vma(const unsigned long *hart_mask, > unsigned long start, > unsigned long size) > { >- SBI_CALL_3(SBI_REMOTE_SFENCE_VMA, hart_mask, start, size); >+ SBI_CALL_3(SBI_EXT_0_1_REMOTE_SFENCE_VMA, hart_mask, start, >size); > } > > static inline void sbi_remote_sfence_vma_asid(const unsigned long >*hart_mask, @@ -93,7 +94,8 @@ static inline void >sbi_remote_sfence_vma_asid(const unsigned long *hart_mask, > unsigned long size, > unsigned long asid) > { >- SBI_CALL_4(SBI_REMOTE_SFENCE_VMA_ASID, hart_mask, start, size, >asid); >+ SBI_CALL_4(SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID, hart_mask, >+ start, size, asid); > } > > #endif Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com> >-- >2.7.4
diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index d5081f9..187ca58 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2015 Regents of the University of California + * Copyright (c) 2020 Western Digital Corporation or its affiliates. * * Taken from Linux arch/riscv/include/asm/sbi.h */ @@ -10,15 +11,15 @@ #include <linux/types.h> -#define SBI_SET_TIMER 0 -#define SBI_CONSOLE_PUTCHAR 1 -#define SBI_CONSOLE_GETCHAR 2 -#define SBI_CLEAR_IPI 3 -#define SBI_SEND_IPI 4 -#define SBI_REMOTE_FENCE_I 5 -#define SBI_REMOTE_SFENCE_VMA 6 -#define SBI_REMOTE_SFENCE_VMA_ASID 7 -#define SBI_SHUTDOWN 8 +#define SBI_EXT_0_1_SET_TIMER 0x0 +#define SBI_EXT_0_1_CONSOLE_PUTCHAR 0x1 +#define SBI_EXT_0_1_CONSOLE_GETCHAR 0x2 +#define SBI_EXT_0_1_CLEAR_IPI 0x3 +#define SBI_EXT_0_1_SEND_IPI 0x4 +#define SBI_EXT_0_1_REMOTE_FENCE_I 0x5 +#define SBI_EXT_0_1_REMOTE_SFENCE_VMA 0x6 +#define SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID 0x7 +#define SBI_EXT_0_1_SHUTDOWN 0x8 #define SBI_CALL(which, arg0, arg1, arg2, arg3) ({ \ register uintptr_t a0 asm ("a0") = (uintptr_t)(arg0); \ @@ -44,48 +45,48 @@ static inline void sbi_console_putchar(int ch) { - SBI_CALL_1(SBI_CONSOLE_PUTCHAR, ch); + SBI_CALL_1(SBI_EXT_0_1_CONSOLE_PUTCHAR, ch); } static inline int sbi_console_getchar(void) { - return SBI_CALL_0(SBI_CONSOLE_GETCHAR); + return SBI_CALL_0(SBI_EXT_0_1_CONSOLE_GETCHAR); } static inline void sbi_set_timer(uint64_t stime_value) { #if __riscv_xlen == 32 - SBI_CALL_2(SBI_SET_TIMER, stime_value, stime_value >> 32); + SBI_CALL_2(SBI_EXT_0_1_SET_TIMER, stime_value, stime_value >> 32); #else - SBI_CALL_1(SBI_SET_TIMER, stime_value); + SBI_CALL_1(SBI_EXT_0_1_SET_TIMER, stime_value); #endif } static inline void sbi_shutdown(void) { - SBI_CALL_0(SBI_SHUTDOWN); + SBI_CALL_0(SBI_EXT_0_1_SHUTDOWN); } static inline void sbi_clear_ipi(void) { - SBI_CALL_0(SBI_CLEAR_IPI); + SBI_CALL_0(SBI_EXT_0_1_CLEAR_IPI); } static inline void sbi_send_ipi(const unsigned long *hart_mask) { - SBI_CALL_1(SBI_SEND_IPI, hart_mask); + SBI_CALL_1(SBI_EXT_0_1_SEND_IPI, hart_mask); } static inline void sbi_remote_fence_i(const unsigned long *hart_mask) { - SBI_CALL_1(SBI_REMOTE_FENCE_I, hart_mask); + SBI_CALL_1(SBI_EXT_0_1_REMOTE_FENCE_I, hart_mask); } static inline void sbi_remote_sfence_vma(const unsigned long *hart_mask, unsigned long start, unsigned long size) { - SBI_CALL_3(SBI_REMOTE_SFENCE_VMA, hart_mask, start, size); + SBI_CALL_3(SBI_EXT_0_1_REMOTE_SFENCE_VMA, hart_mask, start, size); } static inline void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask, @@ -93,7 +94,8 @@ static inline void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask, unsigned long size, unsigned long asid) { - SBI_CALL_4(SBI_REMOTE_SFENCE_VMA_ASID, hart_mask, start, size, asid); + SBI_CALL_4(SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID, hart_mask, + start, size, asid); } #endif
As per the new SBI specification, current SBI implementation version is defined as 0.1 and will be removed/replaced in future. Each of the function call in 0.1 is defined as a separate extension which makes easier to replace them one at a time. Rename existing implementation to reflect that. This patch is just a preparatory patch for SBI v0.2 and doesn't introduce any functional changes. This commit is inspired from Linux kernel patch: https://patchwork.kernel.org/patch/11407355/ Signed-off-by: Bin Meng <bmeng.cn@gmail.com> --- arch/riscv/include/asm/sbi.h | 40 +++++++++++++++++++++------------------- 1 file changed, 21 insertions(+), 19 deletions(-)