From patchwork Wed Nov 9 20:46:35 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 124697 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 5951E1007DB for ; Thu, 10 Nov 2011 07:46:50 +1100 (EST) Received: from localhost ([::1]:59242 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ROF2k-0003Io-VK for incoming@patchwork.ozlabs.org; Wed, 09 Nov 2011 15:46:46 -0500 Received: from eggs.gnu.org ([140.186.70.92]:60658) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ROF2e-0003H0-Om for qemu-devel@nongnu.org; Wed, 09 Nov 2011 15:46:41 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ROF2d-0003nM-HN for qemu-devel@nongnu.org; Wed, 09 Nov 2011 15:46:40 -0500 Received: from mnementh.archaic.org.uk ([81.2.115.146]:48508) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ROF2d-0003nF-3Y for qemu-devel@nongnu.org; Wed, 09 Nov 2011 15:46:39 -0500 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1ROF2Z-0002gd-Jj; Wed, 09 Nov 2011 20:46:35 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Wed, 9 Nov 2011 20:46:35 +0000 Message-Id: <1320871595-10304-1-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 81.2.115.146 Cc: patches@linaro.org Subject: [Qemu-devel] [PATCH] hw/pxa2xx.c: Fix handling of R/WC bits in PMCR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Fix a bug in handling the write-one-to-clear bits in the PMCR which meant that we would always clear the bit even if the value written was a zero. Spotted by Coverity (see bug 887883). Signed-off-by: Peter Maydell --- hw/pxa2xx.c | 4 +++- 1 files changed, 3 insertions(+), 1 deletions(-) diff --git a/hw/pxa2xx.c b/hw/pxa2xx.c index bfc28a9..d38b922 100644 --- a/hw/pxa2xx.c +++ b/hw/pxa2xx.c @@ -114,7 +114,9 @@ static void pxa2xx_pm_write(void *opaque, target_phys_addr_t addr, switch (addr) { case PMCR: - s->pm_regs[addr >> 2] &= 0x15 & ~(value & 0x2a); + /* Clear the write-one-to-clear bits... */ + s->pm_regs[addr >> 2] &= ~(value & 0x2a); + /* ...and set the plain r/w bits */ s->pm_regs[addr >> 2] |= value & 0x15; break;