Message ID | 20200228210552.615672-32-seanga2@gmail.com |
---|---|
State | Superseded |
Delegated to: | Andes |
Headers | show
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Fri, 28 Feb 2020 13:06:42 -0800 (PST) From: Sean Anderson <seanga2@gmail.com> To: u-boot@lists.denx.de Cc: Rick Chen <rickchen36@gmail.com>, Bin Meng <bmeng.cn@gmail.com>, Sean Anderson <seanga2@gmail.com> Subject: [PATCH v5 31/33] riscv: Enable cpu clock if it is present Date: Fri, 28 Feb 2020 16:05:49 -0500 Message-Id: <20200228210552.615672-32-seanga2@gmail.com> X-Mailer: git-send-email 2.25.0 In-Reply-To: <20200228210552.615672-1-seanga2@gmail.com> References: <20200228210552.615672-1-seanga2@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.30rc1 Precedence: list List-Id: U-Boot discussion <u-boot.lists.denx.de> List-Unsubscribe: <https://lists.denx.de/options/u-boot>, <mailto:u-boot-request@lists.denx.de?subject=unsubscribe> List-Archive: <https://lists.denx.de/pipermail/u-boot/> List-Post: <mailto:u-boot@lists.denx.de> List-Help: <mailto:u-boot-request@lists.denx.de?subject=help> List-Subscribe: <https://lists.denx.de/listinfo/u-boot>, <mailto:u-boot-request@lists.denx.de?subject=subscribe> Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" <u-boot-bounces@lists.denx.de> X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de X-Virus-Status: Clean |
Series |
riscv: Add Sipeed Maix support
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expand
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diff --git a/drivers/cpu/riscv_cpu.c b/drivers/cpu/riscv_cpu.c index c6ed060abc..9ce58695aa 100644 --- a/drivers/cpu/riscv_cpu.c +++ b/drivers/cpu/riscv_cpu.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com> + * Copyright (C) 2020, Sean Anderson <seanga2@gmail.com> */ #include <clk.h> @@ -117,6 +118,24 @@ static int riscv_cpu_bind(struct udevice *dev) return 0; } +static int riscv_cpu_probe(struct udevice *dev) +{ + int ret = 0; + struct clk clk; + + /* Get a clock if it exists */ + ret = clk_get_by_index(dev, 0, &clk); + if (ret) + return 0; + + ret = clk_enable(&clk); + clk_free(&clk); + if (ret == -ENOSYS || ret == -ENOTSUPP) + return 0; + else + return ret; +} + static const struct cpu_ops riscv_cpu_ops = { .get_desc = riscv_cpu_get_desc, .get_info = riscv_cpu_get_info, @@ -133,6 +152,7 @@ U_BOOT_DRIVER(riscv_cpu) = { .id = UCLASS_CPU, .of_match = riscv_cpu_ids, .bind = riscv_cpu_bind, + .probe = riscv_cpu_probe, .ops = &riscv_cpu_ops, .flags = DM_FLAG_PRE_RELOC, };