From patchwork Wed Nov 9 18:03:33 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 124646 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id AC1D71007DC for ; Thu, 10 Nov 2011 05:04:43 +1100 (EST) Received: from localhost ([::1]:46425 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ROCVs-0008Uq-Nh for incoming@patchwork.ozlabs.org; Wed, 09 Nov 2011 13:04:40 -0500 Received: from eggs.gnu.org ([140.186.70.92]:35659) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ROCVc-0008Hx-DF for qemu-devel@nongnu.org; Wed, 09 Nov 2011 13:04:26 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ROCVa-0005eR-HV for qemu-devel@nongnu.org; Wed, 09 Nov 2011 13:04:24 -0500 Received: from mail-qw0-f45.google.com ([209.85.216.45]:45307) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ROCVa-0005eM-9N for qemu-devel@nongnu.org; Wed, 09 Nov 2011 13:04:22 -0500 Received: by qadz3 with SMTP id z3so2364892qad.4 for ; Wed, 09 Nov 2011 10:04:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=X+uZh7txTSOUluI6aOMPHXI6GO/9dWVyXMv4G0EdExM=; b=bslrzpRO7lga3D+3BnYelUsknVVRwZ2Ra31oIighp9pBtGeq4oyHPdUIJmgmlVfqox IC1rYXvzj8hsLbV6CQxs1DS6LbgMM8jHYmiKVNdPpqM0o2fWChApgCr5rdlLNMTpboRk dYmrQ6qc8ZvldyA//sggP78fnp2StGBMtqVrQ= Received: by 10.224.185.199 with SMTP id cp7mr3182767qab.68.1320861861804; Wed, 09 Nov 2011 10:04:21 -0800 (PST) Received: from localhost.localdomain (c-98-203-235-125.hsd1.wa.comcast.net. [98.203.235.125]) by mx.google.com with ESMTPS id z1sm5786992qao.1.2011.11.09.10.04.19 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 09 Nov 2011 10:04:21 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 9 Nov 2011 10:03:33 -0800 Message-Id: <1320861815-14317-2-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.6.4 In-Reply-To: <1320861815-14317-1-git-send-email-rth@twiddle.net> References: <1320861815-14317-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 209.85.216.45 Cc: Stefan Weil , Alexander Graf , Blue Swirl , Aurelien Jarno Subject: [Qemu-devel] [PATCH 1/3] tcg: Standardize on TCGReg as the enum for hard registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Most targets did not name the enum; tci used TCGRegister. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.h | 4 ++-- tcg/hppa/tcg-target.h | 4 ++-- tcg/i386/tcg-target.h | 4 ++-- tcg/ia64/tcg-target.h | 4 ++-- tcg/mips/tcg-target.h | 4 ++-- tcg/ppc/tcg-target.h | 4 ++-- tcg/ppc64/tcg-target.h | 4 ++-- tcg/sparc/tcg-target.h | 4 ++-- tcg/tci/tcg-target.h | 2 +- tci.c | 38 +++++++++++++++++++------------------- 10 files changed, 36 insertions(+), 36 deletions(-) diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 33afd97..48586c3 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -27,7 +27,7 @@ #undef TCG_TARGET_WORDS_BIGENDIAN #undef TCG_TARGET_STACK_GROWSUP -enum { +typedef enum { TCG_REG_R0 = 0, TCG_REG_R1, TCG_REG_R2, @@ -44,7 +44,7 @@ enum { TCG_REG_R13, TCG_REG_R14, TCG_REG_PC, -}; +} TCGReg; #define TCG_TARGET_NB_REGS 16 diff --git a/tcg/hppa/tcg-target.h b/tcg/hppa/tcg-target.h index ec9a7bf..7f3c4cc 100644 --- a/tcg/hppa/tcg-target.h +++ b/tcg/hppa/tcg-target.h @@ -32,7 +32,7 @@ #define TCG_TARGET_NB_REGS 32 -enum { +typedef enum { TCG_REG_R0 = 0, TCG_REG_R1, TCG_REG_RP, @@ -65,7 +65,7 @@ enum { TCG_REG_RET1, TCG_REG_SP, TCG_REG_R31, -}; +} TCGReg; #define TCG_CT_CONST_0 0x0100 #define TCG_CT_CONST_S5 0x0200 diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index b9c9d4e..7756e7b 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -36,7 +36,7 @@ # define TCG_TARGET_NB_REGS 8 #endif -enum { +typedef enum { TCG_REG_EAX = 0, TCG_REG_ECX, TCG_REG_EDX, @@ -64,7 +64,7 @@ enum { TCG_REG_RBP = TCG_REG_EBP, TCG_REG_RSI = TCG_REG_ESI, TCG_REG_RDI = TCG_REG_EDI, -}; +} TCGReg; #define TCG_CT_CONST_S32 0x100 #define TCG_CT_CONST_U32 0x200 diff --git a/tcg/ia64/tcg-target.h b/tcg/ia64/tcg-target.h index 578cf29..c388089 100644 --- a/tcg/ia64/tcg-target.h +++ b/tcg/ia64/tcg-target.h @@ -26,7 +26,7 @@ /* We only map the first 64 registers */ #define TCG_TARGET_NB_REGS 64 -enum { +typedef enum { TCG_REG_R0 = 0, TCG_REG_R1, TCG_REG_R2, @@ -91,7 +91,7 @@ enum { TCG_REG_R61, TCG_REG_R62, TCG_REG_R63, -}; +} TCGReg; #define TCG_CT_CONST_ZERO 0x100 #define TCG_CT_CONST_S22 0x200 diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index e2a2571..477bc38 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -31,7 +31,7 @@ #define TCG_TARGET_NB_REGS 32 -enum { +typedef enum { TCG_REG_ZERO = 0, TCG_REG_AT, TCG_REG_V0, @@ -64,7 +64,7 @@ enum { TCG_REG_SP, TCG_REG_FP, TCG_REG_RA, -}; +} TCGReg; #define TCG_CT_CONST_ZERO 0x100 #define TCG_CT_CONST_U16 0x200 diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index 25a6ea4..3f22aaa 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -26,7 +26,7 @@ #define TCG_TARGET_WORDS_BIGENDIAN #define TCG_TARGET_NB_REGS 32 -enum { +typedef enum { TCG_REG_R0 = 0, TCG_REG_R1, TCG_REG_R2, @@ -59,7 +59,7 @@ enum { TCG_REG_R29, TCG_REG_R30, TCG_REG_R31 -}; +} TCGReg; /* used for function call generation */ #define TCG_REG_CALL_STACK TCG_REG_R1 diff --git a/tcg/ppc64/tcg-target.h b/tcg/ppc64/tcg-target.h index 8d1fb73..97eec08 100644 --- a/tcg/ppc64/tcg-target.h +++ b/tcg/ppc64/tcg-target.h @@ -26,7 +26,7 @@ #define TCG_TARGET_WORDS_BIGENDIAN #define TCG_TARGET_NB_REGS 32 -enum { +typedef enum { TCG_REG_R0 = 0, TCG_REG_R1, TCG_REG_R2, @@ -59,7 +59,7 @@ enum { TCG_REG_R29, TCG_REG_R30, TCG_REG_R31 -}; +} TCGReg; /* used for function call generation */ #define TCG_REG_CALL_STACK TCG_REG_R1 diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h index 1464ef4..c3fe131 100644 --- a/tcg/sparc/tcg-target.h +++ b/tcg/sparc/tcg-target.h @@ -27,7 +27,7 @@ #define TCG_TARGET_NB_REGS 32 -enum { +typedef enum { TCG_REG_G0 = 0, TCG_REG_G1, TCG_REG_G2, @@ -60,7 +60,7 @@ enum { TCG_REG_I5, TCG_REG_I6, TCG_REG_I7, -}; +} TCGReg; #define TCG_CT_CONST_S11 0x100 #define TCG_CT_CONST_S13 0x200 diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 81ded86..cb5858c 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -150,7 +150,7 @@ typedef enum { #endif /* Special value UINT8_MAX is used by TCI to encode constant values. */ TCG_CONST = UINT8_MAX -} TCGRegister; +} TCGReg; void tci_disas(uint8_t opc); diff --git a/tci.c b/tci.c index f17785d..a20a714 100644 --- a/tci.c +++ b/tci.c @@ -63,90 +63,90 @@ void *tci_tb_ptr; static tcg_target_ulong tci_reg[TCG_TARGET_NB_REGS]; -static tcg_target_ulong tci_read_reg(TCGRegister index) +static tcg_target_ulong tci_read_reg(TCGReg index) { assert(index < ARRAY_SIZE(tci_reg)); return tci_reg[index]; } #if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64 -static int8_t tci_read_reg8s(TCGRegister index) +static int8_t tci_read_reg8s(TCGReg index) { return (int8_t)tci_read_reg(index); } #endif #if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64 -static int16_t tci_read_reg16s(TCGRegister index) +static int16_t tci_read_reg16s(TCGReg index) { return (int16_t)tci_read_reg(index); } #endif #if TCG_TARGET_REG_BITS == 64 -static int32_t tci_read_reg32s(TCGRegister index) +static int32_t tci_read_reg32s(TCGReg index) { return (int32_t)tci_read_reg(index); } #endif -static uint8_t tci_read_reg8(TCGRegister index) +static uint8_t tci_read_reg8(TCGReg index) { return (uint8_t)tci_read_reg(index); } -static uint16_t tci_read_reg16(TCGRegister index) +static uint16_t tci_read_reg16(TCGReg index) { return (uint16_t)tci_read_reg(index); } -static uint32_t tci_read_reg32(TCGRegister index) +static uint32_t tci_read_reg32(TCGReg index) { return (uint32_t)tci_read_reg(index); } #if TCG_TARGET_REG_BITS == 64 -static uint64_t tci_read_reg64(TCGRegister index) +static uint64_t tci_read_reg64(TCGReg index) { return tci_read_reg(index); } #endif -static void tci_write_reg(TCGRegister index, tcg_target_ulong value) +static void tci_write_reg(TCGReg index, tcg_target_ulong value) { assert(index < ARRAY_SIZE(tci_reg)); assert(index != TCG_AREG0); tci_reg[index] = value; } -static void tci_write_reg8s(TCGRegister index, int8_t value) +static void tci_write_reg8s(TCGReg index, int8_t value) { tci_write_reg(index, value); } -static void tci_write_reg16s(TCGRegister index, int16_t value) +static void tci_write_reg16s(TCGReg index, int16_t value) { tci_write_reg(index, value); } #if TCG_TARGET_REG_BITS == 64 -static void tci_write_reg32s(TCGRegister index, int32_t value) +static void tci_write_reg32s(TCGReg index, int32_t value) { tci_write_reg(index, value); } #endif -static void tci_write_reg8(TCGRegister index, uint8_t value) +static void tci_write_reg8(TCGReg index, uint8_t value) { tci_write_reg(index, value); } -static void tci_write_reg16(TCGRegister index, uint16_t value) +static void tci_write_reg16(TCGReg index, uint16_t value) { tci_write_reg(index, value); } -static void tci_write_reg32(TCGRegister index, uint32_t value) +static void tci_write_reg32(TCGReg index, uint32_t value) { tci_write_reg(index, value); } @@ -159,7 +159,7 @@ static void tci_write_reg64(uint32_t high_index, uint32_t low_index, tci_write_reg(high_index, value >> 32); } #elif TCG_TARGET_REG_BITS == 64 -static void tci_write_reg64(TCGRegister index, uint64_t value) +static void tci_write_reg64(TCGReg index, uint64_t value) { tci_write_reg(index, value); } @@ -290,7 +290,7 @@ static target_ulong tci_read_ulong(uint8_t **tb_ptr) static tcg_target_ulong tci_read_ri(uint8_t **tb_ptr) { tcg_target_ulong value; - TCGRegister r = **tb_ptr; + TCGReg r = **tb_ptr; *tb_ptr += 1; if (r == TCG_CONST) { value = tci_read_i(tb_ptr); @@ -304,7 +304,7 @@ static tcg_target_ulong tci_read_ri(uint8_t **tb_ptr) static uint32_t tci_read_ri32(uint8_t **tb_ptr) { uint32_t value; - TCGRegister r = **tb_ptr; + TCGReg r = **tb_ptr; *tb_ptr += 1; if (r == TCG_CONST) { value = tci_read_i32(tb_ptr); @@ -326,7 +326,7 @@ static uint64_t tci_read_ri64(uint8_t **tb_ptr) static uint64_t tci_read_ri64(uint8_t **tb_ptr) { uint64_t value; - TCGRegister r = **tb_ptr; + TCGReg r = **tb_ptr; *tb_ptr += 1; if (r == TCG_CONST) { value = tci_read_i64(tb_ptr);