From patchwork Thu Feb 27 20:40:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Grimm X-Patchwork-Id: 1246096 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 48T4QQ3Hpcz9sQt for ; Fri, 28 Feb 2020 07:43:58 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 48T4QP0JPrzDrF2 for ; Fri, 28 Feb 2020 07:43:57 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=linux.ibm.com (client-ip=148.163.158.5; helo=mx0a-001b2d01.pphosted.com; envelope-from=grimm@linux.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 48T4MM5WbJzDr68 for ; Fri, 28 Feb 2020 07:41:19 +1100 (AEDT) Received: from pps.filterd (m0098416.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 01RKUGxo089497 for ; Thu, 27 Feb 2020 15:41:17 -0500 Received: from pps.reinject (localhost [127.0.0.1]) by mx0b-001b2d01.pphosted.com with ESMTP id 2yden2xbch-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Thu, 27 Feb 2020 15:41:17 -0500 Received: from m0098416.ppops.net (m0098416.ppops.net [127.0.0.1]) by pps.reinject (8.16.0.36/8.16.0.36) with SMTP id 01RKUMqN091931 for ; Thu, 27 Feb 2020 15:41:16 -0500 Received: from ppma03wdc.us.ibm.com (ba.79.3fa9.ip4.static.sl-reverse.com [169.63.121.186]) by mx0b-001b2d01.pphosted.com with ESMTP id 2yden2xbc9-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 27 Feb 2020 15:41:16 -0500 Received: from pps.filterd (ppma03wdc.us.ibm.com [127.0.0.1]) by ppma03wdc.us.ibm.com (8.16.0.27/8.16.0.27) with SMTP id 01RKeFcg011879; Thu, 27 Feb 2020 20:41:16 GMT Received: from b03cxnp08027.gho.boulder.ibm.com (b03cxnp08027.gho.boulder.ibm.com [9.17.130.19]) by ppma03wdc.us.ibm.com with ESMTP id 2ydcmm03vu-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 27 Feb 2020 20:41:16 +0000 Received: from b03ledav001.gho.boulder.ibm.com (b03ledav001.gho.boulder.ibm.com [9.17.130.232]) by b03cxnp08027.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 01RKfDmM60490052 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 27 Feb 2020 20:41:13 GMT Received: from b03ledav001.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id C1D536E054; Thu, 27 Feb 2020 20:41:13 +0000 (GMT) Received: from b03ledav001.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id B879C6E050; Thu, 27 Feb 2020 20:41:12 +0000 (GMT) Received: from alain.ibm.com (unknown [9.80.218.175]) by b03ledav001.gho.boulder.ibm.com (Postfix) with ESMTP; Thu, 27 Feb 2020 20:41:12 +0000 (GMT) From: Ryan Grimm To: oohall@gmail.com Date: Thu, 27 Feb 2020 15:40:15 -0500 Message-Id: <20200227204023.22125-9-grimm@linux.ibm.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20200227204023.22125-1-grimm@linux.ibm.com> References: <20200227204023.22125-1-grimm@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.572 definitions=2020-02-27_07:2020-02-26, 2020-02-27 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 mlxlogscore=796 adultscore=0 spamscore=0 suspectscore=1 priorityscore=1501 impostorscore=0 phishscore=0 clxscore=1015 malwarescore=0 mlxscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2001150001 definitions=main-2002270140 Subject: [Skiboot] [RFC PATCH v5 08/16] xscoms: read/write xscoms using ucall X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: janani@us.ibm.com, suka@us.ibm.com, skiboot@lists.ozlabs.org Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Madhavan Srinivasan xscom registers are in the secure memory area when secure mode is enabled. These registers cannot be accessed directly and need to use ultravisor services using ultracall. Signed-off-by: Madhavan Srinivasan Signed-off-by: Santosh Sivaraj [ linuxram: Set uv_present just after starting UV ] Signed-off-by: Ram Pai [ grimm: Don't check MSR in xscom read/write ] Signed-off-by: Ryan Grimm --- hw/ultravisor.c | 3 +++ include/ultravisor.h | 23 +++++++++++++++++++++++ include/xscom.h | 5 +++++ 3 files changed, 31 insertions(+) diff --git a/hw/ultravisor.c b/hw/ultravisor.c index 78281b41..ea14d8bd 100644 --- a/hw/ultravisor.c +++ b/hw/ultravisor.c @@ -13,6 +13,7 @@ static struct dt_node *uv_fw_node; static uint64_t uv_base_addr; +bool uv_present = false; struct memcons uv_memcons __section(".data.memcons") = { .magic = MEMCONS_MAGIC, @@ -58,6 +59,8 @@ int start_ultravisor(void *fdt) cpu_start_ultravisor(fdt); + uv_present = true; + while (i > 0) cpu_wait_job(jobs[--i], true); diff --git a/include/ultravisor.h b/include/ultravisor.h index 148041a0..0d4d4939 100644 --- a/include/ultravisor.h +++ b/include/ultravisor.h @@ -6,13 +6,36 @@ #include #include +#include #define UV_LOAD_MAX_SIZE 0x200000 +#define UCALL_BUFSIZE 4 +#define UV_READ_SCOM 0xF114 +#define UV_WRITE_SCOM 0xF118 + extern long ucall(unsigned long opcode, unsigned long *retbuf, ...); extern int start_uv(uint64_t entry, void *fdt); +extern bool uv_present; int start_ultravisor(void *fdt); void init_uv(void); +static inline int uv_xscom_read(u64 partid, u64 pcb_addr, u64 *val) +{ + unsigned long retbuf[UCALL_BUFSIZE]; + long rc; + + rc = ucall(UV_READ_SCOM, retbuf, partid, pcb_addr); + *val = retbuf[0]; + return rc; +} + +static inline int uv_xscom_write(u64 partid, u64 pcb_addr, u64 val) +{ + unsigned long retbuf[UCALL_BUFSIZE]; + + return ucall(UV_WRITE_SCOM, retbuf, partid, pcb_addr, val); +} + #endif /* __ULTRAVISOR_H */ diff --git a/include/xscom.h b/include/xscom.h index 8a466d56..2346db64 100644 --- a/include/xscom.h +++ b/include/xscom.h @@ -7,6 +7,7 @@ #include #include #include +#include /* * SCOM "partID" definitions: @@ -174,9 +175,13 @@ extern void _xscom_unlock(void); /* Targeted SCOM access */ static inline int xscom_read(uint32_t partid, uint64_t pcb_addr, uint64_t *val) { + if (uv_present) + return uv_xscom_read(partid, pcb_addr, val); return _xscom_read(partid, pcb_addr, val, true); } static inline int xscom_write(uint32_t partid, uint64_t pcb_addr, uint64_t val) { + if (uv_present) + return uv_xscom_write(partid, pcb_addr, val); return _xscom_write(partid, pcb_addr, val, true); } extern int xscom_write_mask(uint32_t partid, uint64_t pcb_addr, uint64_t val, uint64_t mask);