[v4,2/8] xive: Set the fused core mode properly
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Message ID 20200226101752.122998-3-svaidy@linux.vnet.ibm.com
State New
Headers show
Series
  • Initial fused-core support for POWER9
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Commit Message

Vaidyanathan Srinivasan Feb. 26, 2020, 10:17 a.m. UTC
From: Benjamin Herrenschmidt <benh@kernel.crashing.org>

Set or clear the fused core mode bit in the XIVE inits
properly. While HostBoot is supposed to do it, I prefer
not depending on it doing the right thing, since we already
configure that register ourselves anyway.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Michael Neuling <mikey@neuling.org>
---
 hw/xive.c              | 4 ++++
 include/xive-p9-regs.h | 1 +
 2 files changed, 5 insertions(+)

Patch
diff mbox series

diff --git a/hw/xive.c b/hw/xive.c
index 78b8ab3a..72742cf7 100644
--- a/hw/xive.c
+++ b/hw/xive.c
@@ -1509,6 +1509,10 @@  static bool xive_config_init(struct xive *x)
 	val |= PC_TCTXT_CFG_LGS_EN;
 	/* Disable pressure relief as we hijack the field in the VPs */
 	val &= ~PC_TCTXT_CFG_STORE_ACK;
+	if (this_cpu()->is_fused_core)
+		val |= PC_TCTXT_CFG_FUSE_CORE_EN;
+	else
+		val &= ~PC_TCTXT_CFG_FUSE_CORE_EN;
 	xive_regw(x, PC_TCTXT_CFG, val);
 	xive_dbg(x, "PC_TCTXT_CFG=%016llx\n", val);
 
diff --git a/include/xive-p9-regs.h b/include/xive-p9-regs.h
index 126ab525..56c94ec2 100644
--- a/include/xive-p9-regs.h
+++ b/include/xive-p9-regs.h
@@ -80,6 +80,7 @@ 
 #define  PC_TCTXT_CFG_TARGET_EN		PPC_BIT(1)
 #define  PC_TCTXT_CFG_LGS_EN		PPC_BIT(2)
 #define  PC_TCTXT_CFG_STORE_ACK		PPC_BIT(3)
+#define  PC_TCTXT_CFG_FUSE_CORE_EN PPC_BIT(4)
 #define  PC_TCTXT_CFG_HARD_CHIPID_BLK	PPC_BIT(8)
 #define  PC_TCTXT_CHIPID_OVERRIDE	PPC_BIT(9)
 #define  PC_TCTXT_CHIPID		PPC_BITMASK(12,15)