From patchwork Wed Nov 9 15:02:58 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benoit Canet X-Patchwork-Id: 124571 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id DA44B1007D9 for ; Thu, 10 Nov 2011 02:03:31 +1100 (EST) Received: from localhost ([::1]:60414 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RO9gW-0004kn-CN for incoming@patchwork.ozlabs.org; Wed, 09 Nov 2011 10:03:28 -0500 Received: from eggs.gnu.org ([140.186.70.92]:51901) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RO9gA-0004Zh-H9 for qemu-devel@nongnu.org; Wed, 09 Nov 2011 10:03:14 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RO9g9-0007gJ-7E for qemu-devel@nongnu.org; Wed, 09 Nov 2011 10:03:06 -0500 Received: from mail-wy0-f173.google.com ([74.125.82.173]:45600) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RO9g9-0007dy-1G for qemu-devel@nongnu.org; Wed, 09 Nov 2011 10:03:05 -0500 Received: by mail-wy0-f173.google.com with SMTP id 22so1829779wyh.4 for ; Wed, 09 Nov 2011 07:03:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=6SztvcYaKKJV6XP6GyHlU2dwwoCtLrZUhwr9GSuKae4=; b=ALFDqSDP0OW0RTwQxkJZy05Z1cMNmqXdY97n48Q035aOAvR8qTEXjgJfNY6g/moQPj FtT3kcJvIhvanalI3TfPtskdzxqY3YByi1qZme0JsJX+Bb34/yjfyMKsyEsAR9zyGRny YHyXVIyf9b5ztOliGfSATodnrihgRNNJE582s= Received: by 10.227.204.75 with SMTP id fl11mr97765wbb.21.1320850984614; Wed, 09 Nov 2011 07:03:04 -0800 (PST) Received: from Laure.box.in.chocolate-blue.net ([109.190.18.76]) by mx.google.com with ESMTPS id q30sm5920103wbn.17.2011.11.09.07.03.02 (version=SSLv3 cipher=OTHER); Wed, 09 Nov 2011 07:03:02 -0800 (PST) From: =?UTF-8?q?Beno=C3=AEt=20Canet?= To: qemu-devel@nongnu.org Date: Wed, 9 Nov 2011 16:02:58 +0100 Message-Id: <1320850979-6620-2-git-send-email-benoit.canet@gmail.com> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1320850979-6620-1-git-send-email-benoit.canet@gmail.com> References: <1320850979-6620-1-git-send-email-benoit.canet@gmail.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 74.125.82.173 Cc: peter.maydell@linaro.org, =?UTF-8?q?Beno=C3=AEt=20Canet?= , afaerber@suse.de Subject: [Qemu-devel] [PATCH 1/2] arm-linux-user: fix elfload.c's AT_HWCAP to reflect cpu features. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The cpu capabilities passed by the elf loader in AT_HWCAP where a constant. Make AT_HWCAP reflect the emulated cpu features in order to give correct clues to eglibc. Fix : [Bug 887516] [NEW] VFP support reported for the PXA270 Signed-off-by: Benoit Canet --- linux-user/elfload.c | 43 +++++++++++++++++++++++++++++++++++++++---- 1 files changed, 39 insertions(+), 4 deletions(-) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index a413976..73c939b 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -330,6 +330,10 @@ enum ARM_HWCAP_ARM_NEON = 1 << 11, ARM_HWCAP_ARM_VFPv3 = 1 << 12, ARM_HWCAP_ARM_VFPv3D16 = 1 << 13, + ARM_HWCAP_ARM_TLS = 1 << 14, + ARM_HWCAP_ARM_VFPv4 = 1 << 15, + ARM_HWCAP_ARM_IDIVA = 1 << 16, + ARM_HWCAP_ARM_IDIVT = 1 << 17, }; #define TARGET_HAS_GUEST_VALIDATE_BASE @@ -375,10 +379,41 @@ bool guest_validate_base(unsigned long guest_base) return 1; /* All good */ } -#define ELF_HWCAP (ARM_HWCAP_ARM_SWP | ARM_HWCAP_ARM_HALF \ - | ARM_HWCAP_ARM_THUMB | ARM_HWCAP_ARM_FAST_MULT \ - | ARM_HWCAP_ARM_FPA | ARM_HWCAP_ARM_VFP \ - | ARM_HWCAP_ARM_NEON | ARM_HWCAP_ARM_VFPv3 ) + +#define ELF_HWCAP get_elf_hwcap() + +static uint32_t get_elf_hwcap(void) +{ + CPUState *e = thread_env; + uint32_t hwcaps = 0; + + hwcaps |= ARM_HWCAP_ARM_SWP; + hwcaps |= ARM_HWCAP_ARM_HALF; + hwcaps |= ARM_HWCAP_ARM_THUMB; + hwcaps |= ARM_HWCAP_ARM_FAST_MULT; + + /* probe for the extra features */ +#define SET_HWCAP(feat, hwcap) \ + do {if (arm_feature(e, feat)) { hwcaps |= hwcap; } } while (0) + SET_HWCAP(ARM_FEATURE_VFP, ARM_HWCAP_ARM_VFP); + SET_HWCAP(ARM_FEATURE_IWMMXT, ARM_HWCAP_ARM_IWMMXT); + SET_HWCAP(ARM_FEATURE_THUMB2EE, ARM_HWCAP_ARM_THUMBEE); + SET_HWCAP(ARM_FEATURE_NEON, ARM_HWCAP_ARM_NEON); + SET_HWCAP(ARM_FEATURE_VFP3, ARM_HWCAP_ARM_VFPv3); + + /* Strictly should be ARM_FEATURE_V5TE but we don't distinguish + * as all our v5 cores are v5TE at the moment + */ + SET_HWCAP(ARM_FEATURE_V5, ARM_HWCAP_ARM_EDSP); + + SET_HWCAP(ARM_FEATURE_V6K, ARM_HWCAP_ARM_TLS); + SET_HWCAP(ARM_FEATURE_VFP4, ARM_HWCAP_ARM_VFPv4); + SET_HWCAP(ARM_FEATURE_ARM_DIV, ARM_HWCAP_ARM_IDIVA); + SET_HWCAP(ARM_FEATURE_THUMB_DIV, ARM_HWCAP_ARM_IDIVT); +#undef SET_HWCAP + + return hwcaps; +} #endif