| Message ID | 20200225093856.7328-3-dkangude@cadence.com |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
| Series | Add EDAC support for Cadence ddr controller | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success | |
| robh/dt-meta-schema | fail | build log |
On Tue, 25 Feb 2020 10:38:56 +0100, Dhananjay Kangude wrote: > Add documentation for cadence ddr memory controller EDAC DTS bindings > > Signed-off-by: Dhananjay Kangude <dkangude@cadence.com> > --- > .../devicetree/bindings/edac/cdns,ddr-edac.yaml | 56 ++++++++++++++++++++ > 1 files changed, 56 insertions(+), 0 deletions(-) > create mode 100644 Documentation/devicetree/bindings/edac/cdns,ddr-edac.yaml > My bot found errors running 'make dt_binding_check' on your patch: Documentation/devicetree/bindings/display/simple-framebuffer.example.dts:21.16-37.11: Warning (chosen_node_is_root): /example-0/chosen: chosen node must be at root node /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/edac/cdns,ddr-edac.example.dt.yaml: edac@fd100000: 'ranges' does not match any of the regexes: 'pinctrl-[0-9]+' See https://patchwork.ozlabs.org/patch/1243950 Please check and re-submit.
diff --git a/Documentation/devicetree/bindings/edac/cdns,ddr-edac.yaml b/Documentation/devicetree/bindings/edac/cdns,ddr-edac.yaml new file mode 100644 index 0000000..df70647 --- /dev/null +++ b/Documentation/devicetree/bindings/edac/cdns,ddr-edac.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/edac/cdns,ddr-edac.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cadence DDR IP with ECC support (EDAC) + +description: + This binding describes the Cadence DDR/LPDDR IP with ECC feature enabled + to detect and correct CE/UE errors. + +maintainers: + - Dhananjay Kangdue <dkangude@cadence.com> + +properties: + compatible: + enum: + - cdns,cadence-ddr4-mc-edac + + '#address-cells': + const: 1 + + '#size-cells': + const: 1 + + reg: + minItems: 1 + maxItems: 2 + items: + - description: + Register block of DDR/LPDDR apb registers up to mapped area. + Mapped area contains the register set for memory controller, + phy and PI module register set doesn't part of this mapping. + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + edac: edac@fd100000 { + compatible = "cdns,cadence-ddr4-mc-edac"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + reg = <0xfd100000 0x4000>; + interrupts = <0x00 0x01 0x04>; + }; +...
Add documentation for cadence ddr memory controller EDAC DTS bindings Signed-off-by: Dhananjay Kangude <dkangude@cadence.com> --- .../devicetree/bindings/edac/cdns,ddr-edac.yaml | 56 ++++++++++++++++++++ 1 files changed, 56 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/edac/cdns,ddr-edac.yaml