From patchwork Tue Nov 8 08:22:11 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jakub Jelinek X-Patchwork-Id: 124292 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 4B7191007D4 for ; Tue, 8 Nov 2011 19:22:46 +1100 (EST) Received: (qmail 32277 invoked by alias); 8 Nov 2011 08:22:41 -0000 Received: (qmail 32263 invoked by uid 22791); 8 Nov 2011 08:22:39 -0000 X-SWARE-Spam-Status: No, hits=-7.2 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, SPF_HELO_PASS X-Spam-Check-By: sourceware.org Received: from mx1.redhat.com (HELO mx1.redhat.com) (209.132.183.28) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Tue, 08 Nov 2011 08:22:15 +0000 Received: from int-mx01.intmail.prod.int.phx2.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id pA88MEun021302 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Tue, 8 Nov 2011 03:22:14 -0500 Received: from tyan-ft48-01.lab.bos.redhat.com (tyan-ft48-01.lab.bos.redhat.com [10.16.42.4]) by int-mx01.intmail.prod.int.phx2.redhat.com (8.13.8/8.13.8) with ESMTP id pA88MDEh032208 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Tue, 8 Nov 2011 03:22:14 -0500 Received: from tyan-ft48-01.lab.bos.redhat.com (tyan-ft48-01.lab.bos.redhat.com [127.0.0.1]) by tyan-ft48-01.lab.bos.redhat.com (8.14.4/8.14.4) with ESMTP id pA88MDgW030689; Tue, 8 Nov 2011 09:22:13 +0100 Received: (from jakub@localhost) by tyan-ft48-01.lab.bos.redhat.com (8.14.4/8.14.4/Submit) id pA88MCX5030687; Mon, 7 Nov 2011 21:22:12 -1100 Date: Mon, 7 Nov 2011 21:22:11 -1100 From: Jakub Jelinek To: David Edelsohn , Alan Modra , Michael Meissner Cc: gcc-patches@gcc.gnu.org Subject: [PATCH] Mixed int/float vcond{,u} for Altivec/VSX Message-ID: <20111108082211.GC17997@tyan-ft48-01.lab.bos.redhat.com> Reply-To: Jakub Jelinek MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.21 (2010-09-15) X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Hi! Working virtually out of Pago Pago for now. The following patch enables mixed mode COND_EXPR vectorization, similarly how it has been enabled for i?86/x86_64 a few months ago. For Altivec/VSX the only combinations that can be supported are V4SImode comparison (unsigned or signed) with V4SFmode then/else and destination and V4SFmode comparison with V4SImode then/else and destination. As Altivec/VSX uses mask vectors for comparisons, the change is trivial. With this we can vectorize gcc.dg/vect/{vect-cond-{8,9,10},slp-cond-2}.c with either -O3 -maltivec or -O3 -mvsx. Bootstrap/regtest pending, ok for trunk if it passes? 2011-11-08 Jakub Jelinek * config/rs6000/vector.md (vcondv4sfv4si, vcondv4siv4sf, vconduv4sfv4si): New patterns. * config/rs6000/rs6000.c (rs6000_emit_vector_cond_expr): Handle different dest_mode from comparison mode. * lib/target-supports.exp (check_effective_target_vect_cond_mixed): Enable also for powerpc*-*-*. Jakub --- gcc/config/rs6000/vector.md.jj 2011-09-02 16:29:39.000000000 +0200 +++ gcc/config/rs6000/vector.md 2011-11-08 08:46:55.000000000 +0100 @@ -406,6 +406,44 @@ (define_expand "vcond" FAIL; }") +(define_expand "vcondv4sfv4si" + [(set (match_operand:V4SF 0 "vfloat_operand" "") + (if_then_else:V4SF + (match_operator 3 "comparison_operator" + [(match_operand:V4SI 4 "vint_operand" "") + (match_operand:V4SI 5 "vint_operand" "")]) + (match_operand:V4SF 1 "vfloat_operand" "") + (match_operand:V4SF 2 "vfloat_operand" "")))] + "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode) + && VECTOR_UNIT_ALTIVEC_P (V4SImode)" + " +{ + if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2], + operands[3], operands[4], operands[5])) + DONE; + else + FAIL; +}") + +(define_expand "vcondv4siv4sf" + [(set (match_operand:V4SI 0 "vint_operand" "") + (if_then_else:V4SI + (match_operator 3 "comparison_operator" + [(match_operand:V4SF 4 "vfloat_operand" "") + (match_operand:V4SF 5 "vfloat_operand" "")]) + (match_operand:V4SI 1 "vint_operand" "") + (match_operand:V4SI 2 "vint_operand" "")))] + "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode) + && VECTOR_UNIT_ALTIVEC_P (V4SImode)" + " +{ + if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2], + operands[3], operands[4], operands[5])) + DONE; + else + FAIL; +}") + (define_expand "vcondu" [(set (match_operand:VEC_I 0 "vint_operand" "") (if_then_else:VEC_I @@ -424,6 +462,25 @@ (define_expand "vcondu" FAIL; }") +(define_expand "vconduv4sfv4si" + [(set (match_operand:V4SF 0 "vfloat_operand" "") + (if_then_else:V4SF + (match_operator 3 "comparison_operator" + [(match_operand:V4SI 4 "vint_operand" "") + (match_operand:V4SI 5 "vint_operand" "")]) + (match_operand:V4SF 1 "vfloat_operand" "") + (match_operand:V4SF 2 "vfloat_operand" "")))] + "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode) + && VECTOR_UNIT_ALTIVEC_P (V4SImode)" + " +{ + if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2], + operands[3], operands[4], operands[5])) + DONE; + else + FAIL; +}") + (define_expand "vector_eq" [(set (match_operand:VEC_C 0 "vlogical_operand" "") (eq:VEC_C (match_operand:VEC_C 1 "vlogical_operand" "") --- gcc/config/rs6000/rs6000.c.jj 2011-11-07 12:40:56.000000000 +0100 +++ gcc/config/rs6000/rs6000.c 2011-11-08 08:59:01.000000000 +0100 @@ -16775,6 +16775,7 @@ rs6000_emit_vector_cond_expr (rtx dest, rtx cond, rtx cc_op0, rtx cc_op1) { enum machine_mode dest_mode = GET_MODE (dest); + enum machine_mode mask_mode = GET_MODE (cc_op0); enum rtx_code rcode = GET_CODE (cond); enum machine_mode cc_mode = CCmode; rtx mask; @@ -16785,6 +16786,9 @@ rs6000_emit_vector_cond_expr (rtx dest, if (VECTOR_UNIT_NONE_P (dest_mode)) return 0; + gcc_assert (GET_MODE_SIZE (dest_mode) == GET_MODE_SIZE (mask_mode) + && GET_MODE_NUNITS (dest_mode) == GET_MODE_NUNITS (mask_mode)); + switch (rcode) { /* Swap operands if we can, and fall back to doing the operation as @@ -16815,7 +16819,7 @@ rs6000_emit_vector_cond_expr (rtx dest, } /* Get the vector mask for the given relational operations. */ - mask = rs6000_emit_vector_compare (rcode, cc_op0, cc_op1, dest_mode); + mask = rs6000_emit_vector_compare (rcode, cc_op0, cc_op1, mask_mode); if (!mask) return 0; @@ -16827,7 +16831,8 @@ rs6000_emit_vector_cond_expr (rtx dest, op_false = tmp; } - cond2 = gen_rtx_fmt_ee (NE, cc_mode, mask, CONST0_RTX (dest_mode)); + cond2 = gen_rtx_fmt_ee (NE, cc_mode, gen_lowpart (dest_mode, mask), + CONST0_RTX (dest_mode)); emit_insn (gen_rtx_SET (VOIDmode, dest, gen_rtx_IF_THEN_ELSE (dest_mode, --- gcc/testsuite/lib/target-supports.exp.jj 2011-11-07 20:32:08.000000000 +0100 +++ gcc/testsuite/lib/target-supports.exp 2011-11-08 09:11:16.000000000 +0100 @@ -3337,7 +3337,8 @@ proc check_effective_target_vect_cond_mi } else { set et_vect_cond_mixed_saved 0 if { [istarget i?86-*-*] - || [istarget x86_64-*-*] } { + || [istarget x86_64-*-*] + || [istarget powerpc*-*-*] } { set et_vect_cond_mixed_saved 1 } }