Patchwork Mixed int/float vcond{,u} for Altivec/VSX

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Submitter Jakub Jelinek
Date Nov. 8, 2011, 8:22 a.m.
Message ID <20111108082211.GC17997@tyan-ft48-01.lab.bos.redhat.com>
Download mbox | patch
Permalink /patch/124292/
State New
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Comments

Jakub Jelinek - Nov. 8, 2011, 8:22 a.m.
Hi!

Working virtually out of Pago Pago for now.

The following patch enables mixed mode COND_EXPR vectorization, similarly
how it has been enabled for i?86/x86_64 a few months ago.
For Altivec/VSX the only combinations that can be supported are
V4SImode comparison (unsigned or signed) with V4SFmode then/else and
destination and V4SFmode comparison with V4SImode then/else and destination.
As Altivec/VSX uses mask vectors for comparisons, the change is trivial.

With this we can vectorize gcc.dg/vect/{vect-cond-{8,9,10},slp-cond-2}.c
with either -O3 -maltivec or -O3 -mvsx.

Bootstrap/regtest pending, ok for trunk if it passes?

2011-11-08  Jakub Jelinek  <jakub@redhat.com>

	* config/rs6000/vector.md (vcondv4sfv4si, vcondv4siv4sf,
	vconduv4sfv4si): New patterns.
	* config/rs6000/rs6000.c (rs6000_emit_vector_cond_expr): Handle
	different dest_mode from comparison mode.

	* lib/target-supports.exp (check_effective_target_vect_cond_mixed):
	Enable also for powerpc*-*-*.


	Jakub
Michael Meissner - Nov. 8, 2011, 10:01 p.m.
On Mon, Nov 07, 2011 at 09:22:11PM -1100, Jakub Jelinek wrote:
> Hi!
> 
> Working virtually out of Pago Pago for now.
> 
> The following patch enables mixed mode COND_EXPR vectorization, similarly
> how it has been enabled for i?86/x86_64 a few months ago.
> For Altivec/VSX the only combinations that can be supported are
> V4SImode comparison (unsigned or signed) with V4SFmode then/else and
> destination and V4SFmode comparison with V4SImode then/else and destination.
> As Altivec/VSX uses mask vectors for comparisons, the change is trivial.
> 
> With this we can vectorize gcc.dg/vect/{vect-cond-{8,9,10},slp-cond-2}.c
> with either -O3 -maltivec or -O3 -mvsx.
> 
> Bootstrap/regtest pending, ok for trunk if it passes?
> 
> 2011-11-08  Jakub Jelinek  <jakub@redhat.com>
> 
> 	* config/rs6000/vector.md (vcondv4sfv4si, vcondv4siv4sf,
> 	vconduv4sfv4si): New patterns.
> 	* config/rs6000/rs6000.c (rs6000_emit_vector_cond_expr): Handle
> 	different dest_mode from comparison mode.
> 
> 	* lib/target-supports.exp (check_effective_target_vect_cond_mixed):
> 	Enable also for powerpc*-*-*.

Looks good to me, but David gets the final call on checking it in.
David Edelsohn - Nov. 8, 2011, 10:06 p.m.
On Tue, Nov 8, 2011 at 5:01 PM, Michael Meissner
<meissner@linux.vnet.ibm.com> wrote:
> On Mon, Nov 07, 2011 at 09:22:11PM -1100, Jakub Jelinek wrote:
>> Hi!
>>
>> Working virtually out of Pago Pago for now.
>>
>> The following patch enables mixed mode COND_EXPR vectorization, similarly
>> how it has been enabled for i?86/x86_64 a few months ago.
>> For Altivec/VSX the only combinations that can be supported are
>> V4SImode comparison (unsigned or signed) with V4SFmode then/else and
>> destination and V4SFmode comparison with V4SImode then/else and destination.
>> As Altivec/VSX uses mask vectors for comparisons, the change is trivial.
>>
>> With this we can vectorize gcc.dg/vect/{vect-cond-{8,9,10},slp-cond-2}.c
>> with either -O3 -maltivec or -O3 -mvsx.
>>
>> Bootstrap/regtest pending, ok for trunk if it passes?
>>
>> 2011-11-08  Jakub Jelinek  <jakub@redhat.com>
>>
>>       * config/rs6000/vector.md (vcondv4sfv4si, vcondv4siv4sf,
>>       vconduv4sfv4si): New patterns.
>>       * config/rs6000/rs6000.c (rs6000_emit_vector_cond_expr): Handle
>>       different dest_mode from comparison mode.
>>
>>       * lib/target-supports.exp (check_effective_target_vect_cond_mixed):
>>       Enable also for powerpc*-*-*.
>
> Looks good to me, but David gets the final call on checking it in.

Okay with me.

Thanks, David

Patch

--- gcc/config/rs6000/vector.md.jj	2011-09-02 16:29:39.000000000 +0200
+++ gcc/config/rs6000/vector.md	2011-11-08 08:46:55.000000000 +0100
@@ -406,6 +406,44 @@  (define_expand "vcond<mode><mode>"
     FAIL;
 }")
 
+(define_expand "vcondv4sfv4si"
+  [(set (match_operand:V4SF 0 "vfloat_operand" "")
+	(if_then_else:V4SF
+	 (match_operator 3 "comparison_operator"
+			 [(match_operand:V4SI 4 "vint_operand" "")
+			  (match_operand:V4SI 5 "vint_operand" "")])
+	 (match_operand:V4SF 1 "vfloat_operand" "")
+	 (match_operand:V4SF 2 "vfloat_operand" "")))]
+  "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
+   && VECTOR_UNIT_ALTIVEC_P (V4SImode)"
+  "
+{
+  if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
+				    operands[3], operands[4], operands[5]))
+    DONE;
+  else
+    FAIL;
+}")
+
+(define_expand "vcondv4siv4sf"
+  [(set (match_operand:V4SI 0 "vint_operand" "")
+	(if_then_else:V4SI
+	 (match_operator 3 "comparison_operator"
+			 [(match_operand:V4SF 4 "vfloat_operand" "")
+			  (match_operand:V4SF 5 "vfloat_operand" "")])
+	 (match_operand:V4SI 1 "vint_operand" "")
+	 (match_operand:V4SI 2 "vint_operand" "")))]
+  "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
+   && VECTOR_UNIT_ALTIVEC_P (V4SImode)"
+  "
+{
+  if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
+				    operands[3], operands[4], operands[5]))
+    DONE;
+  else
+    FAIL;
+}")
+
 (define_expand "vcondu<mode><mode>"
   [(set (match_operand:VEC_I 0 "vint_operand" "")
 	(if_then_else:VEC_I
@@ -424,6 +462,25 @@  (define_expand "vcondu<mode><mode>"
     FAIL;
 }")
 
+(define_expand "vconduv4sfv4si"
+  [(set (match_operand:V4SF 0 "vfloat_operand" "")
+	(if_then_else:V4SF
+	 (match_operator 3 "comparison_operator"
+			 [(match_operand:V4SI 4 "vint_operand" "")
+			  (match_operand:V4SI 5 "vint_operand" "")])
+	 (match_operand:V4SF 1 "vfloat_operand" "")
+	 (match_operand:V4SF 2 "vfloat_operand" "")))]
+  "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
+   && VECTOR_UNIT_ALTIVEC_P (V4SImode)"
+  "
+{
+  if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
+				    operands[3], operands[4], operands[5]))
+    DONE;
+  else
+    FAIL;
+}")
+
 (define_expand "vector_eq<mode>"
   [(set (match_operand:VEC_C 0 "vlogical_operand" "")
 	(eq:VEC_C (match_operand:VEC_C 1 "vlogical_operand" "")
--- gcc/config/rs6000/rs6000.c.jj	2011-11-07 12:40:56.000000000 +0100
+++ gcc/config/rs6000/rs6000.c	2011-11-08 08:59:01.000000000 +0100
@@ -16775,6 +16775,7 @@  rs6000_emit_vector_cond_expr (rtx dest, 
 			      rtx cond, rtx cc_op0, rtx cc_op1)
 {
   enum machine_mode dest_mode = GET_MODE (dest);
+  enum machine_mode mask_mode = GET_MODE (cc_op0);
   enum rtx_code rcode = GET_CODE (cond);
   enum machine_mode cc_mode = CCmode;
   rtx mask;
@@ -16785,6 +16786,9 @@  rs6000_emit_vector_cond_expr (rtx dest, 
   if (VECTOR_UNIT_NONE_P (dest_mode))
     return 0;
 
+  gcc_assert (GET_MODE_SIZE (dest_mode) == GET_MODE_SIZE (mask_mode)
+	      && GET_MODE_NUNITS (dest_mode) == GET_MODE_NUNITS (mask_mode));
+
   switch (rcode)
     {
       /* Swap operands if we can, and fall back to doing the operation as
@@ -16815,7 +16819,7 @@  rs6000_emit_vector_cond_expr (rtx dest, 
     }
 
   /* Get the vector mask for the given relational operations.  */
-  mask = rs6000_emit_vector_compare (rcode, cc_op0, cc_op1, dest_mode);
+  mask = rs6000_emit_vector_compare (rcode, cc_op0, cc_op1, mask_mode);
 
   if (!mask)
     return 0;
@@ -16827,7 +16831,8 @@  rs6000_emit_vector_cond_expr (rtx dest, 
       op_false = tmp;
     }
 
-  cond2 = gen_rtx_fmt_ee (NE, cc_mode, mask, CONST0_RTX (dest_mode));
+  cond2 = gen_rtx_fmt_ee (NE, cc_mode, gen_lowpart (dest_mode, mask),
+			  CONST0_RTX (dest_mode));
   emit_insn (gen_rtx_SET (VOIDmode,
 			  dest,
 			  gen_rtx_IF_THEN_ELSE (dest_mode,
--- gcc/testsuite/lib/target-supports.exp.jj	2011-11-07 20:32:08.000000000 +0100
+++ gcc/testsuite/lib/target-supports.exp	2011-11-08 09:11:16.000000000 +0100
@@ -3337,7 +3337,8 @@  proc check_effective_target_vect_cond_mi
     } else {
 	set et_vect_cond_mixed_saved 0
 	if { [istarget i?86-*-*]
-	     || [istarget x86_64-*-*] } {
+	     || [istarget x86_64-*-*]
+	     || [istarget powerpc*-*-*] } {
 	   set et_vect_cond_mixed_saved 1
 	}
     }