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[U-Boot] arm, davinci: Fix setting of the SDRAM configuration register

Message ID 1320742940-8418-1-git-send-email-christian.riesch@omicron.at
State Superseded, archived
Headers show

Commit Message

Christian Riesch Nov. 8, 2011, 9:02 a.m. UTC 
da850_ddr_setup() expects the BOOTUNLOCK bit to be set in
#define CONFIG_SYS_DA850_DDR2_SDBCR ... in include/configs/*.h
If BOOTUNLOCK is not set in this define, several configuration
bits will not be writeable and the code will not work.

Since the BOOTUNLOCK and TIMUNLOCK bits are not configuration options
but access control bits, this patch changes the code to work
irrespective of the value of these bits in CONFIG_SYS_DA850_DDR2_SDBCR.

Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Cc: Heiko Schocher <hs@denx.de>
Cc: Paulraj Sandeep <s-paulraj@ti.com>
---

This patch applies on top of these two patches:
[PATCH v3 1/2] arm, davinci: Rename AM1808 lowlevel functions to DA850
[PATCH v3 2/2] arm, davinci: Remove the duplication of LPSC functions in da850_lowlevel.c

Best regards, Christian

 arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c |   25 +++++++++++++++++-----
 1 files changed, 19 insertions(+), 6 deletions(-)
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Patch

diff --git a/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c b/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c
index 490ef8f..6f72491 100644
--- a/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c
+++ b/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c
@@ -184,18 +184,31 @@  int da850_ddr_setup(unsigned int freq)
 	clrbits_le32(&davinci_syscfg1_regs->ddr_slew,
 		(1 << DDR_SLEW_CMOSEN_BIT));
 
+	/*
+	 * SDRAM Configuration Register (SDCR):
+	 * First set the BOOTUNLOCK bit to make configuration bits
+	 * writeable.
+	 */ 
 	setbits_le32(&dv_ddr2_regs_ctrl->sdbcr, DV_DDR_BOOTUNLOCK);
 
-	writel((CONFIG_SYS_DA850_DDR2_SDBCR & ~0xf0000000) |
-		(readl(&dv_ddr2_regs_ctrl->sdbcr) & 0xf0000000), /*rsv Bytes*/
-		&dv_ddr2_regs_ctrl->sdbcr);
-	writel(CONFIG_SYS_DA850_DDR2_SDBCR2, &dv_ddr2_regs_ctrl->sdbcr2);
+	/* 
+	 * Write the new value of these bits and clear BOOTUNLOCK.
+	 * At the same time, set the TIMUNLOCK bit to allow changing 
+	 * the timing registers
+	 */
+	tmp = CONFIG_SYS_DA850_DDR2_SDBCR;
+	tmp &= ~(0x1 << DV_DDR_SDCR_BOOTUNLOCK_SHIFT);
+	tmp |= (0x1 << DV_DDR_SDCR_TIMUNLOCK_SHIFT);
+	writel(tmp, &dv_ddr2_regs_ctrl->sdbcr);
 
+	/* write memory configuration and timing */
+	writel(CONFIG_SYS_DA850_DDR2_SDBCR2, &dv_ddr2_regs_ctrl->sdbcr2);
 	writel(CONFIG_SYS_DA850_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr);
 	writel(CONFIG_SYS_DA850_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2);
 
-	clrbits_le32(&dv_ddr2_regs_ctrl->sdbcr,
-		(1 << DV_DDR_SDCR_TIMUNLOCK_SHIFT));
+	/* clear the TIMUNLOCK bit and write the value of the CL field */
+	tmp &= ~(0x1 << DV_DDR_SDCR_TIMUNLOCK_SHIFT);
+	writel(tmp, &dv_ddr2_regs_ctrl->sdbcr);
 
 	/*
 	 * LPMODEN and MCLKSTOPEN must be set!