Patchwork [rs6000] Reorganize powerpc builtins and enable target pragma/attribute to enable/disable builtins

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Submitter Michael Meissner
Date Nov. 7, 2011, 10:32 p.m.
Message ID <20111107223258.GA12073@hungry-tiger2.westford.ibm.com>
Download mbox | patch
Permalink /patch/124207/
State New
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Michael Meissner - Nov. 7, 2011, 10:32 p.m.
(Sorry if this is a duplicate, I'm setting up a new workstation, and I'm not
sure I have the outgoing linux mail setup, so I posted this from the old
workstation).

This patch rewrites the way builtins are handled in the rs6000 port so that
like the x86, when you do #pragma GCC target or attribute((target(...))) and it
enables or disables the builtins based on the current target attributes.  It
also defines or undefines the various hardware macros (__ARCH_<xxx>, __VSX__,
and __ALTIVEC__), and enables/disables the vector keyword.

I've done bootstrap builds with make check, and there is one minor regression,
which I will fix as a bug (gcc.target/powerpc/recip-5.c fails due to not
vectorizing the recip builtin) after this patch goes in.  I build a linuxpaired
compiler and verified that the paired builtins are being handled correctly.

I have some more ideas of cleanup (moving the large table in rs6000-c.c into
rs6000-builtins.def, and eliminating the various bdesc arrays, but for now, it
works, and hopefully is a bit cleaner than before).

Is this ok to check in?

[gcc]
2011-11-07  Michael Meissner  <meissner@tlinux.vnet.ibm.com>

	* config/rs6000/rs6000-builtins.def: Completely rewrite builtin
	handling to centralize more of the builtins in this file.  Change
	some builtin enumerations to be more consistant.  Use a new mask
	to hold the current builtins, including SPE and PAIRED builtins
	which no longer are set via target_flags masks.  Add
	-mdebug=builtin debug support.  For power machines, define all
	Altivec and VSX buitins when the compiler starts, but don't allow
	the use of a builtin unless the appropriate switch is used, or
	#pragma GCC target is used to change the options.  If the user
	uses #pragma GCC target, update the appropriate hardware macros.
	* common/config/rs6000/rs6000-common.c (rs6000_handle_option):
	Ditto.
	* config/rs6000/rs6000.opt (rs6000_builtin_mask): Ditto.
	* config/rs6000/rs6000-c.c (rs6000_macro_to_expand): Ditto.
	(rs6000_define_or_undefine_macro): Ditto.
	(rs6000_target_modify_macros): Ditto.
	(rs6000_cpu_cpp_builtins): Ditto.
	(altivec_overloaded_builtins): Ditto.
	(altivec_build_resolved_builtin): Ditto.
	* config/rs6000/rs6000.c (rs6000_target_modify_macros_ptr):
	Ditto.
	(rs6000_builtin_info): Ditto.
	(def_builtin): Ditto.
	(enable_mask_for_builtins): Ditto.
	(DEBUG_FMT_X): Ditto.
	(rs6000_debug_reg_global): Ditto.
	(rs6000_builtin_mask_calculate): Ditto.
	(rs6000_option_override_internal): Ditto.
	(rs6000_builtin_conversion): Ditto.
	(rs6000_builtin_vectorized_function): Ditto.
	(bdesc_3arg): Ditto.
	(bdesc_dst): Ditto.
	(bdesc_2arg): Ditto.
	(builtin_description_predicates): Ditto.
	(bdesc_altivec_preds): Ditto.
	(bdesc_spe_predicates): Ditto.
	(bdesc_spe_evsel): Ditto.
	(bdesc_paired_preds): Ditto.
	(bdesc_abs): Ditto.
	(bdesc_1arg): Ditto.
	(rs6000_overloaded_builtin_p): Ditto.
	(rs6000_expand_unop_builtin): Ditto.
	(bdesc_2arg_spe): Ditto.
	(spe_expand_builtin): Ditto.
	(rs6000_invalid_builtin): Ditto.
	(rs6000_expand_builtin): Ditto.
	(rs6000_init_builtins): Ditto.
	(spe_init_builtins): Ditto.
	(paired_init_builtins): Ditto.
	(altivec_init_builtins): Ditto.
	(builtin_function_type): Ditto.
	(rs6000_common_init_builtins): Ditto.
	(rs6000_builtin_reciprocal): Ditto.
	(rs6000_builtin_mask_names): Ditto.
	(rs6000_pragma_target_parse): Ditto.
	(rs6000_function_specific_print): Ditto.
	* config/rs6000/rs6000.h (MASK_DEBUG_BUILTIN): Ditto.
	(MASK_DEBUG_ALL): Ditto.
	(TARGET_DEBUG_BUILTIN): Ditto.
	(TARGET_EXTRA_BUILTINS): Ditto.
	(REGISTER_TARGET_PRAGMAS): Ditto.
	(enum rs6000_btc): Ditto.
	(RS6000_BTC_*): Ditto.
	(RS6000_BTM_*): Ditto.
	(enum rs6000_builtins): Ditto.
	* config/rs6000/rs6000-protos.h (rs6000_overloaded_builtin_p):
	Ditto.
	(rs6000_target_modify_macros): Ditto.
	(rs6000_target_modify_macros_ptr): Ditto.

[gcc/testsuite]
2011-11-07  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* testsuite/gcc.target/powerpc/ppc-target-4.c: New test for
	builtin functions being defined and undefined based on the #pragma
	GCC target settings.
David Edelsohn - Nov. 29, 2011, 2:38 a.m.
On Mon, Nov 7, 2011 at 5:32 PM, Michael Meissner
<meissner@linux.vnet.ibm.com> wrote:

> This patch rewrites the way builtins are handled in the rs6000 port so that
> like the x86, when you do #pragma GCC target or attribute((target(...))) and it
> enables or disables the builtins based on the current target attributes.  It
> also defines or undefines the various hardware macros (__ARCH_<xxx>, __VSX__,
> and __ALTIVEC__), and enables/disables the vector keyword.
>
> I've done bootstrap builds with make check, and there is one minor regression,
> which I will fix as a bug (gcc.target/powerpc/recip-5.c fails due to not
> vectorizing the recip builtin) after this patch goes in.  I build a linuxpaired
> compiler and verified that the paired builtins are being handled correctly.
>
> I have some more ideas of cleanup (moving the large table in rs6000-c.c into
> rs6000-builtins.def, and eliminating the various bdesc arrays, but for now, it
> works, and hopefully is a bit cleaner than before).
>
> Is this ok to check in?
>
> [gcc]
> 2011-11-07  Michael Meissner  <meissner@tlinux.vnet.ibm.com>
>
>        * config/rs6000/rs6000-builtins.def: Completely rewrite builtin
>        handling to centralize more of the builtins in this file.  Change
>        some builtin enumerations to be more consistant.  Use a new mask
>        to hold the current builtins, including SPE and PAIRED builtins
>        which no longer are set via target_flags masks.  Add
>        -mdebug=builtin debug support.  For power machines, define all
>        Altivec and VSX buitins when the compiler starts, but don't allow
>        the use of a builtin unless the appropriate switch is used, or
>        #pragma GCC target is used to change the options.  If the user
>        uses #pragma GCC target, update the appropriate hardware macros.
>        * common/config/rs6000/rs6000-common.c (rs6000_handle_option):
>        Ditto.
>        * config/rs6000/rs6000.opt (rs6000_builtin_mask): Ditto.
>        * config/rs6000/rs6000-c.c (rs6000_macro_to_expand): Ditto.
>        (rs6000_define_or_undefine_macro): Ditto.
>        (rs6000_target_modify_macros): Ditto.
>        (rs6000_cpu_cpp_builtins): Ditto.
>        (altivec_overloaded_builtins): Ditto.
>        (altivec_build_resolved_builtin): Ditto.
>        * config/rs6000/rs6000.c (rs6000_target_modify_macros_ptr):
>        Ditto.
>        (rs6000_builtin_info): Ditto.
>        (def_builtin): Ditto.
>        (enable_mask_for_builtins): Ditto.
>        (DEBUG_FMT_X): Ditto.
>        (rs6000_debug_reg_global): Ditto.
>        (rs6000_builtin_mask_calculate): Ditto.
>        (rs6000_option_override_internal): Ditto.
>        (rs6000_builtin_conversion): Ditto.
>        (rs6000_builtin_vectorized_function): Ditto.
>        (bdesc_3arg): Ditto.
>        (bdesc_dst): Ditto.
>        (bdesc_2arg): Ditto.
>        (builtin_description_predicates): Ditto.
>        (bdesc_altivec_preds): Ditto.
>        (bdesc_spe_predicates): Ditto.
>        (bdesc_spe_evsel): Ditto.
>        (bdesc_paired_preds): Ditto.
>        (bdesc_abs): Ditto.
>        (bdesc_1arg): Ditto.
>        (rs6000_overloaded_builtin_p): Ditto.
>        (rs6000_expand_unop_builtin): Ditto.
>        (bdesc_2arg_spe): Ditto.
>        (spe_expand_builtin): Ditto.
>        (rs6000_invalid_builtin): Ditto.
>        (rs6000_expand_builtin): Ditto.
>        (rs6000_init_builtins): Ditto.
>        (spe_init_builtins): Ditto.
>        (paired_init_builtins): Ditto.
>        (altivec_init_builtins): Ditto.
>        (builtin_function_type): Ditto.
>        (rs6000_common_init_builtins): Ditto.
>        (rs6000_builtin_reciprocal): Ditto.
>        (rs6000_builtin_mask_names): Ditto.
>        (rs6000_pragma_target_parse): Ditto.
>        (rs6000_function_specific_print): Ditto.
>        * config/rs6000/rs6000.h (MASK_DEBUG_BUILTIN): Ditto.
>        (MASK_DEBUG_ALL): Ditto.
>        (TARGET_DEBUG_BUILTIN): Ditto.
>        (TARGET_EXTRA_BUILTINS): Ditto.
>        (REGISTER_TARGET_PRAGMAS): Ditto.
>        (enum rs6000_btc): Ditto.
>        (RS6000_BTC_*): Ditto.
>        (RS6000_BTM_*): Ditto.
>        (enum rs6000_builtins): Ditto.
>        * config/rs6000/rs6000-protos.h (rs6000_overloaded_builtin_p):
>        Ditto.
>        (rs6000_target_modify_macros): Ditto.
>        (rs6000_target_modify_macros_ptr): Ditto.
>
> [gcc/testsuite]
> 2011-11-07  Michael Meissner  <meissner@linux.vnet.ibm.com>
>
>        * testsuite/gcc.target/powerpc/ppc-target-4.c: New test for
>        builtin functions being defined and undefined based on the #pragma
>        GCC target settings.

This is okay.

Thanks, David

Patch

Index: gcc/testsuite/gcc.target/powerpc/ppc-target-4.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/ppc-target-4.c	(.../trunk)	(revision 0)
+++ gcc/testsuite/gcc.target/powerpc/ppc-target-4.c	(.../branches/ibm/builtin2)	(revision 181121)
@@ -0,0 +1,83 @@ 
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -ffast-math -mcpu=power5 -mno-altivec -mabi=altivec -fno-unroll-loops" } */
+/* { dg-final { scan-assembler-times "vaddfp" 1 } } */
+/* { dg-final { scan-assembler-times "xvaddsp" 1 } } */
+/* { dg-final { scan-assembler-times "fadds" 1 } } */
+
+#ifndef SIZE
+#define SIZE 1024
+#endif
+
+#ifdef __ALTIVEC__
+#error "__ALTIVEC__ should not be defined."
+#endif
+
+#ifdef __VSX__
+#error "__VSX__ should not be defined."
+#endif
+
+#pragma GCC push_options
+#pragma GCC target("altivec,no-vsx")
+
+#ifndef __ALTIVEC__
+#error "__ALTIVEC__ should be defined."
+#endif
+
+#ifdef __VSX__
+#error "__VSX__ should not be defined."
+#endif
+
+void av_add (float *a, float *b, float *c)
+{
+  unsigned long i;
+  unsigned long n = SIZE / 4;
+  __vector float *av_a = (__vector float *)a;
+  __vector float *av_b = (__vector float *)b;
+  __vector float *av_c = (__vector float *)c;
+
+  for (i = 0; i < n; i++)
+    av_a[i] = __builtin_altivec_vaddfp (av_b[i], av_c[i]);
+}
+
+#pragma GCC target("vsx")
+
+#ifndef __ALTIVEC__
+#error "__ALTIVEC__ should be defined."
+#endif
+
+#ifndef __VSX__
+#error "__VSX__ should be defined."
+#endif
+
+void vsx_add (float *a, float *b, float *c)
+{
+  unsigned long i;
+  unsigned long n = SIZE / 4;
+  __vector float *vsx_a = (__vector float *)a;
+  __vector float *vsx_b = (__vector float *)b;
+  __vector float *vsx_c = (__vector float *)c;
+
+  for (i = 0; i < n; i++)
+    vsx_a[i] = __builtin_vsx_xvaddsp (vsx_b[i], vsx_c[i]);
+}
+
+#pragma GCC pop_options
+#pragma GCC target("no-vsx,no-altivec")
+
+#ifdef __ALTIVEC__
+#error "__ALTIVEC__ should not be defined."
+#endif
+
+#ifdef __VSX__
+#error "__VSX__ should not be defined."
+#endif
+
+void norm_add (float *a, float *b, float *c)
+{
+  unsigned long i;
+
+  for (i = 0; i < SIZE; i++)
+    a[i] = b[i] + c[i];
+}
Index: gcc/common/config/rs6000/rs6000-common.c
===================================================================
--- gcc/common/config/rs6000/rs6000-common.c	(.../trunk)	(revision 181085)
+++ gcc/common/config/rs6000/rs6000-common.c	(.../branches/ibm/builtin2)	(revision 181121)
@@ -202,6 +202,8 @@  rs6000_handle_option (struct gcc_options
 	    mask = MASK_DEBUG_COST;
 	  else if (! strcmp (q, "target"))
 	    mask = MASK_DEBUG_TARGET;
+	  else if (! strcmp (q, "builtin"))
+	    mask = MASK_DEBUG_BUILTIN;
 	  else
 	    error_at (loc, "unknown -mdebug-%s switch", q);
 
Index: gcc/config/rs6000/rs6000.opt
===================================================================
--- gcc/config/rs6000/rs6000.opt	(.../trunk)	(revision 181085)
+++ gcc/config/rs6000/rs6000.opt	(.../branches/ibm/builtin2)	(revision 181121)
@@ -79,6 +79,10 @@  enum rs6000_cmodel rs6000_current_cmodel
 TargetVariable
 unsigned int rs6000_recip_control
 
+;; Mask of what builtin functions are allowed
+TargetVariable
+unsigned int rs6000_builtin_mask
+
 ;; Debug flags
 TargetVariable
 unsigned int rs6000_debug
Index: gcc/config/rs6000/rs6000-c.c
===================================================================
--- gcc/config/rs6000/rs6000-c.c	(.../trunk)	(revision 181085)
+++ gcc/config/rs6000/rs6000-c.c	(.../branches/ibm/builtin2)	(revision 181121)
@@ -159,6 +159,11 @@  rs6000_macro_to_expand (cpp_reader *pfil
   cpp_hashnode *expand_this = tok->val.node.node;
   cpp_hashnode *ident;
 
+  /* If the current machine does not have altivec, don't look for the
+     keywords.  */
+  if (!TARGET_ALTIVEC)
+    return NULL;
+
   ident = altivec_categorize_keyword (tok);
 
   if (ident != expand_this)
@@ -260,40 +265,107 @@  rs6000_macro_to_expand (cpp_reader *pfil
   return expand_this;
 }
 
+
+/* Define or undefine a single macro.  */
+
+static void
+rs6000_define_or_undefine_macro (bool define_p, const char *name)
+{
+  if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
+    fprintf (stderr, "#%s %s\n", (define_p) ? "define" : "undef", name);
+
+  if (define_p)
+    cpp_define (parse_in, name);
+  else
+    cpp_undef (parse_in, name);
+}
+
+/* Define or undefine macros based on the current target.  If the user does
+   #pragma GCC target, we need to adjust the macros dynamically.  Note, some of
+   the options needed for builtins have been moved to separate variables, so
+   have both the target flags and the builtin flags as arguments.  */
+
+void
+rs6000_target_modify_macros (bool define_p, int flags, unsigned bu_mask)
+{
+  if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
+    fprintf (stderr, "rs6000_target_modify_macros (%s, 0x%x, 0x%x)\n",
+	     (define_p) ? "define" : "undef",
+	     (unsigned) flags, bu_mask);
+
+  /* target_flags based options.  */
+  if ((flags & MASK_POWER2) != 0)
+    rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR2");
+  else if ((flags & MASK_POWER) != 0)
+    rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR");
+  if ((flags & MASK_POWERPC) != 0)
+    rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC");
+  if ((flags & MASK_PPC_GPOPT) != 0)
+    rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCSQ");
+  if ((flags & MASK_PPC_GFXOPT) != 0)
+    rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCGR");
+  if ((flags & MASK_POWERPC64) != 0)
+    rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC64");
+  if ((flags & MASK_MFCRF) != 0)
+    rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR4");
+  if ((flags & MASK_POPCNTB) != 0)
+    rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5");
+  if ((flags & MASK_FPRND) != 0)
+    rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5X");
+  if ((flags & MASK_CMPB) != 0)
+    rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6");
+  if ((flags & MASK_MFPGPR) != 0)
+    rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6X");
+  if ((flags & MASK_POPCNTD) != 0)
+    rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7");
+  if ((flags & MASK_SOFT_FLOAT) != 0)
+    rs6000_define_or_undefine_macro (define_p, "_SOFT_FLOAT");
+  if ((flags & MASK_RECIP_PRECISION) != 0)
+    rs6000_define_or_undefine_macro (define_p, "__RECIP_PRECISION__");
+  if ((flags & MASK_ALTIVEC) != 0)
+    {
+      const char *vec_str = (define_p) ? "__VEC__=10206" : "__VEC__";
+      rs6000_define_or_undefine_macro (define_p, "__ALTIVEC__");
+      rs6000_define_or_undefine_macro (define_p, vec_str);
+
+	  /* Define this when supporting context-sensitive keywords.  */
+      if (!flag_iso)
+	rs6000_define_or_undefine_macro (define_p, "__APPLE_ALTIVEC__");
+    }
+  if ((flags & MASK_VSX) != 0)
+    rs6000_define_or_undefine_macro (define_p, "__VSX__");
+
+  /* options from the builtin masks.  */
+  if ((bu_mask & RS6000_BTM_SPE) != 0)
+    rs6000_define_or_undefine_macro (define_p, "__SPE__");
+  if ((bu_mask & RS6000_BTM_PAIRED) != 0)
+    rs6000_define_or_undefine_macro (define_p, "__PAIRED__");
+  if ((bu_mask & RS6000_BTM_CELL) != 0)
+    rs6000_define_or_undefine_macro (define_p, "__PPU__");
+}
+
 void
 rs6000_cpu_cpp_builtins (cpp_reader *pfile)
 {
-  if (TARGET_POWER2)
-    builtin_define ("_ARCH_PWR2");
-  else if (TARGET_POWER)
-    builtin_define ("_ARCH_PWR");
-  if (TARGET_POWERPC)
-    builtin_define ("_ARCH_PPC");
-  if (TARGET_PPC_GPOPT)
-    builtin_define ("_ARCH_PPCSQ");
-  if (TARGET_PPC_GFXOPT)
-    builtin_define ("_ARCH_PPCGR");
-  if (TARGET_POWERPC64)
-    builtin_define ("_ARCH_PPC64");
-  if (TARGET_MFCRF)
-    builtin_define ("_ARCH_PWR4");
-  if (TARGET_POPCNTB)
-    builtin_define ("_ARCH_PWR5");
-  if (TARGET_FPRND)
-    builtin_define ("_ARCH_PWR5X");
-  if (TARGET_CMPB)
-    builtin_define ("_ARCH_PWR6");
-  if (TARGET_MFPGPR)
-    builtin_define ("_ARCH_PWR6X");
+  /* Define all of the common macros.  */
+  rs6000_target_modify_macros (true, target_flags,
+			       rs6000_builtin_mask_calculate ());
+
+  /* _ARCH_COM does not fit in the framework of target_modify_macros, so handle
+     it specially.  */
   if (! TARGET_POWER && ! TARGET_POWER2 && ! TARGET_POWERPC)
     builtin_define ("_ARCH_COM");
-  if (TARGET_POPCNTD)
-    builtin_define ("_ARCH_PWR7");
-  if (TARGET_ALTIVEC)
-    {
-      builtin_define ("__ALTIVEC__");
-      builtin_define ("__VEC__=10206");
+  if (TARGET_FRE)
+    builtin_define ("__RECIP__");
+  if (TARGET_FRES)
+    builtin_define ("__RECIPF__");
+  if (TARGET_FRSQRTE)
+    builtin_define ("__RSQRTE__");
+  if (TARGET_FRSQRTES)
+    builtin_define ("__RSQRTEF__");
 
+  if (TARGET_EXTRA_BUILTINS)
+    {
       /* Define the AltiVec syntactic elements.  */
       builtin_define ("__vector=__attribute__((altivec(vector__)))");
       builtin_define ("__pixel=__attribute__((altivec(pixel__))) unsigned short");
@@ -301,9 +373,6 @@  rs6000_cpu_cpp_builtins (cpp_reader *pfi
 
       if (!flag_iso)
 	{
-	  /* Define this when supporting context-sensitive keywords.  */
-	  builtin_define ("__APPLE_ALTIVEC__");
-	  
 	  builtin_define ("vector=vector");
 	  builtin_define ("pixel=pixel");
 	  builtin_define ("bool=bool");
@@ -314,14 +383,6 @@  rs6000_cpu_cpp_builtins (cpp_reader *pfi
 	  cpp_get_callbacks (pfile)->macro_to_expand = rs6000_macro_to_expand;
 	}
     }
-  if (rs6000_cpu == PROCESSOR_CELL)
-    builtin_define ("__PPU__");
-  if (TARGET_SPE)
-    builtin_define ("__SPE__");
-  if (TARGET_PAIRED_FLOAT)
-    builtin_define ("__PAIRED__");
-  if (TARGET_SOFT_FLOAT)
-    builtin_define ("_SOFT_FLOAT");
   if ((!(TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)))
       ||(TARGET_HARD_FLOAT && TARGET_FPRS && !TARGET_DOUBLE_FLOAT))
     builtin_define ("_SOFT_DOUBLE");
@@ -331,10 +392,9 @@  rs6000_cpu_cpp_builtins (cpp_reader *pfi
   /* Used by libstdc++.  */
   if (TARGET_NO_LWSYNC)
     builtin_define ("__NO_LWSYNC__");
-  if (TARGET_VSX)
-    {
-      builtin_define ("__VSX__");
 
+  if (TARGET_EXTRA_BUILTINS)
+    {
       /* For the VSX builtin functions identical to Altivec functions, just map
 	 the altivec builtin into the vsx version (the altivec functions
 	 generate VSX code if -mvsx).  */
@@ -365,16 +425,6 @@  rs6000_cpu_cpp_builtins (cpp_reader *pfi
       builtin_define ("__builtin_vsx_xvnmsubasp=__builtin_vsx_xvnmsubsp");
       builtin_define ("__builtin_vsx_xvnmsubmsp=__builtin_vsx_xvnmsubsp");
     }
-  if (RS6000_RECIP_HAVE_RE_P (DFmode))
-    builtin_define ("__RECIP__");
-  if (RS6000_RECIP_HAVE_RE_P (SFmode))
-    builtin_define ("__RECIPF__");
-  if (RS6000_RECIP_HAVE_RSQRTE_P (DFmode))
-    builtin_define ("__RSQRTE__");
-  if (RS6000_RECIP_HAVE_RSQRTE_P (SFmode))
-    builtin_define ("__RSQRTEF__");
-  if (TARGET_RECIP_PRECISION)
-    builtin_define ("__RECIP_PRECISION__");
 
   /* Tell users they can use __builtin_bswap{16,64}.  */
   builtin_define ("__HAVE_BSWAP__");
@@ -516,7 +566,7 @@  const struct altivec_builtin_types altiv
     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
   { ALTIVEC_BUILTIN_VEC_RSQRT, ALTIVEC_BUILTIN_VRSQRTFP,
     RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
-  { ALTIVEC_BUILTIN_VEC_RSQRT, VSX_BUILTIN_VEC_RSQRT_V2DF,
+  { ALTIVEC_BUILTIN_VEC_RSQRT, VSX_BUILTIN_RSQRT_2DF,
     RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
   { ALTIVEC_BUILTIN_VEC_RSQRTE, ALTIVEC_BUILTIN_VRSQRTEFP,
     RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
@@ -3198,140 +3248,140 @@  const struct altivec_builtin_types altiv
     ~RS6000_BTI_pixel_V8HI },
 
   /* Predicates.  */
-  { ALTIVEC_BUILTIN_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
+  { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI },
-  { ALTIVEC_BUILTIN_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
+  { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI },
-  { ALTIVEC_BUILTIN_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
+  { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
-  { ALTIVEC_BUILTIN_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSB_P,
+  { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSB_P,
     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI },
-  { ALTIVEC_BUILTIN_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSB_P,
+  { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSB_P,
     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI },
-  { ALTIVEC_BUILTIN_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSB_P,
+  { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSB_P,
     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI },
-  { ALTIVEC_BUILTIN_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUH_P,
+  { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUH_P,
     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI },
-  { ALTIVEC_BUILTIN_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUH_P,
+  { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUH_P,
     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI },
-  { ALTIVEC_BUILTIN_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUH_P,
+  { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUH_P,
     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
-  { ALTIVEC_BUILTIN_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSH_P,
+  { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSH_P,
     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
-  { ALTIVEC_BUILTIN_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSH_P,
+  { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSH_P,
     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI },
-  { ALTIVEC_BUILTIN_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSH_P,
+  { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSH_P,
     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI },
-  { ALTIVEC_BUILTIN_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUW_P,
+  { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUW_P,
     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI },
-  { ALTIVEC_BUILTIN_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUW_P,
+  { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUW_P,
     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI },
-  { ALTIVEC_BUILTIN_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUW_P,
+  { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUW_P,
     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
-  { ALTIVEC_BUILTIN_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSW_P,
+  { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSW_P,
     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI },
-  { ALTIVEC_BUILTIN_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSW_P,
+  { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSW_P,
     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI },
-  { ALTIVEC_BUILTIN_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSW_P,
+  { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSW_P,
     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI },
-  { ALTIVEC_BUILTIN_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTFP_P,
+  { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTFP_P,
     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
-  { ALTIVEC_BUILTIN_VCMPGT_P, VSX_BUILTIN_XVCMPGTDP_P,
+  { ALTIVEC_BUILTIN_VEC_VCMPGT_P, VSX_BUILTIN_XVCMPGTDP_P,
     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
 
 
-  { ALTIVEC_BUILTIN_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
+  { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI },
-  { ALTIVEC_BUILTIN_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
+  { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI },
-  { ALTIVEC_BUILTIN_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
+  { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
-  { ALTIVEC_BUILTIN_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
+  { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI },
-  { ALTIVEC_BUILTIN_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
+  { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI },
-  { ALTIVEC_BUILTIN_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
+  { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI },
-  { ALTIVEC_BUILTIN_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
+  { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI },
-  { ALTIVEC_BUILTIN_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
+  { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI },
-  { ALTIVEC_BUILTIN_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
+  { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI },
-  { ALTIVEC_BUILTIN_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
+  { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
-  { ALTIVEC_BUILTIN_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
+  { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
-  { ALTIVEC_BUILTIN_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
+  { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI },
-  { ALTIVEC_BUILTIN_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
+  { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI },
-  { ALTIVEC_BUILTIN_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
+  { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI },
-  { ALTIVEC_BUILTIN_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
+  { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI },
-  { ALTIVEC_BUILTIN_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
+  { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI },
-  { ALTIVEC_BUILTIN_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
+  { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI },
-  { ALTIVEC_BUILTIN_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
+  { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
-  { ALTIVEC_BUILTIN_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
+  { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI },
-  { ALTIVEC_BUILTIN_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
+  { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI },
-  { ALTIVEC_BUILTIN_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
+  { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI },
-  { ALTIVEC_BUILTIN_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
+  { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI },
-  { ALTIVEC_BUILTIN_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQFP_P,
+  { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQFP_P,
     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
-  { ALTIVEC_BUILTIN_VCMPEQ_P, VSX_BUILTIN_XVCMPEQDP_P,
+  { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, VSX_BUILTIN_XVCMPEQDP_P,
     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
 
 
   /* cmpge is the same as cmpgt for all cases except floating point.
      There is further code to deal with this special case in
      altivec_build_resolved_builtin.  */
-  { ALTIVEC_BUILTIN_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
+  { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI },
-  { ALTIVEC_BUILTIN_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
+  { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI },
-  { ALTIVEC_BUILTIN_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
+  { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
-  { ALTIVEC_BUILTIN_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSB_P,
+  { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSB_P,
     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI },
-  { ALTIVEC_BUILTIN_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSB_P,
+  { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSB_P,
     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI },
-  { ALTIVEC_BUILTIN_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSB_P,
+  { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSB_P,
     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI },
-  { ALTIVEC_BUILTIN_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUH_P,
+  { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUH_P,
     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI },
-  { ALTIVEC_BUILTIN_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUH_P,
+  { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUH_P,
     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI },
-  { ALTIVEC_BUILTIN_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUH_P,
+  { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUH_P,
     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
-  { ALTIVEC_BUILTIN_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSH_P,
+  { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSH_P,
     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
-  { ALTIVEC_BUILTIN_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSH_P,
+  { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSH_P,
     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI },
-  { ALTIVEC_BUILTIN_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSH_P,
+  { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSH_P,
     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI },
-  { ALTIVEC_BUILTIN_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUW_P,
+  { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUW_P,
     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI },
-  { ALTIVEC_BUILTIN_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUW_P,
+  { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUW_P,
     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI },
-  { ALTIVEC_BUILTIN_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUW_P,
+  { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUW_P,
     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
-  { ALTIVEC_BUILTIN_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSW_P,
+  { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSW_P,
     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI },
-  { ALTIVEC_BUILTIN_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSW_P,
+  { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSW_P,
     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI },
-  { ALTIVEC_BUILTIN_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSW_P,
+  { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSW_P,
     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI },
-  { ALTIVEC_BUILTIN_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGEFP_P,
+  { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGEFP_P,
     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
-  { ALTIVEC_BUILTIN_VCMPGE_P, VSX_BUILTIN_XVCMPGEDP_P,
+  { ALTIVEC_BUILTIN_VEC_VCMPGE_P, VSX_BUILTIN_XVCMPGEDP_P,
     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
 
   { (enum rs6000_builtins) 0, (enum rs6000_builtins) 0, 0, 0, 0, 0 }
@@ -3402,7 +3452,7 @@  altivec_build_resolved_builtin (tree *ar
      condition (LT vs. EQ, which is recognizable by bit 1 of the first
      argument) is reversed.  Patch the arguments here before building
      the resolved CALL_EXPR.  */
-  if (desc->code == ALTIVEC_BUILTIN_VCMPGE_P
+  if (desc->code == ALTIVEC_BUILTIN_VEC_VCMPGE_P
       && desc->overloaded_code != ALTIVEC_BUILTIN_VCMPGEFP_P)
     {
       tree t;
@@ -3448,18 +3498,20 @@  altivec_resolve_overloaded_builtin (loca
 {
   VEC(tree,gc) *arglist = (VEC(tree,gc) *) passed_arglist;
   unsigned int nargs = VEC_length (tree, arglist);
-  unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
+  enum rs6000_builtins fcode
+    = (enum rs6000_builtins)DECL_FUNCTION_CODE (fndecl);
   tree fnargs = TYPE_ARG_TYPES (TREE_TYPE (fndecl));
   tree types[3], args[3];
   const struct altivec_builtin_types *desc;
   unsigned int n;
 
-  if ((fcode < ALTIVEC_BUILTIN_OVERLOADED_FIRST
-       || fcode > ALTIVEC_BUILTIN_OVERLOADED_LAST)
-      && (fcode < VSX_BUILTIN_OVERLOADED_FIRST
-	  || fcode > VSX_BUILTIN_OVERLOADED_LAST))
+  if (!rs6000_overloaded_builtin_p (fcode))
     return NULL_TREE;
 
+  if (TARGET_DEBUG_BUILTIN)
+    fprintf (stderr, "altivec_resolve_overloaded_builtin, code = %4d, %s\n",
+	     (int)fcode, IDENTIFIER_POINTER (DECL_NAME (fndecl)));
+
   /* For now treat vec_splats and vec_promote as the same.  */
   if (fcode == ALTIVEC_BUILTIN_VEC_SPLATS
       || fcode == ALTIVEC_BUILTIN_VEC_PROMOTE)
Index: gcc/config/rs6000/rs6000-builtin.def
===================================================================
--- gcc/config/rs6000/rs6000-builtin.def	(.../trunk)	(revision 181085)
+++ gcc/config/rs6000/rs6000-builtin.def	(.../branches/ibm/builtin2)	(revision 181121)
@@ -24,997 +24,1415 @@ 
    see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
    <http://www.gnu.org/licenses/>.  */
 
-/* Before including this file, two macros must be defined:
-   RS6000_BUILTIN	 -- 2 arguments, the enum name, and classification
-   RS6000_BUILTIN_EQUATE -- 2 arguments, enum name and value */
-
-/* AltiVec builtins.  */
-RS6000_BUILTIN(ALTIVEC_BUILTIN_ST_INTERNAL_4si,		RS6000_BTC_MEM)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_LD_INTERNAL_4si,		RS6000_BTC_MEM)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_ST_INTERNAL_8hi,		RS6000_BTC_MEM)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_LD_INTERNAL_8hi,		RS6000_BTC_MEM)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_ST_INTERNAL_16qi,	RS6000_BTC_MEM)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_LD_INTERNAL_16qi,	RS6000_BTC_MEM)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_ST_INTERNAL_4sf,		RS6000_BTC_MEM)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_LD_INTERNAL_4sf,		RS6000_BTC_MEM)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_ST_INTERNAL_2df,		RS6000_BTC_MEM)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_LD_INTERNAL_2df,		RS6000_BTC_MEM)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_ST_INTERNAL_2di,		RS6000_BTC_MEM)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_LD_INTERNAL_2di,		RS6000_BTC_MEM)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VADDUBM,			RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VADDUHM,			RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VADDUWM,			RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VADDFP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VADDCUW,			RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VADDUBS,			RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VADDSBS,			RS6000_BTC_SAT)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VADDUHS,			RS6000_BTC_SAT)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VADDSHS,			RS6000_BTC_SAT)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VADDUWS,			RS6000_BTC_SAT)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VADDSWS,			RS6000_BTC_SAT)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VAND,			RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VANDC,			RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VAVGUB,			RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VAVGSB,			RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VAVGUH,			RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VAVGSH,			RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VAVGUW,			RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VAVGSW,			RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VCFUX,			RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VCFSX,			RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VCTSXS,			RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VCTUXS,			RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VCMPBFP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VCMPEQUB,		RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VCMPEQUH,		RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VCMPEQUW,		RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VCMPEQFP,		RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VCMPGEFP,		RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VCMPGTUB,		RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VCMPGTSB,		RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VCMPGTUH,		RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VCMPGTSH,		RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VCMPGTUW,		RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VCMPGTSW,		RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VCMPGTFP,		RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEXPTEFP,		RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VLOGEFP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VMADDFP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VMAXUB,			RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VMAXSB,			RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VMAXUH,			RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VMAXSH,			RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VMAXUW,			RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VMAXSW,			RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VMAXFP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VMHADDSHS,		RS6000_BTC_SAT)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VMHRADDSHS,		RS6000_BTC_SAT)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VMLADDUHM,		RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VMRGHB,			RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VMRGHH,			RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VMRGHW,			RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VMRGLB,			RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VMRGLH,			RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VMRGLW,			RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VMSUMUBM,		RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VMSUMMBM,		RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VMSUMUHM,		RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VMSUMSHM,		RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VMSUMUHS,		RS6000_BTC_SAT)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VMSUMSHS,		RS6000_BTC_SAT)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VMINUB,			RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VMINSB,			RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VMINUH,			RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VMINSH,			RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VMINUW,			RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VMINSW,			RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VMINFP,			RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VMULEUB,			RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VMULEUB_UNS,		RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VMULESB,			RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VMULEUH,			RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VMULEUH_UNS,		RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VMULESH,			RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VMULOUB,			RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VMULOUB_UNS,		RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VMULOSB,			RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VMULOUH,			RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VMULOUH_UNS,		RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VMULOSH,			RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VNMSUBFP,		RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VNOR,			RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VOR,			RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VSEL_2DF,		RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VSEL_2DI,		RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VSEL_4SI,		RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VSEL_4SF,		RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VSEL_8HI,		RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VSEL_16QI,		RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VSEL_2DI_UNS,		RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VSEL_4SI_UNS,		RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VSEL_8HI_UNS,		RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VSEL_16QI_UNS,		RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VPERM_2DF,		RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VPERM_2DI,		RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VPERM_4SI,		RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VPERM_4SF,		RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VPERM_8HI,		RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VPERM_16QI,		RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VPERM_2DI_UNS,		RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VPERM_4SI_UNS,		RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VPERM_8HI_UNS,		RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VPERM_16QI_UNS,		RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VPKUHUM,			RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VPKUWUM,			RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VPKPX,			RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VPKUHSS,			RS6000_BTC_SAT)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VPKSHSS,			RS6000_BTC_SAT)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VPKUWSS,			RS6000_BTC_SAT)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VPKSWSS,			RS6000_BTC_SAT)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VPKUHUS,			RS6000_BTC_SAT)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VPKSHUS,			RS6000_BTC_SAT)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VPKUWUS,			RS6000_BTC_SAT)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VPKSWUS,			RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VREFP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VRFIM,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VRFIN,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VRFIP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VRFIZ,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VRLB,			RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VRLH,			RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VRLW,			RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VRSQRTFP,		RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VRSQRTEFP,		RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VSLB,			RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VSLH,			RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VSLW,			RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VSL,			RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VSLO,			RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VSPLTB,			RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VSPLTH,			RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VSPLTW,			RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VSPLTISB,		RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VSPLTISH,		RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VSPLTISW,		RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VSRB,			RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VSRH,			RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VSRW,			RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VSRAB,			RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VSRAH,			RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VSRAW,			RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VSR,			RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VSRO,			RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VSUBUBM,			RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VSUBUHM,			RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VSUBUWM,			RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VSUBFP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VSUBCUW,			RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VSUBUBS,			RS6000_BTC_SAT)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VSUBSBS,			RS6000_BTC_SAT)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VSUBUHS,			RS6000_BTC_SAT)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VSUBSHS,			RS6000_BTC_SAT)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VSUBUWS,			RS6000_BTC_SAT)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VSUBSWS,			RS6000_BTC_SAT)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VSUM4UBS,		RS6000_BTC_SAT)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VSUM4SBS,		RS6000_BTC_SAT)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VSUM4SHS,		RS6000_BTC_SAT)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VSUM2SWS,		RS6000_BTC_SAT)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VSUMSWS,			RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VXOR,			RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VSLDOI_16QI,		RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VSLDOI_8HI,		RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VSLDOI_4SI,		RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VSLDOI_4SF,		RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VUPKHSB,			RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VUPKHPX,			RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VUPKHSH,			RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VUPKLSB,			RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VUPKLPX,			RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VUPKLSH,			RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_MTVSCR,			RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_MFVSCR,			RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_DSSALL,			RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_DSS,			RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_LVSL,			RS6000_BTC_MEM)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_LVSR,			RS6000_BTC_MEM)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_DSTT,			RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_DSTST,			RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_DSTSTT,			RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_DST,			RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_LVEBX,			RS6000_BTC_MEM)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_LVEHX,			RS6000_BTC_MEM)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_LVEWX,			RS6000_BTC_MEM)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_LVXL,			RS6000_BTC_MEM)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_LVX,			RS6000_BTC_MEM)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_STVX,			RS6000_BTC_MEM)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_LVLX,			RS6000_BTC_MEM)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_LVLXL,			RS6000_BTC_MEM)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_LVRX,			RS6000_BTC_MEM)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_LVRXL,			RS6000_BTC_MEM)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_STVEBX,			RS6000_BTC_MEM)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_STVEHX,			RS6000_BTC_MEM)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_STVEWX,			RS6000_BTC_MEM)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_STVXL,			RS6000_BTC_MEM)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_STVLX,			RS6000_BTC_MEM)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_STVLXL,			RS6000_BTC_MEM)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_STVRX,			RS6000_BTC_MEM)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_STVRXL,			RS6000_BTC_MEM)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VCMPBFP_P,		RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VCMPEQFP_P,		RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VCMPEQUB_P,		RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VCMPEQUH_P,		RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VCMPEQUW_P,		RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VCMPGEFP_P,		RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VCMPGTFP_P,		RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VCMPGTSB_P,		RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VCMPGTSH_P,		RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VCMPGTSW_P,		RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VCMPGTUB_P,		RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VCMPGTUH_P,		RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VCMPGTUW_P,		RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_ABSS_V4SI,		RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_ABSS_V8HI,		RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_ABSS_V16QI,		RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_ABS_V4SI,		RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_ABS_V4SF,		RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_ABS_V8HI,		RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_ABS_V16QI,		RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_MASK_FOR_LOAD,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_MASK_FOR_STORE,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_INIT_V4SI,		RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_INIT_V8HI,		RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_INIT_V16QI,		RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_INIT_V4SF,		RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_SET_V4SI,		RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_SET_V8HI,		RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_SET_V16QI,		RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_SET_V4SF,		RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_EXT_V4SI,		RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_EXT_V8HI,		RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_EXT_V16QI,		RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_EXT_V4SF,		RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_COPYSIGN_V4SF,		RS6000_BTC_CONST)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VRECIPFP,		RS6000_BTC_FP_PURE)
+/* Before including this file, some macros must be defined:
+   RS6000_BUILTIN_1 -- 1 arg builtins
+   RS6000_BUILTIN_2 -- 2 arg builtins
+   RS6000_BUILTIN_3 -- 3 arg builtins
+   RS6000_BUILTIN_A -- ABS builtins
+   RS6000_BUILTIN_D -- DST builtins
+   RS6000_BUILTIN_E -- SPE EVSEL builtins.
+   RS6000_BUILTIN_P -- Altivec and VSX predicate builtins
+   RS6000_BUILTIN_Q -- Paired floating point VSX predicate builtins
+   RS6000_BUILTIN_S -- SPE predicate builtins
+   RS6000_BUILTIN_X -- special builtins
+
+   Each of the above macros takes 4 arguments:
+	ENUM	Enumeration name
+	NAME	String literal for the name
+	MASK	Mask of bits that indicate which options enables the builtin
+	ATTR	builtin attribute information.
+	ICODE	Insn code of the function that implents the builtin.  */
+
+#ifndef RS6000_BUILTIN_1
+  #error "RS6000_BUILTIN_1 is not defined."
+#endif
+
+#ifndef RS6000_BUILTIN_2
+  #error "RS6000_BUILTIN_2 is not defined."
+#endif
+
+#ifndef RS6000_BUILTIN_3
+  #error "RS6000_BUILTIN_3 is not defined."
+#endif
+
+#ifndef RS6000_BUILTIN_A
+  #error "RS6000_BUILTIN_A is not defined."
+#endif
+
+#ifndef RS6000_BUILTIN_D
+  #error "RS6000_BUILTIN_D is not defined."
+#endif
+
+#ifndef RS6000_BUILTIN_E
+  #error "RS6000_BUILTIN_E is not defined."
+#endif
+
+#ifndef RS6000_BUILTIN_P
+  #error "RS6000_BUILTIN_P is not defined."
+#endif
+
+#ifndef RS6000_BUILTIN_Q
+  #error "RS6000_BUILTIN_Q is not defined."
+#endif
+
+#ifndef RS6000_BUILTIN_S
+  #error "RS6000_BUILTIN_S is not defined."
+#endif
+
+#ifndef RS6000_BUILTIN_X
+  #error "RS6000_BUILTIN_X is not defined."
+#endif
+
+#ifndef BU_AV_1
+/* Define convenience macros using token pasting to allow fitting everything in
+   one line.  */
+
+/* Altivec convenience macros.  */
+#define BU_ALTIVEC_1(ENUM, NAME, ATTR, ICODE)				\
+  RS6000_BUILTIN_1 (ALTIVEC_BUILTIN_ ## ENUM,		/* ENUM */	\
+		    "__builtin_altivec_" NAME,		/* NAME */	\
+		    RS6000_BTM_ALTIVEC,			/* MASK */	\
+		    (RS6000_BTC_ ## ATTR		/* ATTR */	\
+		     | RS6000_BTC_UNARY),				\
+		    CODE_FOR_ ## ICODE)			/* ICODE */
+
+#define BU_ALTIVEC_2(ENUM, NAME, ATTR, ICODE)				\
+  RS6000_BUILTIN_2 (ALTIVEC_BUILTIN_ ## ENUM,		/* ENUM */	\
+		    "__builtin_altivec_" NAME,		/* NAME */	\
+		    RS6000_BTM_ALTIVEC,			/* MASK */	\
+		    (RS6000_BTC_ ## ATTR		/* ATTR */	\
+		     | RS6000_BTC_BINARY),				\
+		    CODE_FOR_ ## ICODE)			/* ICODE */
+
+#define BU_ALTIVEC_3(ENUM, NAME, ATTR, ICODE)				\
+  RS6000_BUILTIN_3 (ALTIVEC_BUILTIN_ ## ENUM,		/* ENUM */	\
+		    "__builtin_altivec_" NAME,		/* NAME */	\
+		    RS6000_BTM_ALTIVEC,			/* MASK */	\
+		    (RS6000_BTC_ ## ATTR		/* ATTR */	\
+		     | RS6000_BTC_TERNARY),				\
+		    CODE_FOR_ ## ICODE)			/* ICODE */
+
+#define BU_ALTIVEC_A(ENUM, NAME, ATTR, ICODE)				\
+  RS6000_BUILTIN_A (ALTIVEC_BUILTIN_ ## ENUM,		/* ENUM */	\
+		    "__builtin_altivec_" NAME,		/* NAME */	\
+		    RS6000_BTM_ALTIVEC,			/* MASK */	\
+		    (RS6000_BTC_ ## ATTR		/* ATTR */	\
+		     | RS6000_BTC_ABS),					\
+		    CODE_FOR_ ## ICODE)			/* ICODE */
+
+#define BU_ALTIVEC_D(ENUM, NAME, ATTR, ICODE)				\
+  RS6000_BUILTIN_D (ALTIVEC_BUILTIN_ ## ENUM,		/* ENUM */	\
+		    "__builtin_altivec_" NAME,		/* NAME */	\
+		    RS6000_BTM_ALTIVEC,			/* MASK */	\
+		    (RS6000_BTC_ ## ATTR		/* ATTR */	\
+		     | RS6000_BTC_DST),					\
+		    CODE_FOR_ ## ICODE)			/* ICODE */
+
+#define BU_ALTIVEC_P(ENUM, NAME, ATTR, ICODE)				\
+  RS6000_BUILTIN_P (ALTIVEC_BUILTIN_ ## ENUM,		/* ENUM */	\
+		    "__builtin_altivec_" NAME,		/* NAME */	\
+		    RS6000_BTM_ALTIVEC,			/* MASK */	\
+		    (RS6000_BTC_ ## ATTR		/* ATTR */	\
+		     | RS6000_BTC_PREDICATE),				\
+		    CODE_FOR_ ## ICODE)			/* ICODE */
+
+#define BU_ALTIVEC_X(ENUM, NAME, ATTR)					\
+  RS6000_BUILTIN_X (ALTIVEC_BUILTIN_ ## ENUM,		/* ENUM */	\
+		    "__builtin_altivec_" NAME,		/* NAME */	\
+		    RS6000_BTM_ALTIVEC,			/* MASK */	\
+		    (RS6000_BTC_ ## ATTR		/* ATTR */	\
+		     | RS6000_BTC_SPECIAL),				\
+		    CODE_FOR_nothing)			/* ICODE */
+
+#define BU_ALTIVEC_C(ENUM, NAME, ATTR)					\
+  RS6000_BUILTIN_X (ALTIVEC_BUILTIN_ ## ENUM,		/* ENUM */	\
+		    "__builtin_altivec_" NAME,		/* NAME */	\
+		    (RS6000_BTM_ALTIVEC			/* MASK */	\
+		     | RS6000_BTM_CELL),				\
+		    (RS6000_BTC_ ## ATTR		/* ATTR */	\
+		     | RS6000_BTC_SPECIAL),				\
+		    CODE_FOR_nothing)			/* ICODE */
+
+/* Altivec overloaded builtin function macros.  */
+#define BU_ALTIVEC_OVERLOAD_1(ENUM, NAME)				\
+  RS6000_BUILTIN_1 (ALTIVEC_BUILTIN_VEC_ ## ENUM,	/* ENUM */	\
+		    "__builtin_vec_" NAME,		/* NAME */	\
+		    RS6000_BTM_ALTIVEC,			/* MASK */	\
+		    (RS6000_BTC_OVERLOADED		/* ATTR */	\
+		     | RS6000_BTC_UNARY),				\
+		    CODE_FOR_nothing)			/* ICODE */
+
+#define BU_ALTIVEC_OVERLOAD_2(ENUM, NAME)				\
+  RS6000_BUILTIN_2 (ALTIVEC_BUILTIN_VEC_ ## ENUM,	/* ENUM */	\
+		    "__builtin_vec_" NAME,		/* NAME */	\
+		    RS6000_BTM_ALTIVEC,			/* MASK */	\
+		    (RS6000_BTC_OVERLOADED		/* ATTR */	\
+		     | RS6000_BTC_BINARY),				\
+		    CODE_FOR_nothing)			/* ICODE */
+
+#define BU_ALTIVEC_OVERLOAD_3(ENUM, NAME)				\
+  RS6000_BUILTIN_3 (ALTIVEC_BUILTIN_VEC_ ## ENUM,	/* ENUM */	\
+		    "__builtin_vec_" NAME,		/* NAME */	\
+		    RS6000_BTM_ALTIVEC,			/* MASK */	\
+		    (RS6000_BTC_OVERLOADED		/* ATTR */	\
+		     | RS6000_BTC_TERNARY),				\
+		    CODE_FOR_nothing)			/* ICODE */
+
+#define BU_ALTIVEC_OVERLOAD_A(ENUM, NAME)				\
+  RS6000_BUILTIN_A (ALTIVEC_BUILTIN_VEC_ ## ENUM,	/* ENUM */	\
+		    "__builtin_vec_" NAME,		/* NAME */	\
+		    RS6000_BTM_ALTIVEC,			/* MASK */	\
+		    (RS6000_BTC_OVERLOADED		/* ATTR */	\
+		     | RS6000_BTC_ABS),					\
+		    CODE_FOR_nothing)			/* ICODE */
+
+#define BU_ALTIVEC_OVERLOAD_D(ENUM, NAME)				\
+  RS6000_BUILTIN_D (ALTIVEC_BUILTIN_VEC_ ## ENUM,	/* ENUM */	\
+		    "__builtin_vec_" NAME,		/* NAME */	\
+		    RS6000_BTM_ALTIVEC,			/* MASK */	\
+		    (RS6000_BTC_OVERLOADED		/* ATTR */	\
+		     | RS6000_BTC_DST),					\
+		    CODE_FOR_nothing)			/* ICODE */
+
+#define BU_ALTIVEC_OVERLOAD_P(ENUM, NAME)				\
+  RS6000_BUILTIN_P (ALTIVEC_BUILTIN_VEC_ ## ENUM,	/* ENUM */	\
+		    "__builtin_vec_" NAME,		/* NAME */	\
+		    RS6000_BTM_ALTIVEC,			/* MASK */	\
+		    (RS6000_BTC_OVERLOADED		/* ATTR */	\
+		     | RS6000_BTC_PREDICATE),				\
+		    CODE_FOR_nothing)			/* ICODE */
+
+#define BU_ALTIVEC_OVERLOAD_X(ENUM, NAME)				\
+  RS6000_BUILTIN_X (ALTIVEC_BUILTIN_VEC_ ## ENUM,	/* ENUM */	\
+		    "__builtin_vec_" NAME,		/* NAME */	\
+		    RS6000_BTM_ALTIVEC,			/* MASK */	\
+		    (RS6000_BTC_OVERLOADED		/* ATTR */	\
+		     | RS6000_BTC_SPECIAL),				\
+		    CODE_FOR_nothing)			/* ICODE */
+
+/* VSX convenience macros.  */
+#define BU_VSX_1(ENUM, NAME, ATTR, ICODE)				\
+  RS6000_BUILTIN_1 (VSX_BUILTIN_ ## ENUM,		/* ENUM */	\
+		    "__builtin_vsx_" NAME,		/* NAME */	\
+		    RS6000_BTM_VSX,			/* MASK */	\
+		    (RS6000_BTC_ ## ATTR		/* ATTR */	\
+		     | RS6000_BTC_UNARY),				\
+		    CODE_FOR_ ## ICODE)			/* ICODE */
+
+#define BU_VSX_2(ENUM, NAME, ATTR, ICODE)				\
+  RS6000_BUILTIN_2 (VSX_BUILTIN_ ## ENUM,		/* ENUM */	\
+		    "__builtin_vsx_" NAME,		/* NAME */	\
+		    RS6000_BTM_VSX,			/* MASK */	\
+		    (RS6000_BTC_ ## ATTR		/* ATTR */	\
+		     | RS6000_BTC_BINARY),				\
+		    CODE_FOR_ ## ICODE)			/* ICODE */
+
+#define BU_VSX_3(ENUM, NAME, ATTR, ICODE)				\
+  RS6000_BUILTIN_3 (VSX_BUILTIN_ ## ENUM,		/* ENUM */	\
+		    "__builtin_vsx_" NAME,		/* NAME */	\
+		    RS6000_BTM_VSX,			/* MASK */	\
+		    (RS6000_BTC_ ## ATTR		/* ATTR */	\
+		     | RS6000_BTC_TERNARY),				\
+		    CODE_FOR_ ## ICODE)			/* ICODE */
+
+#define BU_VSX_A(ENUM, NAME, ATTR, ICODE)				\
+  RS6000_BUILTIN_A (VSX_BUILTIN_ ## ENUM,		/* ENUM */	\
+		    "__builtin_vsx_" NAME,		/* NAME */	\
+		    RS6000_BTM_VSX,			/* MASK */	\
+		    (RS6000_BTC_ ## ATTR		/* ATTR */	\
+		     | RS6000_BTC_ABS),					\
+		    CODE_FOR_ ## ICODE)			/* ICODE */
+
+#define BU_VSX_P(ENUM, NAME, ATTR, ICODE)				\
+  RS6000_BUILTIN_P (VSX_BUILTIN_ ## ENUM,		/* ENUM */	\
+		    "__builtin_vsx_" NAME,		/* NAME */	\
+		    RS6000_BTM_VSX,			/* MASK */	\
+		    (RS6000_BTC_ ## ATTR		/* ATTR */	\
+		     | RS6000_BTC_PREDICATE),				\
+		    CODE_FOR_ ## ICODE)			/* ICODE */
+
+#define BU_VSX_X(ENUM, NAME, ATTR)					\
+  RS6000_BUILTIN_X (VSX_BUILTIN_ ## ENUM,		/* ENUM */	\
+		    "__builtin_vsx_" NAME,		/* NAME */	\
+		    RS6000_BTM_VSX,			/* MASK */	\
+		    (RS6000_BTC_ ## ATTR		/* ATTR */	\
+		     | RS6000_BTC_SPECIAL),				\
+		    CODE_FOR_nothing)			/* ICODE */
+
+/* VSX overloaded builtin function macros.  */
+#define BU_VSX_OVERLOAD_1(ENUM, NAME)					\
+  RS6000_BUILTIN_1 (VSX_BUILTIN_VEC_ ## ENUM,		/* ENUM */	\
+		    "__builtin_vec_" NAME,		/* NAME */	\
+		    RS6000_BTM_VSX,			/* MASK */	\
+		    (RS6000_BTC_OVERLOADED		/* ATTR */	\
+		     | RS6000_BTC_UNARY),				\
+		    CODE_FOR_nothing)			/* ICODE */
+
+#define BU_VSX_OVERLOAD_2(ENUM, NAME)					\
+  RS6000_BUILTIN_2 (VSX_BUILTIN_VEC_ ## ENUM,		/* ENUM */	\
+		    "__builtin_vec_" NAME,		/* NAME */	\
+		    RS6000_BTM_VSX,			/* MASK */	\
+		    (RS6000_BTC_OVERLOADED		/* ATTR */	\
+		     | RS6000_BTC_BINARY),				\
+		    CODE_FOR_nothing)			/* ICODE */
+
+#define BU_VSX_OVERLOAD_3(ENUM, NAME)					\
+  RS6000_BUILTIN_3 (VSX_BUILTIN_VEC_ ## ENUM,		/* ENUM */	\
+		    "__builtin_vec_" NAME,		/* NAME */	\
+		    RS6000_BTM_VSX,			/* MASK */	\
+		    (RS6000_BTC_OVERLOADED		/* ATTR */	\
+		     | RS6000_BTC_TERNARY),				\
+		    CODE_FOR_nothing)			/* ICODE */
+
+/* xxpermdi and xxsldwi are overloaded functions, but had __builtin_vsx names
+   instead of __builtin_vec.  */
+#define BU_VSX_OVERLOAD_3V(ENUM, NAME)					\
+  RS6000_BUILTIN_3 (VSX_BUILTIN_VEC_ ## ENUM,		/* ENUM */	\
+		    "__builtin_vsx_" NAME,		/* NAME */	\
+		    RS6000_BTM_VSX,			/* MASK */	\
+		    (RS6000_BTC_OVERLOADED		/* ATTR */	\
+		     | RS6000_BTC_TERNARY),				\
+		    CODE_FOR_nothing)			/* ICODE */
+
+#define BU_VSX_OVERLOAD_X(ENUM, NAME)					\
+  RS6000_BUILTIN_X (VSX_BUILTIN_VEC_ ## ENUM,		/* ENUM */	\
+		    "__builtin_vec_" NAME,		/* NAME */	\
+		    RS6000_BTM_VSX,			/* MASK */	\
+		    (RS6000_BTC_OVERLOADED		/* ATTR */	\
+		     | RS6000_BTC_SPECIAL),				\
+		    CODE_FOR_nothing)			/* ICODE */
+
+/* SPE convenience macros.  */
+#define BU_SPE_1(ENUM, NAME, ATTR, ICODE)				\
+  RS6000_BUILTIN_1 (SPE_BUILTIN_ ## ENUM,		/* ENUM */	\
+		    "__builtin_spe_" NAME,		/* NAME */	\
+		    RS6000_BTM_SPE,			/* MASK */	\
+		    (RS6000_BTC_ ## ATTR		/* ATTR */	\
+		     | RS6000_BTC_UNARY),				\
+		    CODE_FOR_ ## ICODE)			/* ICODE */
+
+#define BU_SPE_2(ENUM, NAME, ATTR, ICODE)				\
+  RS6000_BUILTIN_2 (SPE_BUILTIN_ ## ENUM,		/* ENUM */	\
+		    "__builtin_spe_" NAME,		/* NAME */	\
+		    RS6000_BTM_SPE,			/* MASK */	\
+		    (RS6000_BTC_ ## ATTR		/* ATTR */	\
+		     | RS6000_BTC_BINARY),				\
+		    CODE_FOR_ ## ICODE)			/* ICODE */
+
+#define BU_SPE_3(ENUM, NAME, ATTR, ICODE)				\
+  RS6000_BUILTIN_3 (SPE_BUILTIN_ ## ENUM,		/* ENUM */	\
+		    "__builtin_spe_" NAME,		/* NAME */	\
+		    RS6000_BTM_SPE,			/* MASK */	\
+		    (RS6000_BTC_ ## ATTR		/* ATTR */	\
+		     | RS6000_BTC_TERNARY),				\
+		    CODE_FOR_ ## ICODE)			/* ICODE */
+
+#define BU_SPE_E(ENUM, NAME, ATTR, ICODE)				\
+  RS6000_BUILTIN_E (SPE_BUILTIN_ ## ENUM,		/* ENUM */	\
+		    "__builtin_spe_" NAME,		/* NAME */	\
+		    RS6000_BTM_SPE,			/* MASK */	\
+		    (RS6000_BTC_ ## ATTR		/* ATTR */	\
+		     | RS6000_BTC_EVSEL),				\
+		    CODE_FOR_ ## ICODE)			/* ICODE */
+
+#define BU_SPE_P(ENUM, NAME, ATTR, ICODE)				\
+  RS6000_BUILTIN_S (SPE_BUILTIN_ ## ENUM,		/* ENUM */	\
+		    "__builtin_spe_" NAME,		/* NAME */	\
+		    RS6000_BTM_SPE,			/* MASK */	\
+		    (RS6000_BTC_ ## ATTR		/* ATTR */	\
+		     | RS6000_BTC_PREDICATE),				\
+		    CODE_FOR_ ## ICODE)			/* ICODE */
+
+#define BU_SPE_X(ENUM, NAME, ATTR)					\
+  RS6000_BUILTIN_X (SPE_BUILTIN_ ## ENUM,		/* ENUM */	\
+		    "__builtin_spe_" NAME,		/* NAME */	\
+		    RS6000_BTM_SPE,			/* MASK */	\
+		    (RS6000_BTC_ ## ATTR		/* ATTR */	\
+		     | RS6000_BTC_SPECIAL),				\
+		    CODE_FOR_nothing)			/* ICODE */
+
+/* Paired floating point convenience macros.  */
+#define BU_PAIRED_1(ENUM, NAME, ATTR, ICODE)				\
+  RS6000_BUILTIN_1 (PAIRED_BUILTIN_ ## ENUM,		/* ENUM */	\
+		    "__builtin_paired_" NAME,		/* NAME */	\
+		    RS6000_BTM_PAIRED,			/* MASK */	\
+		    (RS6000_BTC_ ## ATTR		/* ATTR */	\
+		     | RS6000_BTC_UNARY),				\
+		    CODE_FOR_ ## ICODE)			/* ICODE */
+
+#define BU_PAIRED_2(ENUM, NAME, ATTR, ICODE)				\
+  RS6000_BUILTIN_2 (PAIRED_BUILTIN_ ## ENUM,		/* ENUM */	\
+		    "__builtin_paired_" NAME,		/* NAME */	\
+		    RS6000_BTM_PAIRED,			/* MASK */	\
+		    (RS6000_BTC_ ## ATTR		/* ATTR */	\
+		     | RS6000_BTC_BINARY),				\
+		    CODE_FOR_ ## ICODE)			/* ICODE */
+
+#define BU_PAIRED_3(ENUM, NAME, ATTR, ICODE)				\
+  RS6000_BUILTIN_3 (PAIRED_BUILTIN_ ## ENUM,		/* ENUM */	\
+		    "__builtin_paired_" NAME,		/* NAME */	\
+		    RS6000_BTM_PAIRED,			/* MASK */	\
+		    (RS6000_BTC_ ## ATTR		/* ATTR */	\
+		     | RS6000_BTC_TERNARY),				\
+		    CODE_FOR_ ## ICODE)			/* ICODE */
+
+#define BU_PAIRED_P(ENUM, NAME, ATTR, ICODE)				\
+  RS6000_BUILTIN_Q (PAIRED_BUILTIN_ ## ENUM,		/* ENUM */	\
+		    "__builtin_paired_" NAME,		/* NAME */	\
+		    RS6000_BTM_PAIRED,			/* MASK */	\
+		    (RS6000_BTC_ ## ATTR		/* ATTR */	\
+		     | RS6000_BTC_PREDICATE),				\
+		    CODE_FOR_ ## ICODE)			/* ICODE */
+
+#define BU_PAIRED_X(ENUM, NAME, ATTR)					\
+  RS6000_BUILTIN_X (PAIRED_BUILTIN_ ## ENUM,		/* ENUM */	\
+		    "__builtin_paired_" NAME,		/* NAME */	\
+		    RS6000_BTM_PAIRED,			/* MASK */	\
+		    (RS6000_BTC_ ## ATTR		/* ATTR */	\
+		     | RS6000_BTC_SPECIAL),				\
+		    CODE_FOR_nothing)			/* ICODE */
+
+#define BU_SPECIAL_X(ENUM, NAME, MASK, ATTR)				\
+  RS6000_BUILTIN_X (ENUM,				/* ENUM */	\
+		    NAME,				/* NAME */	\
+		    MASK,				/* MASK */	\
+		    (ATTR | RS6000_BTC_SPECIAL),	/* ATTR */	\
+		    CODE_FOR_nothing)			/* ICODE */
+#endif
+
+/* Insure 0 is not a legitimate index.  */
+BU_SPECIAL_X (RS6000_BUILTIN_NONE, NULL, 0, RS6000_BTC_MISC)
+
+/* 3 argument Altivec builtins.  */
+BU_ALTIVEC_3 (VMADDFP,        "vmaddfp",        FP,    	fmav4sf4)
+BU_ALTIVEC_3 (VMHADDSHS,      "vmhaddshs",      SAT,   	altivec_vmhaddshs)
+BU_ALTIVEC_3 (VMHRADDSHS,     "vmhraddshs",     SAT,   	altivec_vmhraddshs)
+BU_ALTIVEC_3 (VMLADDUHM,      "vmladduhm",      CONST, 	altivec_vmladduhm)
+BU_ALTIVEC_3 (VMSUMUBM,       "vmsumubm",       CONST, 	altivec_vmsumubm)
+BU_ALTIVEC_3 (VMSUMMBM,       "vmsummbm",       CONST, 	altivec_vmsummbm)
+BU_ALTIVEC_3 (VMSUMUHM,       "vmsumuhm",       CONST, 	altivec_vmsumuhm)
+BU_ALTIVEC_3 (VMSUMSHM,       "vmsumshm",       CONST, 	altivec_vmsumshm)
+BU_ALTIVEC_3 (VMSUMUHS,       "vmsumuhs",       SAT,   	altivec_vmsumuhs)
+BU_ALTIVEC_3 (VMSUMSHS,       "vmsumshs",       SAT,   	altivec_vmsumshs)
+BU_ALTIVEC_3 (VNMSUBFP,       "vnmsubfp",       FP,    	nfmsv4sf4)
+BU_ALTIVEC_3 (VPERM_2DF,      "vperm_2df",      CONST, 	altivec_vperm_v2df)
+BU_ALTIVEC_3 (VPERM_2DI,      "vperm_2di",      CONST, 	altivec_vperm_v2di)
+BU_ALTIVEC_3 (VPERM_4SF,      "vperm_4sf",      CONST, 	altivec_vperm_v4sf)
+BU_ALTIVEC_3 (VPERM_4SI,      "vperm_4si",      CONST, 	altivec_vperm_v4si)
+BU_ALTIVEC_3 (VPERM_8HI,      "vperm_8hi",      CONST, 	altivec_vperm_v8hi)
+BU_ALTIVEC_3 (VPERM_16QI,     "vperm_16qi",     CONST, 	altivec_vperm_v16qi_uns)
+BU_ALTIVEC_3 (VPERM_2DI_UNS,  "vperm_2di_uns",  CONST, 	altivec_vperm_v2di_uns)
+BU_ALTIVEC_3 (VPERM_4SI_UNS,  "vperm_4si_uns",  CONST, 	altivec_vperm_v4si_uns)
+BU_ALTIVEC_3 (VPERM_8HI_UNS,  "vperm_8hi_uns",  CONST, 	altivec_vperm_v8hi_uns)
+BU_ALTIVEC_3 (VPERM_16QI_UNS, "vperm_16qi_uns", CONST, 	altivec_vperm_v16qi_uns)
+BU_ALTIVEC_3 (VSEL_4SF,       "vsel_4sf",       CONST, 	vector_select_v4sf)
+BU_ALTIVEC_3 (VSEL_4SI,       "vsel_4si",       CONST, 	vector_select_v4si)
+BU_ALTIVEC_3 (VSEL_8HI,       "vsel_8hi",       CONST, 	vector_select_v8hi)
+BU_ALTIVEC_3 (VSEL_16QI,      "vsel_16qi",      CONST, 	vector_select_v16qi)
+BU_ALTIVEC_3 (VSEL_2DF,       "vsel_2df",       CONST, 	vector_select_v2df)
+BU_ALTIVEC_3 (VSEL_2DI,       "vsel_2di",       CONST, 	vector_select_v2di)
+BU_ALTIVEC_3 (VSEL_4SI_UNS,   "vsel_4si_uns",   CONST, 	vector_select_v4si_uns)
+BU_ALTIVEC_3 (VSEL_8HI_UNS,   "vsel_8hi_uns",   CONST, 	vector_select_v8hi_uns)
+BU_ALTIVEC_3 (VSEL_16QI_UNS,  "vsel_16qi_uns",  CONST, 	vector_select_v16qi_uns)
+BU_ALTIVEC_3 (VSEL_2DI_UNS,   "vsel_2di_uns",   CONST, 	vector_select_v2di_uns)
+BU_ALTIVEC_3 (VSLDOI_16QI,    "vsldoi_16qi",    CONST, 	altivec_vsldoi_v16qi)
+BU_ALTIVEC_3 (VSLDOI_8HI,     "vsldoi_8hi",     CONST, 	altivec_vsldoi_v8hi)
+BU_ALTIVEC_3 (VSLDOI_4SI,     "vsldoi_4si",     CONST, 	altivec_vsldoi_v4si)
+BU_ALTIVEC_3 (VSLDOI_4SF,     "vsldoi_4sf",     CONST, 	altivec_vsldoi_v4sf)
+
+/* Altivec DST builtins.  */
+BU_ALTIVEC_D (DST,	      "dst",		MISC,  	altivec_dst)
+BU_ALTIVEC_D (DSTT,	      "dstt",		MISC,  	altivec_dstt)
+BU_ALTIVEC_D (DSTST,	      "dstst",		MISC,  	altivec_dstst)
+BU_ALTIVEC_D (DSTSTT,	      "dststt",		MISC,  	altivec_dststt)
+
+/* Altivec 2 argument builtin functions.  */
+BU_ALTIVEC_2 (VADDUBM,        "vaddubm",	CONST,	addv16qi3)
+BU_ALTIVEC_2 (VADDUHM,	      "vadduhm",	CONST,	addv8hi3)
+BU_ALTIVEC_2 (VADDUWM,	      "vadduwm",	CONST,	addv4si3)
+BU_ALTIVEC_2 (VADDFP,	      "vaddfp",		CONST,	addv4sf3)
+BU_ALTIVEC_2 (VADDCUW,	      "vaddcuw",	CONST,	altivec_vaddcuw)
+BU_ALTIVEC_2 (VADDUBS,	      "vaddubs",	CONST,	altivec_vaddubs)
+BU_ALTIVEC_2 (VADDSBS,	      "vaddsbs",	CONST,	altivec_vaddsbs)
+BU_ALTIVEC_2 (VADDUHS,	      "vadduhs",	CONST,	altivec_vadduhs)
+BU_ALTIVEC_2 (VADDSHS,	      "vaddshs",	CONST,	altivec_vaddshs)
+BU_ALTIVEC_2 (VADDUWS,	      "vadduws",	CONST,	altivec_vadduws)
+BU_ALTIVEC_2 (VADDSWS,	      "vaddsws",	CONST,	altivec_vaddsws)
+BU_ALTIVEC_2 (VAND,	      "vand",		CONST,	andv4si3)
+BU_ALTIVEC_2 (VANDC,	      "vandc",		CONST,	andcv4si3)
+BU_ALTIVEC_2 (VAVGUB,	      "vavgub",		CONST,	altivec_vavgub)
+BU_ALTIVEC_2 (VAVGSB,	      "vavgsb",		CONST,	altivec_vavgsb)
+BU_ALTIVEC_2 (VAVGUH,	      "vavguh",		CONST,	altivec_vavguh)
+BU_ALTIVEC_2 (VAVGSH,	      "vavgsh",		CONST,	altivec_vavgsh)
+BU_ALTIVEC_2 (VAVGUW,	      "vavguw",		CONST,	altivec_vavguw)
+BU_ALTIVEC_2 (VAVGSW,	      "vavgsw",		CONST,	altivec_vavgsw)
+BU_ALTIVEC_2 (VCFUX,	      "vcfux",		CONST,	altivec_vcfux)
+BU_ALTIVEC_2 (VCFSX,	      "vcfsx",		CONST,	altivec_vcfsx)
+BU_ALTIVEC_2 (VCMPBFP,	      "vcmpbfp",	CONST,	altivec_vcmpbfp)
+BU_ALTIVEC_2 (VCMPEQUB,	      "vcmpequb",	CONST,	vector_eqv16qi)
+BU_ALTIVEC_2 (VCMPEQUH,	      "vcmpequh",	CONST,	vector_eqv8hi)
+BU_ALTIVEC_2 (VCMPEQUW,	      "vcmpequw",	CONST,	vector_eqv4si)
+BU_ALTIVEC_2 (VCMPEQFP,	      "vcmpeqfp",	CONST,	vector_eqv4sf)
+BU_ALTIVEC_2 (VCMPGEFP,	      "vcmpgefp",	CONST,	vector_gev4sf)
+BU_ALTIVEC_2 (VCMPGTUB,	      "vcmpgtub",	CONST,	vector_gtuv16qi)
+BU_ALTIVEC_2 (VCMPGTSB,	      "vcmpgtsb",	CONST,	vector_gtv16qi)
+BU_ALTIVEC_2 (VCMPGTUH,	      "vcmpgtuh",	CONST,	vector_gtuv8hi)
+BU_ALTIVEC_2 (VCMPGTSH,	      "vcmpgtsh",	CONST,	vector_gtv8hi)
+BU_ALTIVEC_2 (VCMPGTUW,	      "vcmpgtuw",	CONST,	vector_gtuv4si)
+BU_ALTIVEC_2 (VCMPGTSW,	      "vcmpgtsw",	CONST,	vector_gtv4si)
+BU_ALTIVEC_2 (VCMPGTFP,	      "vcmpgtfp",	CONST,	vector_gtv4sf)
+BU_ALTIVEC_2 (VCTSXS,	      "vctsxs",		CONST,	altivec_vctsxs)
+BU_ALTIVEC_2 (VCTUXS,	      "vctuxs",		CONST,	altivec_vctuxs)
+BU_ALTIVEC_2 (VMAXUB,	      "vmaxub",		CONST,	umaxv16qi3)
+BU_ALTIVEC_2 (VMAXSB,	      "vmaxsb",		CONST,	smaxv16qi3)
+BU_ALTIVEC_2 (VMAXUH,	      "vmaxuh",		CONST,	umaxv8hi3)
+BU_ALTIVEC_2 (VMAXSH,	      "vmaxsh",		CONST,	smaxv8hi3)
+BU_ALTIVEC_2 (VMAXUW,	      "vmaxuw",		CONST,	umaxv4si3)
+BU_ALTIVEC_2 (VMAXSW,	      "vmaxsw",		CONST,	smaxv4si3)
+BU_ALTIVEC_2 (VMAXFP,	      "vmaxfp",		CONST,	smaxv4sf3)
+BU_ALTIVEC_2 (VMRGHB,	      "vmrghb",		CONST,	altivec_vmrghb)
+BU_ALTIVEC_2 (VMRGHH,	      "vmrghh",		CONST,	altivec_vmrghh)
+BU_ALTIVEC_2 (VMRGHW,	      "vmrghw",		CONST,	altivec_vmrghw)
+BU_ALTIVEC_2 (VMRGLB,	      "vmrglb",		CONST,	altivec_vmrglb)
+BU_ALTIVEC_2 (VMRGLH,	      "vmrglh",		CONST,	altivec_vmrglh)
+BU_ALTIVEC_2 (VMRGLW,	      "vmrglw",		CONST,	altivec_vmrglw)
+BU_ALTIVEC_2 (VMINUB,	      "vminub",		CONST,	uminv16qi3)
+BU_ALTIVEC_2 (VMINSB,	      "vminsb",		CONST,	sminv16qi3)
+BU_ALTIVEC_2 (VMINUH,	      "vminuh",		CONST,	uminv8hi3)
+BU_ALTIVEC_2 (VMINSH,	      "vminsh",		CONST,	sminv8hi3)
+BU_ALTIVEC_2 (VMINUW,	      "vminuw",		CONST,	uminv4si3)
+BU_ALTIVEC_2 (VMINSW,	      "vminsw",		CONST,	sminv4si3)
+BU_ALTIVEC_2 (VMINFP,	      "vminfp",		CONST,	sminv4sf3)
+BU_ALTIVEC_2 (VMULEUB,	      "vmuleub",	CONST,	altivec_vmuleub)
+BU_ALTIVEC_2 (VMULEUB_UNS,    "vmuleub_uns",	CONST,	altivec_vmuleub)
+BU_ALTIVEC_2 (VMULESB,	      "vmulesb",	CONST,	altivec_vmulesb)
+BU_ALTIVEC_2 (VMULEUH,	      "vmuleuh",	CONST,	altivec_vmuleuh)
+BU_ALTIVEC_2 (VMULEUH_UNS,    "vmuleuh_uns",	CONST,	altivec_vmuleuh)
+BU_ALTIVEC_2 (VMULESH,	      "vmulesh",	CONST,	altivec_vmulesh)
+BU_ALTIVEC_2 (VMULOUB,	      "vmuloub",	CONST,	altivec_vmuloub)
+BU_ALTIVEC_2 (VMULOUB_UNS,    "vmuloub_uns",	CONST,	altivec_vmuloub)
+BU_ALTIVEC_2 (VMULOSB,	      "vmulosb",	CONST,	altivec_vmulosb)
+BU_ALTIVEC_2 (VMULOUH,	      "vmulouh",	CONST,	altivec_vmulouh)
+BU_ALTIVEC_2 (VMULOUH_UNS,    "vmulouh_uns",	CONST,	altivec_vmulouh)
+BU_ALTIVEC_2 (VMULOSH,	      "vmulosh",	CONST,	altivec_vmulosh)
+BU_ALTIVEC_2 (VNOR,	      "vnor",		CONST,	norv4si3)
+BU_ALTIVEC_2 (VOR,	      "vor",		CONST,	iorv4si3)
+BU_ALTIVEC_2 (VPKUHUM,	      "vpkuhum",	CONST,	altivec_vpkuhum)
+BU_ALTIVEC_2 (VPKUWUM,	      "vpkuwum",	CONST,	altivec_vpkuwum)
+BU_ALTIVEC_2 (VPKPX,	      "vpkpx",		CONST,	altivec_vpkpx)
+BU_ALTIVEC_2 (VPKSHSS,	      "vpkshss",	CONST,	altivec_vpkshss)
+BU_ALTIVEC_2 (VPKSWSS,	      "vpkswss",	CONST,	altivec_vpkswss)
+BU_ALTIVEC_2 (VPKUHUS,	      "vpkuhus",	CONST,	altivec_vpkuhus)
+BU_ALTIVEC_2 (VPKSHUS,	      "vpkshus",	CONST,	altivec_vpkshus)
+BU_ALTIVEC_2 (VPKUWUS,	      "vpkuwus",	CONST,	altivec_vpkuwus)
+BU_ALTIVEC_2 (VPKSWUS,	      "vpkswus",	CONST,	altivec_vpkswus)
+BU_ALTIVEC_2 (VRECIPFP,	      "vrecipdivfp",	CONST,	recipv4sf3)
+BU_ALTIVEC_2 (VRLB,	      "vrlb",		CONST,	vrotlv16qi3)
+BU_ALTIVEC_2 (VRLH,	      "vrlh",		CONST,	vrotlv8hi3)
+BU_ALTIVEC_2 (VRLW,	      "vrlw",		CONST,	vrotlv4si3)
+BU_ALTIVEC_2 (VSLB,	      "vslb",		CONST,	vashlv16qi3)
+BU_ALTIVEC_2 (VSLH,	      "vslh",		CONST,	vashlv8hi3)
+BU_ALTIVEC_2 (VSLW,	      "vslw",		CONST,	vashlv4si3)
+BU_ALTIVEC_2 (VSL,	      "vsl",		CONST,	altivec_vsl)
+BU_ALTIVEC_2 (VSLO,	      "vslo",		CONST,	altivec_vslo)
+BU_ALTIVEC_2 (VSPLTB,	      "vspltb",		CONST,	altivec_vspltb)
+BU_ALTIVEC_2 (VSPLTH,	      "vsplth",		CONST,	altivec_vsplth)
+BU_ALTIVEC_2 (VSPLTW,	      "vspltw",		CONST,	altivec_vspltw)
+BU_ALTIVEC_2 (VSRB,	      "vsrb",		CONST,	vlshrv16qi3)
+BU_ALTIVEC_2 (VSRH,	      "vsrh",		CONST,	vlshrv8hi3)
+BU_ALTIVEC_2 (VSRW,	      "vsrw",		CONST,	vlshrv4si3)
+BU_ALTIVEC_2 (VSRAB,	      "vsrab",		CONST,	vashrv16qi3)
+BU_ALTIVEC_2 (VSRAH,	      "vsrah",		CONST,	vashrv8hi3)
+BU_ALTIVEC_2 (VSRAW,	      "vsraw",		CONST,	vashrv4si3)
+BU_ALTIVEC_2 (VSR,	      "vsr",		CONST,	altivec_vsr)
+BU_ALTIVEC_2 (VSRO,	      "vsro",		CONST,	altivec_vsro)
+BU_ALTIVEC_2 (VSUBUBM,	      "vsububm",	CONST,	subv16qi3)
+BU_ALTIVEC_2 (VSUBUHM,	      "vsubuhm",	CONST,	subv8hi3)
+BU_ALTIVEC_2 (VSUBUWM,	      "vsubuwm",	CONST,	subv4si3)
+BU_ALTIVEC_2 (VSUBFP,	      "vsubfp",		CONST,	subv4sf3)
+BU_ALTIVEC_2 (VSUBCUW,	      "vsubcuw",	CONST,	altivec_vsubcuw)
+BU_ALTIVEC_2 (VSUBUBS,	      "vsububs",	CONST,	altivec_vsububs)
+BU_ALTIVEC_2 (VSUBSBS,	      "vsubsbs",	CONST,	altivec_vsubsbs)
+BU_ALTIVEC_2 (VSUBUHS,	      "vsubuhs",	CONST,	altivec_vsubuhs)
+BU_ALTIVEC_2 (VSUBSHS,	      "vsubshs",	CONST,	altivec_vsubshs)
+BU_ALTIVEC_2 (VSUBUWS,	      "vsubuws",	CONST,	altivec_vsubuws)
+BU_ALTIVEC_2 (VSUBSWS,	      "vsubsws",	CONST,	altivec_vsubsws)
+BU_ALTIVEC_2 (VSUM4UBS,	      "vsum4ubs",	CONST,	altivec_vsum4ubs)
+BU_ALTIVEC_2 (VSUM4SBS,	      "vsum4sbs",	CONST,	altivec_vsum4sbs)
+BU_ALTIVEC_2 (VSUM4SHS,	      "vsum4shs",	CONST,	altivec_vsum4shs)
+BU_ALTIVEC_2 (VSUM2SWS,	      "vsum2sws",	CONST,	altivec_vsum2sws)
+BU_ALTIVEC_2 (VSUMSWS,	      "vsumsws",	CONST,	altivec_vsumsws)
+BU_ALTIVEC_2 (VXOR,	      "vxor",		CONST,	xorv4si3)
+BU_ALTIVEC_2 (COPYSIGN_V4SF,  "copysignfp",	CONST,	vector_copysignv4sf3)
+
+/* Altivec ABS functions.  */
+BU_ALTIVEC_A (ABS_V4SI,	      "abs_v4si",	CONST,	absv4si2)
+BU_ALTIVEC_A (ABS_V8HI,	      "abs_v8hi",	CONST,	absv8hi2)
+BU_ALTIVEC_A (ABS_V4SF,	      "abs_v4sf",	CONST,	absv4sf2)
+BU_ALTIVEC_A (ABS_V16QI,      "abs_v16qi",	CONST,	absv16qi2)
+BU_ALTIVEC_A (ABSS_V4SI,      "abss_v4si",	SAT,	altivec_abss_v4si)
+BU_ALTIVEC_A (ABSS_V8HI,      "abss_v8hi",	SAT,	altivec_abss_v8hi)
+BU_ALTIVEC_A (ABSS_V16QI,     "abss_v16qi",	SAT,	altivec_abss_v16qi)
+
+/* 1 argument Altivec builtin functions.  */
+BU_ALTIVEC_1 (VEXPTEFP,	      "vexptefp",	FP,	altivec_vexptefp)
+BU_ALTIVEC_1 (VLOGEFP,	      "vlogefp",	FP,	altivec_vlogefp)
+BU_ALTIVEC_1 (VREFP,	      "vrefp",		FP,	rev4sf2)
+BU_ALTIVEC_1 (VRFIM,	      "vrfim",		FP,	vector_floorv4sf2)
+BU_ALTIVEC_1 (VRFIN,	      "vrfin",		FP,	altivec_vrfin)
+BU_ALTIVEC_1 (VRFIP,	      "vrfip",		FP,	vector_ceilv4sf2)
+BU_ALTIVEC_1 (VRFIZ,	      "vrfiz",		FP,	vector_btruncv4sf2)
+BU_ALTIVEC_1 (VRSQRTFP,	      "vrsqrtfp",	FP,	rsqrtv4sf2)
+BU_ALTIVEC_1 (VRSQRTEFP,      "vrsqrtefp",	FP,	rsqrtev4sf2)
+BU_ALTIVEC_1 (VSPLTISB,	      "vspltisb",	CONST,	altivec_vspltisb)
+BU_ALTIVEC_1 (VSPLTISH,	      "vspltish",	CONST,	altivec_vspltish)
+BU_ALTIVEC_1 (VSPLTISW,	      "vspltisw",	CONST,	altivec_vspltisw)
+BU_ALTIVEC_1 (VUPKHSB,	      "vupkhsb",	CONST,	altivec_vupkhsb)
+BU_ALTIVEC_1 (VUPKHPX,	      "vupkhpx",	CONST,	altivec_vupkhpx)
+BU_ALTIVEC_1 (VUPKHSH,	      "vupkhsh",	CONST,	altivec_vupkhsh)
+BU_ALTIVEC_1 (VUPKLSB,	      "vupklsb",	CONST,	altivec_vupklsb)
+BU_ALTIVEC_1 (VUPKLPX,	      "vupklpx",	CONST,	altivec_vupklpx)
+BU_ALTIVEC_1 (VUPKLSH,	      "vupklsh",	CONST,	altivec_vupklsh)
+
+BU_ALTIVEC_1 (FLOAT_V4SI_V4SF,    "float_sisf",	    FP,	floatv4siv4sf2)
+BU_ALTIVEC_1 (UNSFLOAT_V4SI_V4SF, "uns_float_sisf", FP, unsigned_floatv4siv4sf2)
+BU_ALTIVEC_1 (FIX_V4SF_V4SI,      "fix_sfsi",       FP, fix_truncv4sfv4si2)
+BU_ALTIVEC_1 (FIXUNS_V4SF_V4SI,   "fixuns_sfsi",    FP, fixuns_truncv4sfv4si2)
+
+/* Altivec predicate functions.  */
+BU_ALTIVEC_P (VCMPBFP_P,      "vcmpbfp_p",	CONST,	altivec_vcmpbfp_p)
+BU_ALTIVEC_P (VCMPEQFP_P,     "vcmpeqfp_p",	CONST,	vector_eq_v4sf_p)
+BU_ALTIVEC_P (VCMPGEFP_P,     "vcmpgefp_p",	CONST,	vector_ge_v4sf_p)
+BU_ALTIVEC_P (VCMPGTFP_P,     "vcmpgtfp_p",	CONST,	vector_gt_v4sf_p)
+BU_ALTIVEC_P (VCMPEQUW_P,     "vcmpequw_p",	CONST,	vector_eq_v4si_p)
+BU_ALTIVEC_P (VCMPGTSW_P,     "vcmpgtsw_p",	CONST,	vector_gt_v4si_p)
+BU_ALTIVEC_P (VCMPGTUW_P,     "vcmpgtuw_p",	CONST,	vector_gtu_v4si_p)
+BU_ALTIVEC_P (VCMPEQUH_P,     "vcmpequh_p",	CONST,	vector_eq_v8hi_p)
+BU_ALTIVEC_P (VCMPGTSH_P,     "vcmpgtsh_p",	CONST,	vector_gt_v8hi_p)
+BU_ALTIVEC_P (VCMPGTUH_P,     "vcmpgtuh_p",	CONST,	vector_gtu_v8hi_p)
+BU_ALTIVEC_P (VCMPEQUB_P,     "vcmpequb_p",	CONST,	vector_eq_v16qi_p)
+BU_ALTIVEC_P (VCMPGTSB_P,     "vcmpgtsb_p",	CONST,	vector_gt_v16qi_p)
+BU_ALTIVEC_P (VCMPGTUB_P,     "vcmpgtub_p",	CONST,	vector_gtu_v16qi_p)
+
+/* AltiVec builtins that are handled as special cases.  */
+BU_ALTIVEC_X (ST_INTERNAL_4si,  "st_internal_4si",  MEM)
+BU_ALTIVEC_X (LD_INTERNAL_4si,  "ld_internal_4si",  MEM)
+BU_ALTIVEC_X (ST_INTERNAL_8hi,	"st_internal_8hi",  MEM)
+BU_ALTIVEC_X (LD_INTERNAL_8hi,	"ld_internal_8hi",  MEM)
+BU_ALTIVEC_X (ST_INTERNAL_16qi,	"st_internal_16qi", MEM)
+BU_ALTIVEC_X (LD_INTERNAL_16qi,	"ld_internal_16qi", MEM)
+BU_ALTIVEC_X (ST_INTERNAL_4sf,	"st_internal_16qi", MEM)
+BU_ALTIVEC_X (LD_INTERNAL_4sf,	"ld_internal_4sf",  MEM)
+BU_ALTIVEC_X (ST_INTERNAL_2df,	"st_internal_4sf",  MEM)
+BU_ALTIVEC_X (LD_INTERNAL_2df,	"ld_internal_2df",  MEM)
+BU_ALTIVEC_X (ST_INTERNAL_2di,	"st_internal_2di",  MEM)
+BU_ALTIVEC_X (LD_INTERNAL_2di,	"ld_internal_2di",  MEM)
+BU_ALTIVEC_X (MTVSCR,		"mtvscr",	    MISC)
+BU_ALTIVEC_X (MFVSCR,		"mfvscr",	    MISC)
+BU_ALTIVEC_X (DSSALL,		"dssall",	    MISC)
+BU_ALTIVEC_X (DSS,		"dss",		    MISC)
+BU_ALTIVEC_X (LVSL,		"lvsl",		    MEM)
+BU_ALTIVEC_X (LVSR,		"lvsr",		    MEM)
+BU_ALTIVEC_X (LVEBX,		"lvebx",	    MEM)
+BU_ALTIVEC_X (LVEHX,		"lvehx",	    MEM)
+BU_ALTIVEC_X (LVEWX,		"lvewx",	    MEM)
+BU_ALTIVEC_X (LVXL,		"lvxl",		    MEM)
+BU_ALTIVEC_X (LVX,		"lvx",		    MEM)
+BU_ALTIVEC_X (STVX,		"stvx",		    MEM)
+BU_ALTIVEC_C (LVLX,		"lvlx",		    MEM)
+BU_ALTIVEC_C (LVLXL,		"lvlxl",	    MEM)
+BU_ALTIVEC_C (LVRX,		"lvrx",		    MEM)
+BU_ALTIVEC_C (LVRXL,		"lvrxl",	    MEM)
+BU_ALTIVEC_X (STVEBX,		"stvebx",	    MEM)
+BU_ALTIVEC_X (STVEHX,		"stvehx",	    MEM)
+BU_ALTIVEC_X (STVEWX,		"stvewx",	    MEM)
+BU_ALTIVEC_X (STVXL,		"stvxl",	    MEM)
+BU_ALTIVEC_C (STVLX,		"stvlx",	    MEM)
+BU_ALTIVEC_C (STVLXL,		"stvlxl",	    MEM)
+BU_ALTIVEC_C (STVRX,		"stvrx",	    MEM)
+BU_ALTIVEC_C (STVRXL,		"stvrxl",	    MEM)
+BU_ALTIVEC_X (MASK_FOR_LOAD,	"mask_for_load",    MISC)
+BU_ALTIVEC_X (MASK_FOR_STORE,	"mask_for_store",   MISC)
+BU_ALTIVEC_X (VEC_INIT_V4SI,	"vec_init_v4si",    CONST)
+BU_ALTIVEC_X (VEC_INIT_V8HI,	"vec_init_v8hi",    CONST)
+BU_ALTIVEC_X (VEC_INIT_V16QI,	"vec_init_v16qi",   CONST)
+BU_ALTIVEC_X (VEC_INIT_V4SF,	"vec_init_v4sf",    CONST)
+BU_ALTIVEC_X (VEC_SET_V4SI,	"vec_set_v4si",     CONST)
+BU_ALTIVEC_X (VEC_SET_V8HI,	"vec_set_v8hi",     CONST)
+BU_ALTIVEC_X (VEC_SET_V16QI,	"vec_set_v16qi",    CONST)
+BU_ALTIVEC_X (VEC_SET_V4SF,	"vec_set_v4sf",     CONST)
+BU_ALTIVEC_X (VEC_EXT_V4SI,	"vec_ext_v4si",     CONST)
+BU_ALTIVEC_X (VEC_EXT_V8HI,	"vec_ext_v8hi",     CONST)
+BU_ALTIVEC_X (VEC_EXT_V16QI,	"vec_ext_v16qi",    CONST)
+BU_ALTIVEC_X (VEC_EXT_V4SF,	"vec_ext_v4sf",     CONST)
 
 /* Altivec overloaded builtins.  */
 /* For now, don't set the classification for overloaded functions.
    The function should be converted to the type specific instruction
    before we get to the point about classifying the builtin type.  */
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VCMPEQ_P,		RS6000_BTC_MISC)
-RS6000_BUILTIN_EQUATE(ALTIVEC_BUILTIN_OVERLOADED_FIRST,
-		      ALTIVEC_BUILTIN_VCMPEQ_P)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VCMPGT_P,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VCMPGE_P,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_ABS,			RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_ABSS,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_ADD,			RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_ADDC,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_ADDS,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_AND,			RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_ANDC,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_AVG,			RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_EXTRACT,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_CEIL,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_CMPB,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_CMPEQ,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_CMPEQUB,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_CMPEQUH,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_CMPEQUW,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_CMPGE,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_CMPGT,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_CMPLE,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_CMPLT,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_COPYSIGN,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_CTF,			RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_CTS,			RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_CTU,			RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_DST,			RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_DSTST,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_DSTSTT,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_DSTT,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_EXPTE,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_FLOOR,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LD,			RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LDE,			RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LDL,			RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LOGE,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LVEBX,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LVEHX,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LVEWX,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LVLX,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LVLXL,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LVRX,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LVRXL,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LVSL,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LVSR,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_MADD,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_MADDS,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_MAX,			RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_MERGEH,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_MERGEL,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_MIN,			RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_MLADD,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_MPERM,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_MRADDS,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_MRGHB,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_MRGHH,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_MRGHW,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_MRGLB,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_MRGLH,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_MRGLW,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_MSUM,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_MSUMS,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_MTVSCR,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_MULE,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_MULO,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_NEARBYINT,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_NMSUB,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_NOR,			RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_OR,			RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_PACK,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_PACKPX,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_PACKS,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_PACKSU,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_PERM,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_RE,			RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_RECIP,		RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_RL,			RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_RINT,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_ROUND,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_RSQRT,		RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_RSQRTE,		RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_SEL,			RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_SL,			RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_SLD,			RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_SLL,			RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_SLO,			RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_SPLAT,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_SPLAT_S16,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_SPLAT_S32,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_SPLAT_S8,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_SPLAT_U16,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_SPLAT_U32,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_SPLAT_U8,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_SPLTB,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_SPLTH,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_SPLTW,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_SQRT,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_SR,			RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_SRA,			RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_SRL,			RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_SRO,			RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_ST,			RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_STE,			RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_STL,			RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_STVEBX,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_STVEHX,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_STVEWX,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_STVLX,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_STVLXL,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_STVRX,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_STVRXL,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_SUB,			RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_SUBC,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_SUBS,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_SUM2S,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_SUM4S,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_SUMS,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_TRUNC,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_UNPACKH,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_UNPACKL,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VADDFP,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VADDSBS,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VADDSHS,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VADDSWS,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VADDUBM,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VADDUBS,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VADDUHM,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VADDUHS,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VADDUWM,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VADDUWS,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VAVGSB,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VAVGSH,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VAVGSW,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VAVGUB,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VAVGUH,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VAVGUW,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VCFSX,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VCFUX,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VCMPEQFP,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VCMPEQUB,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VCMPEQUH,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VCMPEQUW,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VCMPGTFP,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VCMPGTSB,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VCMPGTSH,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VCMPGTSW,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VCMPGTUB,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VCMPGTUH,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VCMPGTUW,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VMAXFP,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VMAXSB,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VMAXSH,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VMAXSW,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VMAXUB,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VMAXUH,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VMAXUW,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VMINFP,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VMINSB,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VMINSH,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VMINSW,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VMINUB,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VMINUH,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VMINUW,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VMRGHB,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VMRGHH,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VMRGHW,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VMRGLB,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VMRGLH,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VMRGLW,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VMSUMMBM,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VMSUMSHM,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VMSUMSHS,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VMSUMUBM,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VMSUMUHM,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VMSUMUHS,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VMULESB,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VMULESH,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VMULEUB,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VMULEUH,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VMULOSB,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VMULOSH,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VMULOUB,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VMULOUH,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VPKSHSS,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VPKSHUS,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VPKSWSS,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VPKSWUS,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VPKUHUM,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VPKUHUS,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VPKUWUM,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VPKUWUS,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VRLB,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VRLH,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VRLW,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VSLB,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VSLH,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VSLW,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VSPLTB,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VSPLTH,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VSPLTW,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VSRAB,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VSRAH,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VSRAW,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VSRB,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VSRH,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VSRW,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VSUBFP,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VSUBSBS,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VSUBSHS,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VSUBSWS,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VSUBUBM,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VSUBUBS,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VSUBUHM,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VSUBUHS,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VSUBUWM,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VSUBUWS,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VSUM4SBS,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VSUM4SHS,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VSUM4UBS,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VUPKHPX,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VUPKHSB,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VUPKHSH,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VUPKLPX,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VUPKLSB,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VUPKLSH,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_XOR,			RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_STEP,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_PROMOTE,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_INSERT,		RS6000_BTC_MISC)
-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_SPLATS,		RS6000_BTC_MISC)
-RS6000_BUILTIN_EQUATE(ALTIVEC_BUILTIN_OVERLOADED_LAST,
-		      ALTIVEC_BUILTIN_VEC_SPLATS)
-
-/* SPE builtins.  */
-RS6000_BUILTIN(SPE_BUILTIN_EVADDW,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVAND,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVANDC,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVDIVWS,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVDIVWU,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVEQV,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVFSADD,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVFSDIV,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVFSMUL,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVFSSUB,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVLDDX,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVLDHX,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVLDWX,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVLHHESPLATX,		RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVLHHOSSPLATX,		RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVLHHOUSPLATX,		RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVLWHEX,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVLWHOSX,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVLWHOUX,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVLWHSPLATX,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVLWWSPLATX,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMERGEHI,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMERGEHILO,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMERGELO,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMERGELOHI,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMHEGSMFAA,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMHEGSMFAN,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMHEGSMIAA,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMHEGSMIAN,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMHEGUMIAA,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMHEGUMIAN,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMHESMF,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMHESMFA,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMHESMFAAW,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMHESMFANW,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMHESMI,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMHESMIA,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMHESMIAAW,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMHESMIANW,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMHESSF,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMHESSFA,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMHESSFAAW,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMHESSFANW,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMHESSIAAW,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMHESSIANW,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMHEUMI,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMHEUMIA,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMHEUMIAAW,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMHEUMIANW,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMHEUSIAAW,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMHEUSIANW,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMHOGSMFAA,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMHOGSMFAN,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMHOGSMIAA,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMHOGSMIAN,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMHOGUMIAA,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMHOGUMIAN,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMHOSMF,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMHOSMFA,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMHOSMFAAW,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMHOSMFANW,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMHOSMI,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMHOSMIA,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMHOSMIAAW,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMHOSMIANW,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMHOSSF,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMHOSSFA,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMHOSSFAAW,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMHOSSFANW,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMHOSSIAAW,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMHOSSIANW,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMHOUMI,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMHOUMIA,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMHOUMIAAW,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMHOUMIANW,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMHOUSIAAW,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMHOUSIANW,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMWHSMF,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMWHSMFA,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMWHSMI,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMWHSMIA,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMWHSSF,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMWHSSFA,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMWHUMI,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMWHUMIA,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMWLSMIAAW,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMWLSMIANW,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMWLSSIAAW,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMWLSSIANW,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMWLUMI,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMWLUMIA,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMWLUMIAAW,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMWLUMIANW,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMWLUSIAAW,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMWLUSIANW,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMWSMF,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMWSMFA,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMWSMFAA,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMWSMFAN,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMWSMI,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMWSMIA,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMWSMIAA,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMWSMIAN,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMWHSSFAA,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMWSSF,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMWSSFA,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMWSSFAA,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMWSSFAN,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMWUMI,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMWUMIA,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMWUMIAA,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMWUMIAN,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVNAND,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVNOR,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVOR,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVORC,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVRLW,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVSLW,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVSRWS,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVSRWU,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVSTDDX,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVSTDHX,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVSTDWX,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVSTWHEX,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVSTWHOX,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVSTWWEX,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVSTWWOX,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVSUBFW,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVXOR,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVABS,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVADDSMIAAW,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVADDSSIAAW,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVADDUMIAAW,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVADDUSIAAW,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVCNTLSW,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVCNTLZW,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVEXTSB,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVEXTSH,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVFSABS,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVFSCFSF,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVFSCFSI,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVFSCFUF,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVFSCFUI,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVFSCTSF,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVFSCTSI,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVFSCTSIZ,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVFSCTUF,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVFSCTUI,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVFSCTUIZ,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVFSNABS,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVFSNEG,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMRA,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVNEG,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVRNDW,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVSUBFSMIAAW,		RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVSUBFSSIAAW,		RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVSUBFUMIAAW,		RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVSUBFUSIAAW,		RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVADDIW,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVLDD,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVLDH,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVLDW,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVLHHESPLAT,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVLHHOSSPLAT,		RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVLHHOUSPLAT,		RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVLWHE,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVLWHOS,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVLWHOU,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVLWHSPLAT,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVLWWSPLAT,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVRLWI,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVSLWI,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVSRWIS,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVSRWIU,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVSTDD,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVSTDH,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVSTDW,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVSTWHE,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVSTWHO,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVSTWWE,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVSTWWO,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVSUBIFW,			RS6000_BTC_MISC)
-
-  /* Compares.  */
-RS6000_BUILTIN(SPE_BUILTIN_EVCMPEQ,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVCMPGTS,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVCMPGTU,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVCMPLTS,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVCMPLTU,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVFSCMPEQ,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVFSCMPGT,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVFSCMPLT,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVFSTSTEQ,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVFSTSTGT,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVFSTSTLT,			RS6000_BTC_MISC)
-
-/* EVSEL compares.  */
-RS6000_BUILTIN(SPE_BUILTIN_EVSEL_CMPEQ,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVSEL_CMPGTS,		RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVSEL_CMPGTU,		RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVSEL_CMPLTS,		RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVSEL_CMPLTU,		RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVSEL_FSCMPEQ,		RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVSEL_FSCMPGT,		RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVSEL_FSCMPLT,		RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVSEL_FSTSTEQ,		RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVSEL_FSTSTGT,		RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVSEL_FSTSTLT,		RS6000_BTC_MISC)
-
-RS6000_BUILTIN(SPE_BUILTIN_EVSPLATFI,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVSPLATI,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMWHSSMAA,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMWHSMFAA,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMWHSMIAA,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMWHUSIAA,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMWHUMIAA,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMWHSSFAN,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMWHSSIAN,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMWHSMFAN,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMWHSMIAN,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMWHUSIAN,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMWHUMIAN,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMWHGSSFAA,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMWHGSMFAA,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMWHGSMIAA,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMWHGUMIAA,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMWHGSSFAN,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMWHGSMFAN,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMWHGSMIAN,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_EVMWHGUMIAN,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_MTSPEFSCR,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_MFSPEFSCR,			RS6000_BTC_MISC)
-RS6000_BUILTIN(SPE_BUILTIN_BRINC,			RS6000_BTC_MISC)
-
-/* PAIRED builtins.  */
-RS6000_BUILTIN(PAIRED_BUILTIN_DIVV2SF3,			RS6000_BTC_MISC)
-RS6000_BUILTIN(PAIRED_BUILTIN_ABSV2SF2,			RS6000_BTC_MISC)
-RS6000_BUILTIN(PAIRED_BUILTIN_NEGV2SF2,			RS6000_BTC_MISC)
-RS6000_BUILTIN(PAIRED_BUILTIN_SQRTV2SF2,		RS6000_BTC_MISC)
-RS6000_BUILTIN(PAIRED_BUILTIN_ADDV2SF3,			RS6000_BTC_MISC)
-RS6000_BUILTIN(PAIRED_BUILTIN_SUBV2SF3,			RS6000_BTC_MISC)
-RS6000_BUILTIN(PAIRED_BUILTIN_RESV2SF2,			RS6000_BTC_MISC)
-RS6000_BUILTIN(PAIRED_BUILTIN_MULV2SF3,			RS6000_BTC_MISC)
-RS6000_BUILTIN(PAIRED_BUILTIN_MSUB,			RS6000_BTC_MISC)
-RS6000_BUILTIN(PAIRED_BUILTIN_MADD,			RS6000_BTC_MISC)
-RS6000_BUILTIN(PAIRED_BUILTIN_NMSUB,			RS6000_BTC_MISC)
-RS6000_BUILTIN(PAIRED_BUILTIN_NMADD,			RS6000_BTC_MISC)
-RS6000_BUILTIN(PAIRED_BUILTIN_NABSV2SF2,		RS6000_BTC_MISC)
-RS6000_BUILTIN(PAIRED_BUILTIN_SUM0,			RS6000_BTC_MISC)
-RS6000_BUILTIN(PAIRED_BUILTIN_SUM1,			RS6000_BTC_MISC)
-RS6000_BUILTIN(PAIRED_BUILTIN_MULS0,			RS6000_BTC_MISC)
-RS6000_BUILTIN(PAIRED_BUILTIN_MULS1,			RS6000_BTC_MISC)
-RS6000_BUILTIN(PAIRED_BUILTIN_MERGE00,			RS6000_BTC_MISC)
-RS6000_BUILTIN(PAIRED_BUILTIN_MERGE01,			RS6000_BTC_MISC)
-RS6000_BUILTIN(PAIRED_BUILTIN_MERGE10,			RS6000_BTC_MISC)
-RS6000_BUILTIN(PAIRED_BUILTIN_MERGE11,			RS6000_BTC_MISC)
-RS6000_BUILTIN(PAIRED_BUILTIN_MADDS0,			RS6000_BTC_MISC)
-RS6000_BUILTIN(PAIRED_BUILTIN_MADDS1,			RS6000_BTC_MISC)
-RS6000_BUILTIN(PAIRED_BUILTIN_STX,			RS6000_BTC_MISC)
-RS6000_BUILTIN(PAIRED_BUILTIN_LX,			RS6000_BTC_MISC)
-RS6000_BUILTIN(PAIRED_BUILTIN_SELV2SF4,			RS6000_BTC_MISC)
-RS6000_BUILTIN(PAIRED_BUILTIN_CMPU0,			RS6000_BTC_MISC)
-RS6000_BUILTIN(PAIRED_BUILTIN_CMPU1,			RS6000_BTC_MISC)
-
-  /* VSX builtins.  */
-RS6000_BUILTIN(VSX_BUILTIN_LXSDX,			RS6000_BTC_MEM)
-RS6000_BUILTIN(VSX_BUILTIN_LXVD2X_V2DF,			RS6000_BTC_MEM)
-RS6000_BUILTIN(VSX_BUILTIN_LXVD2X_V2DI,			RS6000_BTC_MEM)
-RS6000_BUILTIN(VSX_BUILTIN_LXVDSX,			RS6000_BTC_MEM)
-RS6000_BUILTIN(VSX_BUILTIN_LXVW4X_V4SF,			RS6000_BTC_MEM)
-RS6000_BUILTIN(VSX_BUILTIN_LXVW4X_V4SI,			RS6000_BTC_MEM)
-RS6000_BUILTIN(VSX_BUILTIN_LXVW4X_V8HI,			RS6000_BTC_MEM)
-RS6000_BUILTIN(VSX_BUILTIN_LXVW4X_V16QI,		RS6000_BTC_MEM)
-RS6000_BUILTIN(VSX_BUILTIN_STXSDX,			RS6000_BTC_MEM)
-RS6000_BUILTIN(VSX_BUILTIN_STXVD2X_V2DF,		RS6000_BTC_MEM)
-RS6000_BUILTIN(VSX_BUILTIN_STXVD2X_V2DI,		RS6000_BTC_MEM)
-RS6000_BUILTIN(VSX_BUILTIN_STXVW4X_V4SF,		RS6000_BTC_MEM)
-RS6000_BUILTIN(VSX_BUILTIN_STXVW4X_V4SI,		RS6000_BTC_MEM)
-RS6000_BUILTIN(VSX_BUILTIN_STXVW4X_V8HI,		RS6000_BTC_MEM)
-RS6000_BUILTIN(VSX_BUILTIN_STXVW4X_V16QI,		RS6000_BTC_MEM)
-RS6000_BUILTIN(VSX_BUILTIN_XSABSDP,			RS6000_BTC_CONST)
-RS6000_BUILTIN(VSX_BUILTIN_XSADDDP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XSCMPODP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XSCMPUDP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XSCPSGNDP,			RS6000_BTC_CONST)
-RS6000_BUILTIN(VSX_BUILTIN_XSCVDPSP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XSCVDPSXDS,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XSCVDPSXWS,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XSCVDPUXDS,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XSCVDPUXWS,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XSCVSPDP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XSCVSXDDP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XSCVUXDDP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XSDIVDP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XSMADDADP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XSMADDMDP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XSMAXDP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XSMINDP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XSMOVDP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XSMSUBADP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XSMSUBMDP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XSMULDP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XSNABSDP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XSNEGDP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XSNMADDADP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XSNMADDMDP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XSNMSUBADP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XSNMSUBMDP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XSRDPI,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XSRDPIC,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XSRDPIM,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XSRDPIP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XSRDPIZ,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XSREDP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XSRSQRTEDP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XSSQRTDP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XSSUBDP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_CPSGNDP,			RS6000_BTC_CONST)
-RS6000_BUILTIN(VSX_BUILTIN_CPSGNSP,			RS6000_BTC_CONST)
-RS6000_BUILTIN(VSX_BUILTIN_XSTDIVDP_FE,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XSTDIVDP_FG,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XSTSQRTDP_FE,		RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XSTSQRTDP_FG,		RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XVABSDP,			RS6000_BTC_CONST)
-RS6000_BUILTIN(VSX_BUILTIN_XVABSSP,			RS6000_BTC_CONST)
-RS6000_BUILTIN(VSX_BUILTIN_XVADDDP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XVADDSP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XVCMPEQDP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XVCMPEQSP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XVCMPGEDP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XVCMPGESP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XVCMPGTDP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XVCMPGTSP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XVCMPEQDP_P,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XVCMPEQSP_P,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XVCMPGEDP_P,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XVCMPGESP_P,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XVCMPGTDP_P,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XVCMPGTSP_P,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XVCPSGNDP,			RS6000_BTC_CONST)
-RS6000_BUILTIN(VSX_BUILTIN_XVCPSGNSP,			RS6000_BTC_CONST)
-RS6000_BUILTIN(VSX_BUILTIN_XVCVDPSP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XVCVDPSXDS,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XVCVDPSXWS,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XVCVDPUXDS,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XVCVDPUXDS_UNS,		RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XVCVDPUXWS,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XVCVSPDP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XVCVSPSXDS,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XVCVSPSXWS,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XVCVSPUXDS,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XVCVSPUXWS,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XVCVSXDDP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XVCVSXDSP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XVCVSXWDP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XVCVSXWSP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XVCVUXDDP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XVCVUXDDP_UNS,		RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XVCVUXDSP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XVCVUXWDP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XVCVUXWSP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XVDIVDP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XVDIVSP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XVMADDDP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XVMADDSP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XVMAXDP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XVMAXSP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XVMINDP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XVMINSP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XVMSUBDP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XVMSUBSP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XVMULDP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XVMULSP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XVNABSDP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XVNABSSP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XVNEGDP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XVNEGSP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XVNMADDDP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XVNMADDSP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XVNMSUBDP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XVNMSUBSP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XVRDPI,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XVRDPIC,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XVRDPIM,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XVRDPIP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XVRDPIZ,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XVREDP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XVRESP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XVRSPI,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XVRSPIC,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XVRSPIM,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XVRSPIP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XVRSPIZ,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XVRSQRTEDP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XVRSQRTESP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XVSQRTDP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XVSQRTSP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XVSUBDP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XVSUBSP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XVTDIVDP_FE,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XVTDIVDP_FG,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XVTDIVSP_FE,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XVTDIVSP_FG,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XVTSQRTDP_FE,		RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XVTSQRTDP_FG,		RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XVTSQRTSP_FE,		RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XVTSQRTSP_FG,		RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XXSEL_2DI,			RS6000_BTC_CONST)
-RS6000_BUILTIN(VSX_BUILTIN_XXSEL_2DF,			RS6000_BTC_CONST)
-RS6000_BUILTIN(VSX_BUILTIN_XXSEL_4SI,			RS6000_BTC_CONST)
-RS6000_BUILTIN(VSX_BUILTIN_XXSEL_4SF,			RS6000_BTC_CONST)
-RS6000_BUILTIN(VSX_BUILTIN_XXSEL_8HI,			RS6000_BTC_CONST)
-RS6000_BUILTIN(VSX_BUILTIN_XXSEL_16QI,			RS6000_BTC_CONST)
-RS6000_BUILTIN(VSX_BUILTIN_XXSEL_2DI_UNS,		RS6000_BTC_CONST)
-RS6000_BUILTIN(VSX_BUILTIN_XXSEL_4SI_UNS,		RS6000_BTC_CONST)
-RS6000_BUILTIN(VSX_BUILTIN_XXSEL_8HI_UNS,		RS6000_BTC_CONST)
-RS6000_BUILTIN(VSX_BUILTIN_XXSEL_16QI_UNS,		RS6000_BTC_CONST)
-RS6000_BUILTIN(VSX_BUILTIN_VPERM_2DI,			RS6000_BTC_CONST)
-RS6000_BUILTIN(VSX_BUILTIN_VPERM_2DF,			RS6000_BTC_CONST)
-RS6000_BUILTIN(VSX_BUILTIN_VPERM_4SI,			RS6000_BTC_CONST)
-RS6000_BUILTIN(VSX_BUILTIN_VPERM_4SF,			RS6000_BTC_CONST)
-RS6000_BUILTIN(VSX_BUILTIN_VPERM_8HI,			RS6000_BTC_CONST)
-RS6000_BUILTIN(VSX_BUILTIN_VPERM_16QI,			RS6000_BTC_CONST)
-RS6000_BUILTIN(VSX_BUILTIN_VPERM_2DI_UNS,		RS6000_BTC_CONST)
-RS6000_BUILTIN(VSX_BUILTIN_VPERM_4SI_UNS,		RS6000_BTC_CONST)
-RS6000_BUILTIN(VSX_BUILTIN_VPERM_8HI_UNS,		RS6000_BTC_CONST)
-RS6000_BUILTIN(VSX_BUILTIN_VPERM_16QI_UNS,		RS6000_BTC_CONST)
-RS6000_BUILTIN(VSX_BUILTIN_XXPERMDI_2DF,		RS6000_BTC_CONST)
-RS6000_BUILTIN(VSX_BUILTIN_XXPERMDI_2DI,		RS6000_BTC_CONST)
-RS6000_BUILTIN(VSX_BUILTIN_XXPERMDI_4SF,		RS6000_BTC_CONST)
-RS6000_BUILTIN(VSX_BUILTIN_XXPERMDI_4SI,		RS6000_BTC_CONST)
-RS6000_BUILTIN(VSX_BUILTIN_XXPERMDI_8HI,		RS6000_BTC_CONST)
-RS6000_BUILTIN(VSX_BUILTIN_XXPERMDI_16QI,		RS6000_BTC_CONST)
-RS6000_BUILTIN(VSX_BUILTIN_CONCAT_2DF,			RS6000_BTC_CONST)
-RS6000_BUILTIN(VSX_BUILTIN_CONCAT_2DI,			RS6000_BTC_CONST)
-RS6000_BUILTIN(VSX_BUILTIN_SET_2DF,			RS6000_BTC_CONST)
-RS6000_BUILTIN(VSX_BUILTIN_SET_2DI,			RS6000_BTC_CONST)
-RS6000_BUILTIN(VSX_BUILTIN_SPLAT_2DF,			RS6000_BTC_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_SPLAT_2DI,			RS6000_BTC_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_XXMRGHW_4SF,			RS6000_BTC_CONST)
-RS6000_BUILTIN(VSX_BUILTIN_XXMRGHW_4SI,			RS6000_BTC_CONST)
-RS6000_BUILTIN(VSX_BUILTIN_XXMRGLW_4SF,			RS6000_BTC_CONST)
-RS6000_BUILTIN(VSX_BUILTIN_XXMRGLW_4SI,			RS6000_BTC_CONST)
-RS6000_BUILTIN(VSX_BUILTIN_XXSLDWI_16QI,		RS6000_BTC_CONST)
-RS6000_BUILTIN(VSX_BUILTIN_XXSLDWI_8HI,			RS6000_BTC_CONST)
-RS6000_BUILTIN(VSX_BUILTIN_XXSLDWI_4SI,			RS6000_BTC_CONST)
-RS6000_BUILTIN(VSX_BUILTIN_XXSLDWI_4SF,			RS6000_BTC_CONST)
-RS6000_BUILTIN(VSX_BUILTIN_XXSLDWI_2DI,			RS6000_BTC_CONST)
-RS6000_BUILTIN(VSX_BUILTIN_XXSLDWI_2DF,			RS6000_BTC_CONST)
-RS6000_BUILTIN(VSX_BUILTIN_VEC_INIT_V2DF,		RS6000_BTC_CONST)
-RS6000_BUILTIN(VSX_BUILTIN_VEC_INIT_V2DI,		RS6000_BTC_CONST)
-RS6000_BUILTIN(VSX_BUILTIN_VEC_SET_V2DF,		RS6000_BTC_CONST)
-RS6000_BUILTIN(VSX_BUILTIN_VEC_SET_V2DI,		RS6000_BTC_CONST)
-RS6000_BUILTIN(VSX_BUILTIN_VEC_EXT_V2DF,		RS6000_BTC_CONST)
-RS6000_BUILTIN(VSX_BUILTIN_VEC_EXT_V2DI,		RS6000_BTC_CONST)
-RS6000_BUILTIN(VSX_BUILTIN_VEC_MERGEL_V2DF,		RS6000_BTC_CONST)
-RS6000_BUILTIN(VSX_BUILTIN_VEC_MERGEL_V2DI,		RS6000_BTC_CONST)
-RS6000_BUILTIN(VSX_BUILTIN_VEC_MERGEH_V2DF,		RS6000_BTC_CONST)
-RS6000_BUILTIN(VSX_BUILTIN_VEC_MERGEH_V2DI,		RS6000_BTC_CONST)
-RS6000_BUILTIN(VSX_BUILTIN_VEC_RSQRT_V4SF,		RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_VEC_RSQRT_V2DF,		RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_RECIP_V4SF,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VSX_BUILTIN_RECIP_V2DF,			RS6000_BTC_FP_PURE)
+
+/* 3 argument Altivec overloaded builtins.  */
+BU_ALTIVEC_OVERLOAD_3 (MADD,       "madd")
+BU_ALTIVEC_OVERLOAD_3 (MADDS,      "madds")
+BU_ALTIVEC_OVERLOAD_3 (MLADD,      "mladd")
+BU_ALTIVEC_OVERLOAD_3 (MRADDS,     "mradds")
+BU_ALTIVEC_OVERLOAD_3 (MSUM,       "msum")
+BU_ALTIVEC_OVERLOAD_3 (MSUMS,      "msums")
+BU_ALTIVEC_OVERLOAD_3 (NMSUB,      "nmsub")
+BU_ALTIVEC_OVERLOAD_3 (PERM,       "perm")
+BU_ALTIVEC_OVERLOAD_3 (SEL,        "sel")
+BU_ALTIVEC_OVERLOAD_3 (VMSUMMBM,   "vmsummbm")
+BU_ALTIVEC_OVERLOAD_3 (VMSUMSHM,   "vmsumshm")
+BU_ALTIVEC_OVERLOAD_3 (VMSUMSHS,   "vmsumshs")
+BU_ALTIVEC_OVERLOAD_3 (VMSUMUBM,   "vmsumubm")
+BU_ALTIVEC_OVERLOAD_3 (VMSUMUHM,   "vmsumuhm")
+BU_ALTIVEC_OVERLOAD_3 (VMSUMUHS,   "vmsumuhs")
+
+/* Altivec DST overloaded builtins.  */
+BU_ALTIVEC_OVERLOAD_D (DST,	   "dst")
+BU_ALTIVEC_OVERLOAD_D (DSTT,	   "dstt")
+BU_ALTIVEC_OVERLOAD_D (DSTST,	   "dstst")
+BU_ALTIVEC_OVERLOAD_D (DSTSTT,	   "dststt")
+
+/* 2 argument Altivec overloaded builtins.  */
+BU_ALTIVEC_OVERLOAD_2 (ADD,	   "add")
+BU_ALTIVEC_OVERLOAD_2 (ADDC,	   "addc")
+BU_ALTIVEC_OVERLOAD_2 (ADDS,	   "adds")
+BU_ALTIVEC_OVERLOAD_2 (AND,	   "and")
+BU_ALTIVEC_OVERLOAD_2 (ANDC,	   "andc")
+BU_ALTIVEC_OVERLOAD_2 (AVG,	   "avg")
+BU_ALTIVEC_OVERLOAD_2 (CMPB,	   "cmpb")
+BU_ALTIVEC_OVERLOAD_2 (CMPEQ,	   "cmpeq")
+BU_ALTIVEC_OVERLOAD_2 (CMPGE,	   "cmpge")
+BU_ALTIVEC_OVERLOAD_2 (CMPGT,	   "cmpgt")
+BU_ALTIVEC_OVERLOAD_2 (CMPLE,	   "cmple")
+BU_ALTIVEC_OVERLOAD_2 (CMPLT,	   "cmplt")
+BU_ALTIVEC_OVERLOAD_2 (COPYSIGN,   "copysign")
+BU_ALTIVEC_OVERLOAD_2 (MAX,	   "max")
+BU_ALTIVEC_OVERLOAD_2 (MERGEH,	   "mergeh")
+BU_ALTIVEC_OVERLOAD_2 (MERGEL,	   "mergel")
+BU_ALTIVEC_OVERLOAD_2 (MIN,	   "min")
+BU_ALTIVEC_OVERLOAD_2 (MULE,	   "mule")
+BU_ALTIVEC_OVERLOAD_2 (MULO,	   "mulo")
+BU_ALTIVEC_OVERLOAD_2 (NOR,	   "nor")
+BU_ALTIVEC_OVERLOAD_2 (OR,	   "or")
+BU_ALTIVEC_OVERLOAD_2 (PACK,	   "pack")
+BU_ALTIVEC_OVERLOAD_2 (PACKPX,	   "packpx")
+BU_ALTIVEC_OVERLOAD_2 (PACKS,	   "packs")
+BU_ALTIVEC_OVERLOAD_2 (PACKSU,	   "packsu")
+BU_ALTIVEC_OVERLOAD_2 (RECIP,	   "recipdiv")
+BU_ALTIVEC_OVERLOAD_2 (RL,	   "rl")
+BU_ALTIVEC_OVERLOAD_2 (SL,	   "sl")
+BU_ALTIVEC_OVERLOAD_2 (SLL,	   "sll")
+BU_ALTIVEC_OVERLOAD_2 (SLO,	   "slo")
+BU_ALTIVEC_OVERLOAD_2 (SR,	   "sr")
+BU_ALTIVEC_OVERLOAD_2 (SRA,	   "sra")
+BU_ALTIVEC_OVERLOAD_2 (SRL,	   "srl")
+BU_ALTIVEC_OVERLOAD_2 (SRO,	   "sro")
+BU_ALTIVEC_OVERLOAD_2 (SUB,	   "sub")
+BU_ALTIVEC_OVERLOAD_2 (SUBC,	   "subc")
+BU_ALTIVEC_OVERLOAD_2 (SUBS,	   "subs")
+BU_ALTIVEC_OVERLOAD_2 (SUM2S,	   "sum2s")
+BU_ALTIVEC_OVERLOAD_2 (SUM4S,	   "sum4s")
+BU_ALTIVEC_OVERLOAD_2 (SUMS,	   "sums")
+BU_ALTIVEC_OVERLOAD_2 (VADDFP,	   "vaddfp")
+BU_ALTIVEC_OVERLOAD_2 (VADDSBS,	   "vaddsbs")
+BU_ALTIVEC_OVERLOAD_2 (VADDSHS,	   "vaddshs")
+BU_ALTIVEC_OVERLOAD_2 (VADDSWS,	   "vaddsws")
+BU_ALTIVEC_OVERLOAD_2 (VADDUBM,	   "vaddubm")
+BU_ALTIVEC_OVERLOAD_2 (VADDUBS,	   "vaddubs")
+BU_ALTIVEC_OVERLOAD_2 (VADDUHM,	   "vadduhm")
+BU_ALTIVEC_OVERLOAD_2 (VADDUHS,	   "vadduhs")
+BU_ALTIVEC_OVERLOAD_2 (VADDUWM,	   "vadduwm")
+BU_ALTIVEC_OVERLOAD_2 (VADDUWS,	   "vadduws")
+BU_ALTIVEC_OVERLOAD_2 (VAVGSB,	   "vavgsb")
+BU_ALTIVEC_OVERLOAD_2 (VAVGSH,	   "vavgsh")
+BU_ALTIVEC_OVERLOAD_2 (VAVGSW,	   "vavgsw")
+BU_ALTIVEC_OVERLOAD_2 (VAVGUB,	   "vavgub")
+BU_ALTIVEC_OVERLOAD_2 (VAVGUH,	   "vavguh")
+BU_ALTIVEC_OVERLOAD_2 (VAVGUW,	   "vavguw")
+BU_ALTIVEC_OVERLOAD_2 (VCMPEQFP,   "vcmpeqfp")
+BU_ALTIVEC_OVERLOAD_2 (VCMPEQUB,   "vcmpequb")
+BU_ALTIVEC_OVERLOAD_2 (VCMPEQUH,   "vcmpequh")
+BU_ALTIVEC_OVERLOAD_2 (VCMPEQUW,   "vcmpequw")
+BU_ALTIVEC_OVERLOAD_2 (VCMPGTFP,   "vcmpgtfp")
+BU_ALTIVEC_OVERLOAD_2 (VCMPGTSB,   "vcmpgtsb")
+BU_ALTIVEC_OVERLOAD_2 (VCMPGTSH,   "vcmpgtsh")
+BU_ALTIVEC_OVERLOAD_2 (VCMPGTSW,   "vcmpgtsw")
+BU_ALTIVEC_OVERLOAD_2 (VCMPGTUB,   "vcmpgtub")
+BU_ALTIVEC_OVERLOAD_2 (VCMPGTUH,   "vcmpgtuh")
+BU_ALTIVEC_OVERLOAD_2 (VCMPGTUW,   "vcmpgtuw")
+BU_ALTIVEC_OVERLOAD_2 (VMAXFP,	   "vmaxfp")
+BU_ALTIVEC_OVERLOAD_2 (VMAXSB,	   "vmaxsb")
+BU_ALTIVEC_OVERLOAD_2 (VMAXSH,	   "vmaxsh")
+BU_ALTIVEC_OVERLOAD_2 (VMAXSW,	   "vmaxsw")
+BU_ALTIVEC_OVERLOAD_2 (VMAXUB,	   "vmaxub")
+BU_ALTIVEC_OVERLOAD_2 (VMAXUH,	   "vmaxuh")
+BU_ALTIVEC_OVERLOAD_2 (VMAXUW,	   "vmaxuw")
+BU_ALTIVEC_OVERLOAD_2 (VMINFP,	   "vminfp")
+BU_ALTIVEC_OVERLOAD_2 (VMINSB,	   "vminsb")
+BU_ALTIVEC_OVERLOAD_2 (VMINSH,	   "vminsh")
+BU_ALTIVEC_OVERLOAD_2 (VMINSW,	   "vminsw")
+BU_ALTIVEC_OVERLOAD_2 (VMINUB,	   "vminub")
+BU_ALTIVEC_OVERLOAD_2 (VMINUH,	   "vminuh")
+BU_ALTIVEC_OVERLOAD_2 (VMINUW,	   "vminuw")
+BU_ALTIVEC_OVERLOAD_2 (VMRGHB,	   "vmrghb")
+BU_ALTIVEC_OVERLOAD_2 (VMRGHH,	   "vmrghh")
+BU_ALTIVEC_OVERLOAD_2 (VMRGHW,	   "vmrghw")
+BU_ALTIVEC_OVERLOAD_2 (VMRGLB,	   "vmrglb")
+BU_ALTIVEC_OVERLOAD_2 (VMRGLH,	   "vmrglh")
+BU_ALTIVEC_OVERLOAD_2 (VMRGLW,	   "vmrglw")
+BU_ALTIVEC_OVERLOAD_2 (VMULESB,	   "vmulesb")
+BU_ALTIVEC_OVERLOAD_2 (VMULESH,	   "vmulesh")
+BU_ALTIVEC_OVERLOAD_2 (VMULEUB,	   "vmuleub")
+BU_ALTIVEC_OVERLOAD_2 (VMULEUH,	   "vmuleuh")
+BU_ALTIVEC_OVERLOAD_2 (VMULOSB,	   "vmulosb")
+BU_ALTIVEC_OVERLOAD_2 (VMULOSH,	   "vmulosh")
+BU_ALTIVEC_OVERLOAD_2 (VMULOUB,	   "vmuloub")
+BU_ALTIVEC_OVERLOAD_2 (VMULOUH,	   "vmulouh")
+BU_ALTIVEC_OVERLOAD_2 (VPKSHSS,	   "vpkshss")
+BU_ALTIVEC_OVERLOAD_2 (VPKSHUS,	   "vpkshus")
+BU_ALTIVEC_OVERLOAD_2 (VPKSWSS,	   "vpkswss")
+BU_ALTIVEC_OVERLOAD_2 (VPKSWUS,	   "vpkswus")
+BU_ALTIVEC_OVERLOAD_2 (VPKUHUM,	   "vpkuhum")
+BU_ALTIVEC_OVERLOAD_2 (VPKUHUS,	   "vpkuhus")
+BU_ALTIVEC_OVERLOAD_2 (VPKUWUM,	   "vpkuwum")
+BU_ALTIVEC_OVERLOAD_2 (VPKUWUS,	   "vpkuwus")
+BU_ALTIVEC_OVERLOAD_2 (VRLB,	   "vrlb")
+BU_ALTIVEC_OVERLOAD_2 (VRLH,	   "vrlh")
+BU_ALTIVEC_OVERLOAD_2 (VRLW,	   "vrlw")
+BU_ALTIVEC_OVERLOAD_2 (VSLB,	   "vslb")
+BU_ALTIVEC_OVERLOAD_2 (VSLH,	   "vslh")
+BU_ALTIVEC_OVERLOAD_2 (VSLW,	   "vslw")
+BU_ALTIVEC_OVERLOAD_2 (VSRAB,	   "vsrab")
+BU_ALTIVEC_OVERLOAD_2 (VSRAH,	   "vsrah")
+BU_ALTIVEC_OVERLOAD_2 (VSRAW,	   "vsraw")
+BU_ALTIVEC_OVERLOAD_2 (VSRB,	   "vsrb")
+BU_ALTIVEC_OVERLOAD_2 (VSRH,	   "vsrh")
+BU_ALTIVEC_OVERLOAD_2 (VSRW,	   "vsrw")
+BU_ALTIVEC_OVERLOAD_2 (VSUBFP,	   "vsubfp")
+BU_ALTIVEC_OVERLOAD_2 (VSUBSBS,	   "vsubsbs")
+BU_ALTIVEC_OVERLOAD_2 (VSUBSHS,	   "vsubshs")
+BU_ALTIVEC_OVERLOAD_2 (VSUBSWS,	   "vsubsws")
+BU_ALTIVEC_OVERLOAD_2 (VSUBUBM,	   "vsububm")
+BU_ALTIVEC_OVERLOAD_2 (VSUBUBS,	   "vsububs")
+BU_ALTIVEC_OVERLOAD_2 (VSUBUHM,	   "vsubuhm")
+BU_ALTIVEC_OVERLOAD_2 (VSUBUHS,	   "vsubuhs")
+BU_ALTIVEC_OVERLOAD_2 (VSUBUWM,	   "vsubuwm")
+BU_ALTIVEC_OVERLOAD_2 (VSUBUWS,	   "vsubuws")
+BU_ALTIVEC_OVERLOAD_2 (VSUM4SBS,   "vsum4sbs")
+BU_ALTIVEC_OVERLOAD_2 (VSUM4SHS,   "vsum4shs")
+BU_ALTIVEC_OVERLOAD_2 (VSUM4UBS,   "vsum4ubs")
+BU_ALTIVEC_OVERLOAD_2 (XOR,	   "xor")
+
+/* 1 argument Altivec overloaded functions.  */
+BU_ALTIVEC_OVERLOAD_1 (ABS,	   "abs")
+BU_ALTIVEC_OVERLOAD_1 (ABSS,	   "abss")
+BU_ALTIVEC_OVERLOAD_1 (CEIL,	   "ceil")
+BU_ALTIVEC_OVERLOAD_1 (EXPTE,	   "expte")
+BU_ALTIVEC_OVERLOAD_1 (FLOOR,	   "floor")
+BU_ALTIVEC_OVERLOAD_1 (LOGE,	   "loge")
+BU_ALTIVEC_OVERLOAD_1 (MTVSCR,	   "mtvscr")
+BU_ALTIVEC_OVERLOAD_1 (NEARBYINT,  "nearbyint")
+BU_ALTIVEC_OVERLOAD_1 (RE,	   "re")
+BU_ALTIVEC_OVERLOAD_1 (RINT,       "rint")
+BU_ALTIVEC_OVERLOAD_1 (ROUND,	   "round")
+BU_ALTIVEC_OVERLOAD_1 (RSQRT,	   "rsqrt")
+BU_ALTIVEC_OVERLOAD_1 (RSQRTE,	   "rsqrte")
+BU_ALTIVEC_OVERLOAD_1 (SQRT,       "sqrt")
+BU_ALTIVEC_OVERLOAD_1 (TRUNC,	   "trunc")
+BU_ALTIVEC_OVERLOAD_1 (UNPACKH,	   "unpackh")
+BU_ALTIVEC_OVERLOAD_1 (UNPACKL,	   "unpackl")
+BU_ALTIVEC_OVERLOAD_1 (VUPKHPX,	   "vupkhpx")
+BU_ALTIVEC_OVERLOAD_1 (VUPKHSB,	   "vupkhsb")
+BU_ALTIVEC_OVERLOAD_1 (VUPKHSH,	   "vupkhsh")
+BU_ALTIVEC_OVERLOAD_1 (VUPKLPX,	   "vupklpx")
+BU_ALTIVEC_OVERLOAD_1 (VUPKLSB,	   "vupklsb")
+BU_ALTIVEC_OVERLOAD_1 (VUPKLSH,	   "vupklsh")
+
+/* Overloaded altivec predicates.  */
+BU_ALTIVEC_OVERLOAD_P (VCMPEQ_P,   "vcmpeq_p")
+BU_ALTIVEC_OVERLOAD_P (VCMPGT_P,   "vcmpgt_p")
+BU_ALTIVEC_OVERLOAD_P (VCMPGE_P,   "vcmpge_p")
+
+/* Overloaded Altivec builtins that are handled as special cases.  */
+BU_ALTIVEC_OVERLOAD_X (CTF,	   "ctf")
+BU_ALTIVEC_OVERLOAD_X (CTS,	   "cts")
+BU_ALTIVEC_OVERLOAD_X (CTU,	   "ctu")
+BU_ALTIVEC_OVERLOAD_X (EXTRACT,	   "extract")
+BU_ALTIVEC_OVERLOAD_X (INSERT,	   "insert")
+BU_ALTIVEC_OVERLOAD_X (LD,	   "ld")
+BU_ALTIVEC_OVERLOAD_X (LDE,	   "lde")
+BU_ALTIVEC_OVERLOAD_X (LDL,	   "ldl")
+BU_ALTIVEC_OVERLOAD_X (LVEBX,	   "lvebx")
+BU_ALTIVEC_OVERLOAD_X (LVEHX,	   "lvehx")
+BU_ALTIVEC_OVERLOAD_X (LVEWX,	   "lvewx")
+BU_ALTIVEC_OVERLOAD_X (LVLX,	   "lvlx")
+BU_ALTIVEC_OVERLOAD_X (LVLXL,	   "lvlxl")
+BU_ALTIVEC_OVERLOAD_X (LVRX,	   "lvrx")
+BU_ALTIVEC_OVERLOAD_X (LVRXL,	   "lvrxl")
+BU_ALTIVEC_OVERLOAD_X (LVSL,	   "lvsl")
+BU_ALTIVEC_OVERLOAD_X (LVSR,	   "lvsr")
+BU_ALTIVEC_OVERLOAD_X (PROMOTE,	   "promote")
+BU_ALTIVEC_OVERLOAD_X (SLD,	   "sld")
+BU_ALTIVEC_OVERLOAD_X (SPLAT,	   "splat")
+BU_ALTIVEC_OVERLOAD_X (SPLATS,	   "splats")
+BU_ALTIVEC_OVERLOAD_X (ST,	   "st")
+BU_ALTIVEC_OVERLOAD_X (STE,	   "ste")
+BU_ALTIVEC_OVERLOAD_X (STEP,	   "step")
+BU_ALTIVEC_OVERLOAD_X (STL,	   "stl")
+BU_ALTIVEC_OVERLOAD_X (STVEBX,	   "stvebx")
+BU_ALTIVEC_OVERLOAD_X (STVEHX,	   "stvehx")
+BU_ALTIVEC_OVERLOAD_X (STVEWX,	   "stvewx")
+BU_ALTIVEC_OVERLOAD_X (STVLX,	   "stvlx")
+BU_ALTIVEC_OVERLOAD_X (STVLXL,	   "stvlxl")
+BU_ALTIVEC_OVERLOAD_X (STVRX,	   "stvrx")
+BU_ALTIVEC_OVERLOAD_X (STVRXL,	   "stvrxl")
+BU_ALTIVEC_OVERLOAD_X (VCFSX,	   "vcfsx")
+BU_ALTIVEC_OVERLOAD_X (VCFUX,	   "vcfux")
+BU_ALTIVEC_OVERLOAD_X (VSPLTB,	   "vspltb")
+BU_ALTIVEC_OVERLOAD_X (VSPLTH,	   "vsplth")
+BU_ALTIVEC_OVERLOAD_X (VSPLTW,	   "vspltw")
+
+/* 3 argument VSX builtins.  */
+BU_VSX_3 (XVMADDSP,           "xvmaddsp",       CONST, 	fmav4sf4)
+BU_VSX_3 (XVMSUBSP,           "xvmsubsp",       CONST, 	fmsv4sf4)
+BU_VSX_3 (XVNMADDSP,          "xvnmaddsp",      CONST, 	nfmav4sf4)
+BU_VSX_3 (XVNMSUBSP,          "xvnmsubsp",      CONST, 	nfmsv4sf4)
+
+BU_VSX_3 (XVMADDDP,           "xvmadddp",       CONST, 	fmav2df4)
+BU_VSX_3 (XVMSUBDP,           "xvmsubdp",       CONST, 	fmsv2df4)
+BU_VSX_3 (XVNMADDDP,          "xvnmadddp",      CONST, 	nfmav2df4)
+BU_VSX_3 (XVNMSUBDP,          "xvnmsubdp",      CONST, 	nfmsv2df4)
+
+BU_VSX_3 (XXSEL_2DI,          "xxsel_2di",      CONST, 	vector_select_v2di)
+BU_VSX_3 (XXSEL_2DF,          "xxsel_2df",      CONST, 	vector_select_v2df)
+BU_VSX_3 (XXSEL_4SF,          "xxsel_4sf",      CONST, 	vector_select_v4sf)
+BU_VSX_3 (XXSEL_4SI,          "xxsel_4si",      CONST, 	vector_select_v4si)
+BU_VSX_3 (XXSEL_8HI,          "xxsel_8hi",      CONST, 	vector_select_v8hi)
+BU_VSX_3 (XXSEL_16QI,         "xxsel_16qi",     CONST, 	vector_select_v16qi)
+BU_VSX_3 (XXSEL_2DI_UNS,      "xxsel_2di_uns",  CONST, 	vector_select_v2di_uns)
+BU_VSX_3 (XXSEL_4SI_UNS,      "xxsel_4si_uns",  CONST, 	vector_select_v4si_uns)
+BU_VSX_3 (XXSEL_8HI_UNS,      "xxsel_8hi_uns",  CONST, 	vector_select_v8hi_uns)
+BU_VSX_3 (XXSEL_16QI_UNS,     "xxsel_16qi_uns", CONST, 	vector_select_v16qi_uns)
+
+BU_VSX_3 (VPERM_2DI,          "vperm_2di",      CONST, 	altivec_vperm_v2di)
+BU_VSX_3 (VPERM_2DF,          "vperm_2df",      CONST, 	altivec_vperm_v2df)
+BU_VSX_3 (VPERM_4SF,          "vperm_4sf",      CONST, 	altivec_vperm_v4sf)
+BU_VSX_3 (VPERM_4SI,          "vperm_4si",      CONST, 	altivec_vperm_v4si)
+BU_VSX_3 (VPERM_8HI,          "vperm_8hi",      CONST, 	altivec_vperm_v8hi)
+BU_VSX_3 (VPERM_16QI,         "vperm_16qi",     CONST, 	altivec_vperm_v16qi)
+BU_VSX_3 (VPERM_2DI_UNS,      "vperm_2di_uns",  CONST, 	altivec_vperm_v2di_uns)
+BU_VSX_3 (VPERM_4SI_UNS,      "vperm_4si_uns",  CONST, 	altivec_vperm_v4si_uns)
+BU_VSX_3 (VPERM_8HI_UNS,      "vperm_8hi_uns",  CONST, 	altivec_vperm_v8hi_uns)
+BU_VSX_3 (VPERM_16QI_UNS,     "vperm_16qi_uns", CONST, 	altivec_vperm_v16qi_uns)
+
+BU_VSX_3 (XXPERMDI_2DF,       "xxpermdi_2df",   CONST, 	vsx_xxpermdi_v2df)
+BU_VSX_3 (XXPERMDI_2DI,       "xxpermdi_2di",   CONST, 	vsx_xxpermdi_v2di)
+BU_VSX_3 (XXPERMDI_4SF,       "xxpermdi_4sf",   CONST, 	vsx_xxpermdi_v4sf)
+BU_VSX_3 (XXPERMDI_4SI,       "xxpermdi_4si",   CONST, 	vsx_xxpermdi_v4si)
+BU_VSX_3 (XXPERMDI_8HI,       "xxpermdi_8hi",   CONST, 	vsx_xxpermdi_v8hi)
+BU_VSX_3 (XXPERMDI_16QI,      "xxpermdi_16qi",  CONST, 	vsx_xxpermdi_v16qi)
+BU_VSX_3 (SET_2DF,            "set_2df",        CONST, 	vsx_set_v2df)
+BU_VSX_3 (SET_2DI,            "set_2di",        CONST, 	vsx_set_v2di)
+BU_VSX_3 (XXSLDWI_2DI,        "xxsldwi_2di",    CONST, 	vsx_xxsldwi_v2di)
+BU_VSX_3 (XXSLDWI_2DF,        "xxsldwi_2df",    CONST, 	vsx_xxsldwi_v2df)
+BU_VSX_3 (XXSLDWI_4SF,        "xxsldwi_4sf",    CONST, 	vsx_xxsldwi_v4sf)
+BU_VSX_3 (XXSLDWI_4SI,        "xxsldwi_4si",    CONST, 	vsx_xxsldwi_v4si)
+BU_VSX_3 (XXSLDWI_8HI,        "xxsldwi_8hi",    CONST, 	vsx_xxsldwi_v8hi)
+BU_VSX_3 (XXSLDWI_16QI,       "xxsldwi_16qi",   CONST, 	vsx_xxsldwi_v16qi)
+
+/* 2 argument VSX builtins.  */
+BU_VSX_2 (XVADDDP,	      "xvadddp",	FP,	addv2df3)
+BU_VSX_2 (XVSUBDP,	      "xvsubdp",	FP,	subv2df3)
+BU_VSX_2 (XVMULDP,	      "xvmuldp",	FP,	mulv2df3)
+BU_VSX_2 (XVDIVDP,	      "xvdivdp",	FP,	divv2df3)
+BU_VSX_2 (RECIP_V2DF,	      "xvrecipdivdp",	FP,	recipv2df3)
+BU_VSX_2 (XVMINDP,	      "xvmindp",	CONST,	sminv2df3)
+BU_VSX_2 (XVMAXDP,	      "xvmaxdp",	CONST,	smaxv2df3)
+BU_VSX_2 (XVTDIVDP_FE,	      "xvtdivdp_fe",	CONST,	vsx_tdivv2df3_fe)
+BU_VSX_2 (XVTDIVDP_FG,	      "xvtdivdp_fg",	CONST,	vsx_tdivv2df3_fg)
+BU_VSX_2 (XVCMPEQDP,	      "xvcmpeqdp",	CONST,	vector_eqv2df)
+BU_VSX_2 (XVCMPGTDP,	      "xvcmpgtdp",	CONST,	vector_gtv2df)
+BU_VSX_2 (XVCMPGEDP,	      "xvcmpgedp",	CONST,	vector_gev2df)
+
+BU_VSX_2 (XVADDSP,	      "xvaddsp",	FP,	addv4sf3)
+BU_VSX_2 (XVSUBSP,	      "xvsubsp",	FP,	subv4sf3)
+BU_VSX_2 (XVMULSP,	      "xvmulsp",	FP,	mulv4sf3)
+BU_VSX_2 (XVDIVSP,	      "xvdivsp",	FP,	divv4sf3)
+BU_VSX_2 (RECIP_V4SF,	      "xvrecipdivsp",	FP,	recipv4sf3)
+BU_VSX_2 (XVMINSP,	      "xvminsp",	CONST,	sminv4sf3)
+BU_VSX_2 (XVMAXSP,	      "xvmaxsp",	CONST,	smaxv4sf3)
+BU_VSX_2 (XVTDIVSP_FE,	      "xvtdivsp_fe",	CONST,	vsx_tdivv4sf3_fe)
+BU_VSX_2 (XVTDIVSP_FG,	      "xvtdivsp_fg",	CONST,	vsx_tdivv4sf3_fg)
+BU_VSX_2 (XVCMPEQSP,	      "xvcmpeqsp",	CONST,	vector_eqv4sf)
+BU_VSX_2 (XVCMPGTSP,	      "xvcmpgtsp",	CONST,	vector_gtv4sf)
+BU_VSX_2 (XVCMPGESP,	      "xvcmpgesp",	CONST,	vector_gev4sf)
+
+BU_VSX_2 (XSMINDP,	      "xsmindp",	CONST,	smindf3)
+BU_VSX_2 (XSMAXDP,	      "xsmaxdp",	CONST,	smaxdf3)
+BU_VSX_2 (XSTDIVDP_FE,	      "xstdivdp_fe",	CONST,	vsx_tdivdf3_fe)
+BU_VSX_2 (XSTDIVDP_FG,	      "xstdivdp_fg",	CONST,	vsx_tdivdf3_fg)
+BU_VSX_2 (CPSGNDP,	      "cpsgndp",	CONST,	vector_copysignv2df3)
+BU_VSX_2 (CPSGNSP,	      "cpsgnsp",	CONST,	vector_copysignv4sf3)
+
+BU_VSX_2 (CONCAT_2DF,	      "concat_2df",	CONST,	vsx_concat_v2df)
+BU_VSX_2 (CONCAT_2DI,	      "concat_2di",	CONST,	vsx_concat_v2di)
+BU_VSX_2 (SPLAT_2DF,	      "splat_2df",	CONST,	vsx_splat_v2df)
+BU_VSX_2 (SPLAT_2DI,	      "splat_2di",	CONST,	vsx_splat_v2di)
+BU_VSX_2 (XXMRGHW_4SF,	      "xxmrghw",	CONST,	vsx_xxmrghw_v4sf)
+BU_VSX_2 (XXMRGHW_4SI,	      "xxmrghw_4si",	CONST,	vsx_xxmrghw_v4si)
+BU_VSX_2 (XXMRGLW_4SF,	      "xxmrglw",	CONST,	vsx_xxmrglw_v4sf)
+BU_VSX_2 (XXMRGLW_4SI,	      "xxmrglw_4si",	CONST,	vsx_xxmrglw_v4si)
+BU_VSX_2 (VEC_MERGEL_V2DF,    "mergel_2df",	CONST,	vec_interleave_lowv2df)
+BU_VSX_2 (VEC_MERGEL_V2DI,    "mergel_2di",	CONST,	vec_interleave_lowv2di)
+BU_VSX_2 (VEC_MERGEH_V2DF,    "mergeh_2df",	CONST,	vec_interleave_highv2df)
+BU_VSX_2 (VEC_MERGEH_V2DI,    "mergeh_2di",	CONST,	vec_interleave_highv2di)
+
+/* VSX abs builtin functions.  */
+BU_VSX_A (XVABSDP,	      "xvabsdp",	CONST,	absv2df2)
+BU_VSX_A (XVNABSDP,	      "xvnabsdp",	CONST,	vsx_nabsv2df2)
+BU_VSX_A (XVABSSP,	      "xvabssp",	CONST,	absv4sf2)
+BU_VSX_A (XVNABSSP,	      "xvnabssp",	CONST,	vsx_nabsv4sf2)
+
+/* 1 argument VSX builtin functions.  */
+BU_VSX_1 (XVNEGDP,	      "xvnegdp",	CONST,	negv2df2)
+BU_VSX_1 (XVSQRTDP,	      "xvsqrtdp",	CONST,	sqrtv2df2)
+BU_VSX_1 (RSQRT_2DF,	      "xvrsqrtdp",	CONST,	rsqrtv2df2)
+BU_VSX_1 (XVRSQRTEDP,	      "xvrsqrtedp",	CONST,	rsqrtev2df2)
+BU_VSX_1 (XVTSQRTDP_FE,	      "xvtsqrtdp_fe",	CONST,	vsx_tsqrtv2df2_fe)
+BU_VSX_1 (XVTSQRTDP_FG,	      "xvtsqrtdp_fg",	CONST,	vsx_tsqrtv2df2_fg)
+BU_VSX_1 (XVREDP,	      "xvredp",		CONST,	vsx_frev2df2)
+
+BU_VSX_1 (XVNEGSP,	      "xvnegsp",	CONST,	negv4sf2)
+BU_VSX_1 (XVSQRTSP,	      "xvsqrtsp",	CONST,	sqrtv4sf2)
+BU_VSX_1 (RSQRT_4SF,          "xvrsqrtsp",	CONST,	rsqrtv4sf2)
+BU_VSX_1 (XVRSQRTESP,	      "xvrsqrtesp",	CONST,	rsqrtev4sf2)
+BU_VSX_1 (XVTSQRTSP_FE,	      "xvtsqrtsp_fe",	CONST,	vsx_tsqrtv4sf2_fe)
+BU_VSX_1 (XVTSQRTSP_FG,	      "xvtsqrtsp_fg",	CONST,	vsx_tsqrtv4sf2_fg)
+BU_VSX_1 (XVRESP,	      "xvresp",		CONST,	vsx_frev4sf2)
+
+BU_VSX_1 (XSCVDPSP,	      "xscvdpsp",	CONST,	vsx_xscvdpsp)
+BU_VSX_1 (XSCVSPDP,	      "xscvspdp",	CONST,	vsx_xscvdpsp)
+BU_VSX_1 (XVCVDPSP,	      "xvcvdpsp",	CONST,	vsx_xvcvdpsp)
+BU_VSX_1 (XVCVSPDP,	      "xvcvspdp",	CONST,	vsx_xvcvspdp)
+BU_VSX_1 (XSTSQRTDP_FE,	      "xstsqrtdp_fe",	CONST,	vsx_tsqrtdf2_fe)
+BU_VSX_1 (XSTSQRTDP_FG,	      "xstsqrtdp_fg",	CONST,	vsx_tsqrtdf2_fg)
+
+BU_VSX_1 (XVCVDPSXDS,	      "xvcvdpsxds",	CONST,	vsx_fix_truncv2dfv2di2)
+BU_VSX_1 (XVCVDPUXDS,	      "xvcvdpuxds",	CONST,	vsx_fixuns_truncv2dfv2di2)
+BU_VSX_1 (XVCVDPUXDS_UNS,     "xvcvdpuxds_uns",	CONST,	vsx_fixuns_truncv2dfv2di2)
+BU_VSX_1 (XVCVSXDDP,	      "xvcvsxddp",	CONST,	vsx_floatv2div2df2)
+BU_VSX_1 (XVCVUXDDP,	      "xvcvuxddp",	CONST,	vsx_floatunsv2div2df2)
+BU_VSX_1 (XVCVUXDDP_UNS,       "xvcvuxddp_uns",	CONST,	vsx_floatunsv2div2df2)
+
+BU_VSX_1 (XVCVSPSXWS,	      "xvcvspsxws",	CONST,	vsx_fix_truncv4sfv4si2)
+BU_VSX_1 (XVCVSPUXWS,	      "xvcvspuxws",	CONST,	vsx_fixuns_truncv4sfv4si2)
+BU_VSX_1 (XVCVSXWSP,	      "xvcvsxwsp",	CONST,	vsx_floatv4siv4sf2)
+BU_VSX_1 (XVCVUXWSP,	      "xvcvuxwsp",	CONST,	vsx_floatunsv4siv4sf2)
+
+BU_VSX_1 (XVCVDPSXWS,	      "xvcvdpsxws",	CONST,	vsx_xvcvdpsxws)
+BU_VSX_1 (XVCVDPUXWS,	      "xvcvdpuxws",	CONST,	vsx_xvcvdpuxws)
+BU_VSX_1 (XVCVSXWDP,	      "xvcvsxwdp",	CONST,	vsx_xvcvsxwdp)
+BU_VSX_1 (XVCVUXWDP,	      "xvcvuxwdp",	CONST,	vsx_xvcvuxwdp)
+BU_VSX_1 (XVRDPI,	      "xvrdpi",		CONST,	vsx_xvrdpi)
+BU_VSX_1 (XVRDPIC,	      "xvrdpic",	CONST,	vsx_xvrdpic)
+BU_VSX_1 (XVRDPIM,	      "xvrdpim",	CONST,	vsx_floorv2df2)
+BU_VSX_1 (XVRDPIP,	      "xvrdpip",	CONST,	vsx_ceilv2df2)
+BU_VSX_1 (XVRDPIZ,	      "xvrdpiz",	CONST,	vsx_btruncv2df2)
+
+BU_VSX_1 (XVCVSPSXDS,	      "xvcvspsxds",	CONST,	vsx_xvcvspsxds)
+BU_VSX_1 (XVCVSPUXDS,	      "xvcvspuxds",	CONST,	vsx_xvcvspuxds)
+BU_VSX_1 (XVCVSXDSP,	      "xvcvsxdsp",	CONST,	vsx_xvcvsxdsp)
+BU_VSX_1 (XVCVUXDSP,	      "xvcvuxdsp",	CONST,	vsx_xvcvuxdsp)
+BU_VSX_1 (XVRSPI,	      "xvrspi",		CONST,	vsx_xvrspi)
+BU_VSX_1 (XVRSPIC,	      "xvrspic",	CONST,	vsx_xvrspic)
+BU_VSX_1 (XVRSPIM,	      "xvrspim",	CONST,	vsx_floorv4sf2)
+BU_VSX_1 (XVRSPIP,	      "xvrspip",	CONST,	vsx_ceilv4sf2)
+BU_VSX_1 (XVRSPIZ,	      "xvrspiz",	CONST,	vsx_btruncv4sf2)
+
+BU_VSX_1 (XSRDPI,	      "xsrdpi",		CONST,	vsx_xsrdpi)
+BU_VSX_1 (XSRDPIC,	      "xsrdpic",	CONST,	vsx_xsrdpic)
+BU_VSX_1 (XSRDPIM,	      "xsrdpim",	CONST,	vsx_floordf2)
+BU_VSX_1 (XSRDPIP,	      "xsrdpip",	CONST,	vsx_ceildf2)
+BU_VSX_1 (XSRDPIZ,	      "xsrdpiz",	CONST,	vsx_btruncdf2)
+
+/* VSX predicate functions.  */
+BU_VSX_P (XVCMPEQSP_P,	      "xvcmpeqsp_p",	CONST,	vector_eq_v4sf_p)
+BU_VSX_P (XVCMPGESP_P,	      "xvcmpgesp_p",	CONST,	vector_ge_v4sf_p)
+BU_VSX_P (XVCMPGTSP_P,	      "xvcmpgtsp_p",	CONST,	vector_gt_v4sf_p)
+BU_VSX_P (XVCMPEQDP_P,	      "xvcmpeqdp_p",	CONST,	vector_eq_v2df_p)
+BU_VSX_P (XVCMPGEDP_P,	      "xvcmpgedp_p",	CONST,	vector_ge_v2df_p)
+BU_VSX_P (XVCMPGTDP_P,	      "xvcmpgtdp_p",	CONST,	vector_gt_v2df_p)
+
+/* VSX builtins that are handled as special cases.  */
+BU_VSX_X (LXSDX,	      "lxsdx",		MEM)
+BU_VSX_X (LXVD2X_V2DF,	      "lxvd2x_v2df",	MEM)
+BU_VSX_X (LXVD2X_V2DI,	      "lxvd2x_v2di",	MEM)
+BU_VSX_X (LXVDSX,	      "lxvdsx",		MEM)
+BU_VSX_X (LXVW4X_V4SF,	      "lxvw4x_v4sf",	MEM)
+BU_VSX_X (LXVW4X_V4SI,        "lxvw4x_v4si",	MEM)
+BU_VSX_X (LXVW4X_V8HI,        "lxvw4x_v8hi",	MEM)
+BU_VSX_X (LXVW4X_V16QI,	      "lxvw4x_v16qi",	MEM)
+BU_VSX_X (STXSDX,	      "stxsdx",		MEM)
+BU_VSX_X (STXVD2X_V2DF,	      "stxsdx_v2df",	MEM)
+BU_VSX_X (STXVD2X_V2DI,	      "stxsdx_v2di",	MEM)
+BU_VSX_X (STXVW4X_V4SF,	      "stxsdx_v4sf",	MEM)
+BU_VSX_X (STXVW4X_V4SI,	      "stxsdx_v4si",	MEM)
+BU_VSX_X (STXVW4X_V8HI,	      "stxsdx_v8hi",	MEM)
+BU_VSX_X (STXVW4X_V16QI,      "stxsdx_v16qi",	MEM)
+BU_VSX_X (XSABSDP,	      "xsabsdp",	CONST)
+BU_VSX_X (XSADDDP,	      "xsadddp",	FP)
+BU_VSX_X (XSCMPODP,	      "xscmpodp",	FP)
+BU_VSX_X (XSCMPUDP,	      "xscmpudp",	FP)
+BU_VSX_X (XSCVDPSXDS,	      "xscvdpsxds",	FP)
+BU_VSX_X (XSCVDPSXWS,	      "xscvdpsxws",	FP)
+BU_VSX_X (XSCVDPUXDS,	      "xscvdpuxds",	FP)
+BU_VSX_X (XSCVDPUXWS,	      "xscvdpuxws",	FP)
+BU_VSX_X (XSCVSXDDP,	      "xscvsxddp",	FP)
+BU_VSX_X (XSCVUXDDP,	      "xscvuxddp",	FP)
+BU_VSX_X (XSDIVDP,	      "xsdivdp",	FP)
+BU_VSX_X (XSMADDADP,	      "xsmaddadp",	FP)
+BU_VSX_X (XSMADDMDP,	      "xsmaddmdp",	FP)
+BU_VSX_X (XSMOVDP,	      "xsmovdp",	FP)
+BU_VSX_X (XSMSUBADP,	      "xsmsubadp",	FP)
+BU_VSX_X (XSMSUBMDP,	      "xsmsubmdp",	FP)
+BU_VSX_X (XSMULDP,	      "xsmuldp",	FP)
+BU_VSX_X (XSNABSDP,	      "xsnabsdp",	FP)
+BU_VSX_X (XSNEGDP,	      "xsnegdp",	FP)
+BU_VSX_X (XSNMADDADP,	      "xsnmaddadp",	FP)
+BU_VSX_X (XSNMADDMDP,	      "xsnmaddmdp",	FP)
+BU_VSX_X (XSNMSUBADP,	      "xsnmsubadp",	FP)
+BU_VSX_X (XSNMSUBMDP,	      "xsnmsubmdp",	FP)
+BU_VSX_X (XSSUBDP,	      "xssubdp",	FP)
+BU_VSX_X (VEC_INIT_V2DF,      "vec_init_v2df",	CONST)
+BU_VSX_X (VEC_INIT_V2DI,      "vec_init_v2di",	CONST)
+BU_VSX_X (VEC_SET_V2DF,	      "vec_set_v2df",	CONST)
+BU_VSX_X (VEC_SET_V2DI,	      "vec_set_v2di",	CONST)
+BU_VSX_X (VEC_EXT_V2DF,	      "vec_ext_v2df",	CONST)
+BU_VSX_X (VEC_EXT_V2DI,	      "vec_ext_v2di",	CONST)
 
 /* VSX overloaded builtins, add the overloaded functions not present in
    Altivec.  */
-RS6000_BUILTIN(VSX_BUILTIN_VEC_MUL,			RS6000_BTC_MISC)
-RS6000_BUILTIN_EQUATE(VSX_BUILTIN_OVERLOADED_FIRST,
-		      VSX_BUILTIN_VEC_MUL)
-RS6000_BUILTIN(VSX_BUILTIN_VEC_MSUB,			RS6000_BTC_MISC)
-RS6000_BUILTIN(VSX_BUILTIN_VEC_NMADD,			RS6000_BTC_MISC)
-RS6000_BUILTIN(VSX_BUITLIN_VEC_NMSUB,			RS6000_BTC_MISC)
-RS6000_BUILTIN(VSX_BUILTIN_VEC_DIV,			RS6000_BTC_MISC)
-RS6000_BUILTIN(VSX_BUILTIN_VEC_XXMRGHW,			RS6000_BTC_MISC)
-RS6000_BUILTIN(VSX_BUILTIN_VEC_XXMRGLW,			RS6000_BTC_MISC)
-RS6000_BUILTIN(VSX_BUILTIN_VEC_XXPERMDI,		RS6000_BTC_MISC)
-RS6000_BUILTIN(VSX_BUILTIN_VEC_XXSLDWI,			RS6000_BTC_MISC)
-RS6000_BUILTIN(VSX_BUILTIN_VEC_XXSPLTD,			RS6000_BTC_MISC)
-RS6000_BUILTIN(VSX_BUILTIN_VEC_XXSPLTW,			RS6000_BTC_MISC)
-RS6000_BUILTIN(VSX_BUILTIN_VEC_LD,			RS6000_BTC_MISC)
-RS6000_BUILTIN(VSX_BUILTIN_VEC_ST,			RS6000_BTC_MISC)
-RS6000_BUILTIN_EQUATE(VSX_BUILTIN_OVERLOADED_LAST,
-		      VSX_BUILTIN_VEC_ST)
-
-/* Combined VSX/Altivec builtins.  */
-RS6000_BUILTIN(VECTOR_BUILTIN_FLOAT_V4SI_V4SF,		RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VECTOR_BUILTIN_UNSFLOAT_V4SI_V4SF,	RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VECTOR_BUILTIN_FIX_V4SF_V4SI,		RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(VECTOR_BUILTIN_FIXUNS_V4SF_V4SI,		RS6000_BTC_FP_PURE)
 
+/* 3 argument VSX overloaded builtins.  */
+BU_VSX_OVERLOAD_3  (MSUB,     "msub")
+BU_VSX_OVERLOAD_3  (NMADD,    "nmadd")
+BU_VSX_OVERLOAD_3V (XXPERMDI, "xxpermdi")
+BU_VSX_OVERLOAD_3V (XXSLDWI,  "xxsldwi")
+
+/* 2 argument VSX overloaded builtin functions.  */
+BU_VSX_OVERLOAD_2 (MUL,	     "mul")
+BU_VSX_OVERLOAD_2 (DIV,	     "div")
+BU_VSX_OVERLOAD_2 (XXMRGHW,  "xxmrghw")
+BU_VSX_OVERLOAD_2 (XXMRGLW,  "xxmrglw")
+BU_VSX_OVERLOAD_2 (XXSPLTD,  "xxspltd")
+BU_VSX_OVERLOAD_2 (XXSPLTW,  "xxspltw")
+
+/* VSX builtins that are handled as special cases.  */
+BU_VSX_OVERLOAD_X (LD,	     "ld")
+BU_VSX_OVERLOAD_X (ST,	     "st")
+
+/* 3 argument paired floating point builtins.  */
+BU_PAIRED_3 (MSUB,            "msub",           FP, 	fmsv2sf4)
+BU_PAIRED_3 (MADD,            "madd",           FP, 	fmav2sf4)
+BU_PAIRED_3 (MADDS0,          "madds0",         FP, 	paired_madds0)
+BU_PAIRED_3 (MADDS1,          "madds1",         FP, 	paired_madds1)
+BU_PAIRED_3 (NMSUB,           "nmsub",          FP, 	nfmsv2sf4)
+BU_PAIRED_3 (NMADD,           "nmadd",          FP, 	nfmav2sf4)
+BU_PAIRED_3 (SUM0,            "sum0",           FP, 	paired_sum0)
+BU_PAIRED_3 (SUM1,            "sum1",           FP, 	paired_sum1)
+BU_PAIRED_3 (SELV2SF4,        "selv2sf4",       CONST, 	selv2sf4)
+
+/* 2 argument paired floating point builtins.  */
+BU_PAIRED_2 (DIVV2SF3,	      "divv2sf3",	FP,	paired_divv2sf3)
+BU_PAIRED_2 (ADDV2SF3,	      "addv2sf3",	FP,	paired_addv2sf3)
+BU_PAIRED_2 (SUBV2SF3,	      "subv2sf3",	FP,	paired_subv2sf3)
+BU_PAIRED_2 (MULV2SF3,	      "mulv2sf3",	FP,	paired_mulv2sf3)
+BU_PAIRED_2 (MULS0,	      "muls0",		FP,	paired_muls0)
+BU_PAIRED_2 (MULS1,	      "muls1",		FP,	paired_muls1)
+BU_PAIRED_2 (MERGE00,	      "merge00",	CONST,	paired_merge00)
+BU_PAIRED_2 (MERGE01,	      "merge01",	CONST,	paired_merge01)
+BU_PAIRED_2 (MERGE10,	      "merge10",	CONST,	paired_merge10)
+BU_PAIRED_2 (MERGE11,	      "merge11",	CONST,	paired_merge11)
+
+/* 1 argument paired floating point builtin functions.  */
+BU_PAIRED_1 (ABSV2SF2,	      "absv2sf2",	CONST,	paired_absv2sf2)
+BU_PAIRED_1 (NABSV2SF2,	      "nabsv2sf2",	CONST,	nabsv2sf2)
+BU_PAIRED_1 (NEGV2SF2,	      "negv2sf2",	CONST,	paired_negv2sf2)
+BU_PAIRED_1 (SQRTV2SF2,	      "sqrtv2sf2",	FP,	sqrtv2sf2)
+BU_PAIRED_1 (RESV2SF,	      "resv2sf2",	FP,	resv2sf2)
+
+/* PAIRED builtins that are handled as special cases.  */
+BU_PAIRED_X (STX,	      "stx",		MISC)
+BU_PAIRED_X (LX,	      "lx",		MISC)
+
+/* Paired predicates.  */
+BU_PAIRED_P (CMPU0,	"cmpu0",	CONST,	paired_cmpu0)
+BU_PAIRED_P (CMPU1,	"cmpu1",	CONST,	paired_cmpu1)
+
+/* PowerPC E500 builtins (SPE).  */
+
+BU_SPE_2 (EVADDW,	"evaddw",	MISC,	addv2si3)
+BU_SPE_2 (EVAND,	"evand",	MISC,	andv2si3)
+BU_SPE_2 (EVANDC,	"evandc",	MISC,	spe_evandc)
+BU_SPE_2 (EVDIVWS,	"evdivws",	MISC,	divv2si3)
+BU_SPE_2 (EVDIVWU,	"evdivwu",	MISC,	spe_evdivwu)
+BU_SPE_2 (EVEQV,	"eveqv",	MISC,	spe_eveqv)
+BU_SPE_2 (EVFSADD,	"evfsadd",	MISC,	spe_evfsadd)
+BU_SPE_2 (EVFSDIV,	"evfsdiv",	MISC,	spe_evfsdiv)
+BU_SPE_2 (EVFSMUL,	"evfsmul",	MISC,	spe_evfsmul)
+BU_SPE_2 (EVFSSUB,	"evfssub",	MISC,	spe_evfssub)
+BU_SPE_2 (EVMERGEHI,	"evmergehi",	MISC,	spe_evmergehi)
+BU_SPE_2 (EVMERGEHILO,	"evmergehilo",	MISC,	spe_evmergehilo)
+BU_SPE_2 (EVMERGELO,	"evmergelo",	MISC,	spe_evmergelo)
+BU_SPE_2 (EVMERGELOHI,	"evmergelohi",	MISC,	spe_evmergelohi)
+BU_SPE_2 (EVMHEGSMFAA,	"evmhegsmfaa",	MISC,	spe_evmhegsmfaa)
+BU_SPE_2 (EVMHEGSMFAN,	"evmhegsmfan",	MISC,	spe_evmhegsmfan)
+BU_SPE_2 (EVMHEGSMIAA,	"evmhegsmiaa",	MISC,	spe_evmhegsmiaa)
+BU_SPE_2 (EVMHEGSMIAN,	"evmhegsmian",	MISC,	spe_evmhegsmian)
+BU_SPE_2 (EVMHEGUMIAA,	"evmhegumiaa",	MISC,	spe_evmhegumiaa)
+BU_SPE_2 (EVMHEGUMIAN,	"evmhegumian",	MISC,	spe_evmhegumian)
+BU_SPE_2 (EVMHESMF,	"evmhesmf",	MISC,	spe_evmhesmf)
+BU_SPE_2 (EVMHESMFA,	"evmhesmfa",	MISC,	spe_evmhesmfa)
+BU_SPE_2 (EVMHESMFAAW,	"evmhesmfaaw",	MISC,	spe_evmhesmfaaw)
+BU_SPE_2 (EVMHESMFANW,	"evmhesmfanw",	MISC,	spe_evmhesmfanw)
+BU_SPE_2 (EVMHESMI,	"evmhesmi",	MISC,	spe_evmhesmi)
+BU_SPE_2 (EVMHESMIA,	"evmhesmia",	MISC,	spe_evmhesmia)
+BU_SPE_2 (EVMHESMIAAW,	"evmhesmiaaw",	MISC,	spe_evmhesmiaaw)
+BU_SPE_2 (EVMHESMIANW,	"evmhesmianw",	MISC,	spe_evmhesmianw)
+BU_SPE_2 (EVMHESSF,	"evmhessf",	MISC,	spe_evmhessf)
+BU_SPE_2 (EVMHESSFA,	"evmhessfa",	MISC,	spe_evmhessfa)
+BU_SPE_2 (EVMHESSFAAW,	"evmhessfaaw",	MISC,	spe_evmhessfaaw)
+BU_SPE_2 (EVMHESSFANW,	"evmhessfanw",	MISC,	spe_evmhessfanw)
+BU_SPE_2 (EVMHESSIAAW,	"evmhessiaaw",	MISC,	spe_evmhessiaaw)
+BU_SPE_2 (EVMHESSIANW,	"evmhessianw",	MISC,	spe_evmhessianw)
+BU_SPE_2 (EVMHEUMI,	"evmheumi",	MISC,	spe_evmheumi)
+BU_SPE_2 (EVMHEUMIA,	"evmheumia",	MISC,	spe_evmheumia)
+BU_SPE_2 (EVMHEUMIAAW,	"evmheumiaaw",	MISC,	spe_evmheumiaaw)
+BU_SPE_2 (EVMHEUMIANW,	"evmheumianw",	MISC,	spe_evmheumianw)
+BU_SPE_2 (EVMHEUSIAAW,	"evmheusiaaw",	MISC,	spe_evmheusiaaw)
+BU_SPE_2 (EVMHEUSIANW,	"evmheusianw",	MISC,	spe_evmheusianw)
+BU_SPE_2 (EVMHOGSMFAA,	"evmhogsmfaa",	MISC,	spe_evmhogsmfaa)
+BU_SPE_2 (EVMHOGSMFAN,	"evmhogsmfan",	MISC,	spe_evmhogsmfan)
+BU_SPE_2 (EVMHOGSMIAA,	"evmhogsmiaa",	MISC,	spe_evmhogsmiaa)
+BU_SPE_2 (EVMHOGSMIAN,	"evmhogsmian",	MISC,	spe_evmhogsmian)
+BU_SPE_2 (EVMHOGUMIAA,	"evmhogumiaa",	MISC,	spe_evmhogumiaa)
+BU_SPE_2 (EVMHOGUMIAN,	"evmhogumian",	MISC,	spe_evmhogumian)
+BU_SPE_2 (EVMHOSMF,	"evmhosmf",	MISC,	spe_evmhosmf)
+BU_SPE_2 (EVMHOSMFA,	"evmhosmfa",	MISC,	spe_evmhosmfa)
+BU_SPE_2 (EVMHOSMFAAW,	"evmhosmfaaw",	MISC,	spe_evmhosmfaaw)
+BU_SPE_2 (EVMHOSMFANW,	"evmhosmfanw",	MISC,	spe_evmhosmfanw)
+BU_SPE_2 (EVMHOSMI,	"evmhosmi",	MISC,	spe_evmhosmi)
+BU_SPE_2 (EVMHOSMIA,	"evmhosmia",	MISC,	spe_evmhosmia)
+BU_SPE_2 (EVMHOSMIAAW,	"evmhosmiaaw",	MISC,	spe_evmhosmiaaw)
+BU_SPE_2 (EVMHOSMIANW,	"evmhosmianw",	MISC,	spe_evmhosmianw)
+BU_SPE_2 (EVMHOSSF,	"evmhossf",	MISC,	spe_evmhossf)
+BU_SPE_2 (EVMHOSSFA,	"evmhossfa",	MISC,	spe_evmhossfa)
+BU_SPE_2 (EVMHOSSFAAW,	"evmhossfaaw",	MISC,	spe_evmhossfaaw)
+BU_SPE_2 (EVMHOSSFANW,	"evmhossfanw",	MISC,	spe_evmhossfanw)
+BU_SPE_2 (EVMHOSSIAAW,	"evmhossiaaw",	MISC,	spe_evmhossiaaw)
+BU_SPE_2 (EVMHOSSIANW,	"evmhossianw",	MISC,	spe_evmhossianw)
+BU_SPE_2 (EVMHOUMI,	"evmhoumi",	MISC,	spe_evmhoumi)
+BU_SPE_2 (EVMHOUMIA,	"evmhoumia",	MISC,	spe_evmhoumia)
+BU_SPE_2 (EVMHOUMIAAW,	"evmhoumiaaw",	MISC,	spe_evmhoumiaaw)
+BU_SPE_2 (EVMHOUMIANW,	"evmhoumianw",	MISC,	spe_evmhoumianw)
+BU_SPE_2 (EVMHOUSIAAW,	"evmhousiaaw",	MISC,	spe_evmhousiaaw)
+BU_SPE_2 (EVMHOUSIANW,	"evmhousianw",	MISC,	spe_evmhousianw)
+BU_SPE_2 (EVMWHSMF,	"evmwhsmf",	MISC,	spe_evmwhsmf)
+BU_SPE_2 (EVMWHSMFA,	"evmwhsmfa",	MISC,	spe_evmwhsmfa)
+BU_SPE_2 (EVMWHSMI,	"evmwhsmi",	MISC,	spe_evmwhsmi)
+BU_SPE_2 (EVMWHSMIA,	"evmwhsmia",	MISC,	spe_evmwhsmia)
+BU_SPE_2 (EVMWHSSF,	"evmwhssf",	MISC,	spe_evmwhssf)
+BU_SPE_2 (EVMWHSSFA,	"evmwhssfa",	MISC,	spe_evmwhssfa)
+BU_SPE_2 (EVMWHUMI,	"evmwhumi",	MISC,	spe_evmwhumi)
+BU_SPE_2 (EVMWHUMIA,	"evmwhumia",	MISC,	spe_evmwhumia)
+BU_SPE_2 (EVMWLSMIAAW,	"evmwlsmiaaw",	MISC,	spe_evmwlsmiaaw)
+BU_SPE_2 (EVMWLSMIANW,	"evmwlsmianw",	MISC,	spe_evmwlsmianw)
+BU_SPE_2 (EVMWLSSIAAW,	"evmwlssiaaw",	MISC,	spe_evmwlssiaaw)
+BU_SPE_2 (EVMWLSSIANW,	"evmwlssianw",	MISC,	spe_evmwlssianw)
+BU_SPE_2 (EVMWLUMI,	"evmwlumi",	MISC,	spe_evmwlumi)
+BU_SPE_2 (EVMWLUMIA,	"evmwlumia",	MISC,	spe_evmwlumia)
+BU_SPE_2 (EVMWLUMIAAW,	"evmwlumiaaw",	MISC,	spe_evmwlumiaaw)
+BU_SPE_2 (EVMWLUMIANW,	"evmwlumianw",	MISC,	spe_evmwlumianw)
+BU_SPE_2 (EVMWLUSIAAW,	"evmwlusiaaw",	MISC,	spe_evmwlusiaaw)
+BU_SPE_2 (EVMWLUSIANW,	"evmwlusianw",	MISC,	spe_evmwlusianw)
+BU_SPE_2 (EVMWSMF,	"evmwsmf",	MISC,	spe_evmwsmf)
+BU_SPE_2 (EVMWSMFA,	"evmwsmfa",	MISC,	spe_evmwsmfa)
+BU_SPE_2 (EVMWSMFAA,	"evmwsmfaa",	MISC,	spe_evmwsmfaa)
+BU_SPE_2 (EVMWSMFAN,	"evmwsmfan",	MISC,	spe_evmwsmfan)
+BU_SPE_2 (EVMWSMI,	"evmwsmi",	MISC,	spe_evmwsmi)
+BU_SPE_2 (EVMWSMIA,	"evmwsmia",	MISC,	spe_evmwsmia)
+BU_SPE_2 (EVMWSMIAA,	"evmwsmiaa",	MISC,	spe_evmwsmiaa)
+BU_SPE_2 (EVMWSMIAN,	"evmwsmian",	MISC,	spe_evmwsmian)
+BU_SPE_2 (EVMWSSF,	"evmwssf",	MISC,	spe_evmwssf)
+BU_SPE_2 (EVMWSSFA,	"evmwssfa",	MISC,	spe_evmwssfa)
+BU_SPE_2 (EVMWSSFAA,	"evmwssfaa",	MISC,	spe_evmwssfaa)
+BU_SPE_2 (EVMWSSFAN,	"evmwssfan",	MISC,	spe_evmwssfan)
+BU_SPE_2 (EVMWUMI,	"evmwumi",	MISC,	spe_evmwumi)
+BU_SPE_2 (EVMWUMIA,	"evmwumia",	MISC,	spe_evmwumia)
+BU_SPE_2 (EVMWUMIAA,	"evmwumiaa",	MISC,	spe_evmwumiaa)
+BU_SPE_2 (EVMWUMIAN,	"evmwumian",	MISC,	spe_evmwumian)
+BU_SPE_2 (EVNAND,	"evnand",	MISC,	spe_evnand)
+BU_SPE_2 (EVNOR,	"evnor",	MISC,	spe_evnor)
+BU_SPE_2 (EVOR,		"evor",		MISC,	spe_evor)
+BU_SPE_2 (EVORC,	"evorc",	MISC,	spe_evorc)
+BU_SPE_2 (EVRLW,	"evrlw",	MISC,	spe_evrlw)
+BU_SPE_2 (EVSLW,	"evslw",	MISC,	spe_evslw)
+BU_SPE_2 (EVSRWS,	"evsrws",	MISC,	spe_evsrws)
+BU_SPE_2 (EVSRWU,	"evsrwu",	MISC,	spe_evsrwu)
+BU_SPE_2 (EVSUBFW,	"evsubfw",	MISC,	subv2si3)
+
+/* SPE binary operations expecting a 5-bit unsigned literal.  */
+BU_SPE_2 (EVADDIW,	"evaddiw",	MISC,	spe_evaddiw)
+
+BU_SPE_2 (EVRLWI,	"evrlwi",	MISC,	spe_evrlwi)
+BU_SPE_2 (EVSLWI,	"evslwi",	MISC,	spe_evslwi)
+BU_SPE_2 (EVSRWIS,	"evsrwis",	MISC,	spe_evsrwis)
+BU_SPE_2 (EVSRWIU,	"evsrwiu",	MISC,	spe_evsrwiu)
+BU_SPE_2 (EVSUBIFW,	"evsubifw",	MISC,	spe_evsubifw)
+BU_SPE_2 (EVMWHSSFAA,	"evmwhssfaa",	MISC,	spe_evmwhssfaa)
+BU_SPE_2 (EVMWHSSMAA,	"evmwhssmaa",	MISC,	spe_evmwhssmaa)
+BU_SPE_2 (EVMWHSMFAA,	"evmwhsmfaa",	MISC,	spe_evmwhsmfaa)
+BU_SPE_2 (EVMWHSMIAA,	"evmwhsmiaa",	MISC,	spe_evmwhsmiaa)
+BU_SPE_2 (EVMWHUSIAA,	"evmwhusiaa",	MISC,	spe_evmwhusiaa)
+BU_SPE_2 (EVMWHUMIAA,	"evmwhumiaa",	MISC,	spe_evmwhumiaa)
+BU_SPE_2 (EVMWHSSFAN,	"evmwhssfan",	MISC,	spe_evmwhssfan)
+BU_SPE_2 (EVMWHSSIAN,	"evmwhssian",	MISC,	spe_evmwhssian)
+BU_SPE_2 (EVMWHSMFAN,	"evmwhsmfan",	MISC,	spe_evmwhsmfan)
+BU_SPE_2 (EVMWHSMIAN,	"evmwhsmian",	MISC,	spe_evmwhsmian)
+BU_SPE_2 (EVMWHUSIAN,	"evmwhusian",	MISC,	spe_evmwhusian)
+BU_SPE_2 (EVMWHUMIAN,	"evmwhumian",	MISC,	spe_evmwhumian)
+BU_SPE_2 (EVMWHGSSFAA,	"evmwhgssfaa",	MISC,	spe_evmwhgssfaa)
+BU_SPE_2 (EVMWHGSMFAA,	"evmwhgsmfaa",	MISC,	spe_evmwhgsmfaa)
+BU_SPE_2 (EVMWHGSMIAA,	"evmwhgsmiaa",	MISC,	spe_evmwhgsmiaa)
+BU_SPE_2 (EVMWHGUMIAA,	"evmwhgumiaa",	MISC,	spe_evmwhgumiaa)
+BU_SPE_2 (EVMWHGSSFAN,	"evmwhgssfan",	MISC,	spe_evmwhgssfan)
+BU_SPE_2 (EVMWHGSMFAN,	"evmwhgsmfan",	MISC,	spe_evmwhgsmfan)
+BU_SPE_2 (EVMWHGSMIAN,	"evmwhgsmian",	MISC,	spe_evmwhgsmian)
+BU_SPE_2 (EVMWHGUMIAN,	"evmwhgumian",	MISC,	spe_evmwhgumian)
+BU_SPE_2 (BRINC,	"brinc",	MISC,	spe_brinc)
+BU_SPE_2 (EVXOR,	"evxor",	MISC,	xorv2si3)
+
+/* SPE predicate builtins.  */
+BU_SPE_P (EVCMPEQ,	"evcmpeq",	MISC,	spe_evcmpeq)
+BU_SPE_P (EVCMPGTS,	"evcmpgts",	MISC,	spe_evcmpgts)
+BU_SPE_P (EVCMPGTU,	"evcmpgtu",	MISC,	spe_evcmpgtu)
+BU_SPE_P (EVCMPLTS,	"evcmplts",	MISC,	spe_evcmplts)
+BU_SPE_P (EVCMPLTU,	"evcmpltu",	MISC,	spe_evcmpltu)
+BU_SPE_P (EVFSCMPEQ,	"evfscmpeq",	MISC,	spe_evfscmpeq)
+BU_SPE_P (EVFSCMPGT,	"evfscmpgt",	MISC,	spe_evfscmpgt)
+BU_SPE_P (EVFSCMPLT,	"evfscmplt",	MISC,	spe_evfscmplt)
+BU_SPE_P (EVFSTSTEQ,	"evfststeq",	MISC,	spe_evfststeq)
+BU_SPE_P (EVFSTSTGT,	"evfststgt",	MISC,	spe_evfststgt)
+BU_SPE_P (EVFSTSTLT,	"evfststlt",	MISC,	spe_evfststlt)
+
+/* SPE evsel builtins.  */
+BU_SPE_E (EVSEL_CMPGTS,	 "evsel_gts",	  MISC,	spe_evcmpgts)
+BU_SPE_E (EVSEL_CMPGTU,	 "evsel_gtu",	  MISC,	spe_evcmpgtu)
+BU_SPE_E (EVSEL_CMPLTS,	 "evsel_lts",	  MISC,	spe_evcmplts)
+BU_SPE_E (EVSEL_CMPLTU,	 "evsel_ltu",	  MISC,	spe_evcmpltu)
+BU_SPE_E (EVSEL_CMPEQ,	 "evsel_eq",	  MISC,	spe_evcmpeq)
+BU_SPE_E (EVSEL_FSCMPGT, "evsel_fsgt",	  MISC,	spe_evfscmpgt)
+BU_SPE_E (EVSEL_FSCMPLT, "evsel_fslt",	  MISC,	spe_evfscmplt)
+BU_SPE_E (EVSEL_FSCMPEQ, "evsel_fseq",	  MISC,	spe_evfscmpeq)
+BU_SPE_E (EVSEL_FSTSTGT, "evsel_fststgt", MISC,	spe_evfststgt)
+BU_SPE_E (EVSEL_FSTSTLT, "evsel_fststlt", MISC,	spe_evfststlt)
+BU_SPE_E (EVSEL_FSTSTEQ, "evsel_fststeq", MISC,	spe_evfststeq)
+
+BU_SPE_1 (EVABS,	"evabs",	CONST,	absv2si2)
+BU_SPE_1 (EVADDSMIAAW,	"evaddsmiaaw",	CONST,	spe_evaddsmiaaw)
+BU_SPE_1 (EVADDSSIAAW,	"evaddssiaaw",	CONST,	spe_evaddssiaaw)
+BU_SPE_1 (EVADDUMIAAW,	"evaddumiaaw",	CONST,	spe_evaddumiaaw)
+BU_SPE_1 (EVADDUSIAAW,	"evaddusiaaw",	CONST,	spe_evaddusiaaw)
+BU_SPE_1 (EVCNTLSW,	"evcntlsw",	CONST,	spe_evcntlsw)
+BU_SPE_1 (EVCNTLZW,	"evcntlzw",	CONST,	spe_evcntlzw)
+BU_SPE_1 (EVEXTSB,	"evextsb",	CONST,	spe_evextsb)
+BU_SPE_1 (EVEXTSH,	"evextsh",	CONST,	spe_evextsh)
+BU_SPE_1 (EVFSABS,	"evfsabs",	CONST,	spe_evfsabs)
+BU_SPE_1 (EVFSCFSF,	"evfscfsf",	CONST,	spe_evfscfsf)
+BU_SPE_1 (EVFSCFSI,	"evfscfsi",	CONST,	spe_evfscfsi)
+BU_SPE_1 (EVFSCFUF,	"evfscfuf",	CONST,	spe_evfscfuf)
+BU_SPE_1 (EVFSCFUI,	"evfscfui",	CONST,	spe_evfscfui)
+BU_SPE_1 (EVFSCTSF,	"evfsctsf",	CONST,	spe_evfsctsf)
+BU_SPE_1 (EVFSCTSI,	"evfsctsi",	CONST,	spe_evfsctsi)
+BU_SPE_1 (EVFSCTSIZ,	"evfsctsiz",	CONST,	spe_evfsctsiz)
+BU_SPE_1 (EVFSCTUF,	"evfsctuf",	CONST,	spe_evfsctuf)
+BU_SPE_1 (EVFSCTUI,	"evfsctui",	CONST,	spe_evfsctui)
+BU_SPE_1 (EVFSCTUIZ,	"evfsctuiz",	CONST,	spe_evfsctuiz)
+BU_SPE_1 (EVFSNABS,	"evfsnabs",	CONST,	spe_evfsnabs)
+BU_SPE_1 (EVFSNEG,	"evfsneg",	CONST,	spe_evfsneg)
+BU_SPE_1 (EVMRA,	"evmra",	CONST,	spe_evmra)
+BU_SPE_1 (EVNEG,	"evneg",	CONST,	negv2si2)
+BU_SPE_1 (EVRNDW,	"evrndw",	CONST,	spe_evrndw)
+BU_SPE_1 (EVSUBFSMIAAW,	"evsubfsmiaaw",	CONST,	spe_evsubfsmiaaw)
+BU_SPE_1 (EVSUBFSSIAAW,	"evsubfssiaaw",	CONST,	spe_evsubfssiaaw)
+BU_SPE_1 (EVSUBFUMIAAW,	"evsubfumiaaw",	CONST,	spe_evsubfumiaaw)
+BU_SPE_1 (EVSUBFUSIAAW,	"evsubfusiaaw",	CONST,	spe_evsubfusiaaw)
+
+/* SPE builtins that are handled as special cases.  */
+BU_SPE_X (EVLDD,	      "evldd",		MISC)
+BU_SPE_X (EVLDDX,	      "evlddx",		MISC)
+BU_SPE_X (EVLDH,	      "evldh",		MISC)
+BU_SPE_X (EVLDHX,	      "evldhx",		MISC)
+BU_SPE_X (EVLDW,	      "evldw",		MISC)
+BU_SPE_X (EVLDWX,	      "evldwx",		MISC)
+BU_SPE_X (EVLHHESPLAT,	      "evlhhesplat",	MISC)
+BU_SPE_X (EVLHHESPLATX,	      "evlhhesplatx",	MISC)
+BU_SPE_X (EVLHHOSSPLAT,	      "evlhhossplat",	MISC)
+BU_SPE_X (EVLHHOSSPLATX,      "evlhhossplatx",	MISC)
+BU_SPE_X (EVLHHOUSPLAT,	      "evlhhousplat",	MISC)
+BU_SPE_X (EVLHHOUSPLATX,      "evlhhousplatx",	MISC)
+BU_SPE_X (EVLWHE,	      "evlwhe",		MISC)
+BU_SPE_X (EVLWHEX,	      "evlwhex",	MISC)
+BU_SPE_X (EVLWHOS,	      "evlwhos",	MISC)
+BU_SPE_X (EVLWHOSX,	      "evlwhosx",	MISC)
+BU_SPE_X (EVLWHOU,	      "evlwhou",	MISC)
+BU_SPE_X (EVLWHOUX,	      "evlwhoux",	MISC)
+BU_SPE_X (EVLWHSPLAT,	      "evlwhsplat",	MISC)
+BU_SPE_X (EVLWHSPLATX,	      "evlwhsplatx",	MISC)
+BU_SPE_X (EVLWWSPLAT,	      "evlwwsplat",	MISC)
+BU_SPE_X (EVLWWSPLATX,	      "evlwwsplatx",	MISC)
+BU_SPE_X (EVSPLATFI,	      "evsplatfi",	MISC)
+BU_SPE_X (EVSPLATI,	      "evsplati",	MISC)
+BU_SPE_X (EVSTDD,	      "evstdd",		MISC)
+BU_SPE_X (EVSTDDX,	      "evstddx",	MISC)
+BU_SPE_X (EVSTDH,	      "evstdh",		MISC)
+BU_SPE_X (EVSTDHX,	      "evstdhx",	MISC)
+BU_SPE_X (EVSTDW,	      "evstdw",		MISC)
+BU_SPE_X (EVSTDWX,	      "evstdwx",	MISC)
+BU_SPE_X (EVSTWHE,	      "evstwhe",	MISC)
+BU_SPE_X (EVSTWHEX,	      "evstwhex",	MISC)
+BU_SPE_X (EVSTWHO,	      "evstwho",	MISC)
+BU_SPE_X (EVSTWHOX,	      "evstwhox",	MISC)
+BU_SPE_X (EVSTWWE,	      "evstwwe",	MISC)
+BU_SPE_X (EVSTWWEX,	      "evstwwex",	MISC)
+BU_SPE_X (EVSTWWO,	      "evstwwo",	MISC)
+BU_SPE_X (EVSTWWOX,	      "evstwwox",	MISC)
+BU_SPE_X (MFSPEFSCR,	      "mfspefscr",	MISC)
+BU_SPE_X (MTSPEFSCR,	      "mtspefscr",	MISC)
+
+
 /* Power7 builtins, that aren't VSX instructions.  */
-RS6000_BUILTIN(POWER7_BUILTIN_BPERMD,			RS6000_BTC_CONST)
+BU_SPECIAL_X (POWER7_BUILTIN_BPERMD, "__builtin_bpermd", RS6000_BTM_POPCNTD,
+	      RS6000_BTC_CONST)
 
 /* Miscellaneous builtins.  */
-RS6000_BUILTIN(RS6000_BUILTIN_RECIP,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(RS6000_BUILTIN_RECIPF,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(RS6000_BUILTIN_RSQRTF,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(RS6000_BUILTIN_RSQRT,			RS6000_BTC_FP_PURE)
-RS6000_BUILTIN(RS6000_BUILTIN_BSWAP_HI,			RS6000_BTC_CONST)
+BU_SPECIAL_X (RS6000_BUILTIN_RECIP, "__builtin_recipdiv", RS6000_BTM_FRE,
+	      RS6000_BTC_FP)
+
+BU_SPECIAL_X (RS6000_BUILTIN_RECIPF, "__builtin_recipdivf", RS6000_BTM_FRES,
+	      RS6000_BTC_FP)
+
+BU_SPECIAL_X (RS6000_BUILTIN_RSQRT, "__builtin_rsqrt", RS6000_BTM_FRSQRTE,
+	      RS6000_BTC_FP)
+
+BU_SPECIAL_X (RS6000_BUILTIN_RSQRTF, "__builtin_rsqrtf", RS6000_BTM_FRSQRTES,
+	      RS6000_BTC_FP)
+
+BU_SPECIAL_X (RS6000_BUILTIN_BSWAP_HI, "__builtin_bswap16", RS6000_BTM_POWERPC,
+	      RS6000_BTC_MEM)
 
 /* Darwin CfString builtin.  */
-RS6000_BUILTIN(RS6000_BUILTIN_CFSTRING,			RS6000_BTC_MISC)
+BU_SPECIAL_X (RS6000_BUILTIN_CFSTRING, "__builtin_cfstring", RS6000_BTM_POWERPC,
+	      RS6000_BTC_MISC)
Index: gcc/config/rs6000/rs6000.c
===================================================================
--- gcc/config/rs6000/rs6000.c	(.../trunk)	(revision 181085)
+++ gcc/config/rs6000/rs6000.c	(.../branches/ibm/builtin2)	(revision 181121)
@@ -289,6 +289,11 @@  static struct
 /* 2 argument gen function typedef.  */
 typedef rtx (*gen_2arg_fn_t) (rtx, rtx, rtx);
 
+/* Pointer to function (in rs6000-c.c) that can define or undefine target
+   macros that have changed.  Languages that don't support the preprocessor
+   don't link in rs6000-c.c, so we can't call it directly.  */
+void (*rs6000_target_modify_macros_ptr) (bool, int, unsigned);
+
 
 /* Target cpu costs.  */
 
@@ -849,18 +854,69 @@  struct processor_costs ppca2_cost = {
 
 
 /* Table that classifies rs6000 builtin functions (pure, const, etc.).  */
-#undef RS6000_BUILTIN
-#undef RS6000_BUILTIN_EQUATE
-#define RS6000_BUILTIN(NAME, TYPE) TYPE,
-#define RS6000_BUILTIN_EQUATE(NAME, VALUE)
+#undef RS6000_BUILTIN_1
+#undef RS6000_BUILTIN_2
+#undef RS6000_BUILTIN_3
+#undef RS6000_BUILTIN_A
+#undef RS6000_BUILTIN_D
+#undef RS6000_BUILTIN_E
+#undef RS6000_BUILTIN_P
+#undef RS6000_BUILTIN_Q
+#undef RS6000_BUILTIN_S
+#undef RS6000_BUILTIN_X
+
+#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
+  { NAME, ICODE, MASK, ATTR },
+
+#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)  \
+  { NAME, ICODE, MASK, ATTR },
+
+#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)  \
+  { NAME, ICODE, MASK, ATTR },
+
+#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)  \
+  { NAME, ICODE, MASK, ATTR },
+
+#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)  \
+  { NAME, ICODE, MASK, ATTR },
+
+#define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)  \
+  { NAME, ICODE, MASK, ATTR },
 
-static const enum rs6000_btc builtin_classify[(int)RS6000_BUILTIN_COUNT] =
+#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)  \
+  { NAME, ICODE, MASK, ATTR },
+
+#define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)  \
+  { NAME, ICODE, MASK, ATTR },
+
+#define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)  \
+  { NAME, ICODE, MASK, ATTR },
+
+#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)  \
+  { NAME, ICODE, MASK, ATTR },
+
+struct rs6000_builtin_info_type {
+  const char *name;
+  const enum insn_code icode;
+  const unsigned mask;
+  const unsigned attr;
+};
+
+static const struct rs6000_builtin_info_type rs6000_builtin_info[] =
 {
 #include "rs6000-builtin.def"
 };
 
-#undef RS6000_BUILTIN
-#undef RS6000_BUILTIN_EQUATE
+#undef RS6000_BUILTIN_1
+#undef RS6000_BUILTIN_2
+#undef RS6000_BUILTIN_3
+#undef RS6000_BUILTIN_A
+#undef RS6000_BUILTIN_D
+#undef RS6000_BUILTIN_E
+#undef RS6000_BUILTIN_P
+#undef RS6000_BUILTIN_Q
+#undef RS6000_BUILTIN_S
+#undef RS6000_BUILTIN_X
 
 /* Support for -mveclibabi=<xxx> to control which vector library to use.  */
 static tree (*rs6000_veclib_handler) (tree, tree, tree);
@@ -994,7 +1050,7 @@  static int rs6000_builtin_vectorization_
                                               tree, int);
 static enum machine_mode rs6000_preferred_simd_mode (enum machine_mode);
 
-static void def_builtin (int, const char *, tree, int);
+static void def_builtin (const char *, tree, enum rs6000_builtins);
 static bool rs6000_vector_alignment_reachable (const_tree, bool);
 static void rs6000_init_builtins (void);
 static tree rs6000_builtin_decl (unsigned, bool);
@@ -1018,9 +1074,6 @@  static rtx paired_expand_lv_builtin (enu
 static rtx paired_expand_stv_builtin (enum insn_code, tree);
 static rtx paired_expand_predicate_builtin (enum insn_code, tree, rtx);
 
-static void enable_mask_for_builtins (struct builtin_description *, int,
-				      enum rs6000_builtins,
-				      enum rs6000_builtins);
 static void spe_init_builtins (void);
 static rtx spe_expand_builtin (tree, rtx, bool *);
 static rtx spe_expand_stv_builtin (enum insn_code, tree);
@@ -1876,6 +1929,7 @@  rs6000_debug_reg_print (int first_regno,
 }
 
 #define DEBUG_FMT_D "%-32s= %d\n"
+#define DEBUG_FMT_X "%-32s= 0x%x\n"
 #define DEBUG_FMT_S "%-32s= %s\n"
 
 /* Print various interesting information with -mdebug=reg.  */
@@ -2103,6 +2157,11 @@  rs6000_debug_reg_global (void)
 	   rs6000_long_double_type_size);
   fprintf (stderr, DEBUG_FMT_D, "sched_restricted_insns_priority",
 	   (int)rs6000_sched_restricted_insns_priority);
+  fprintf (stderr, DEBUG_FMT_D, "Number of standard builtins",
+	   (int)END_BUILTINS);
+  fprintf (stderr, DEBUG_FMT_D, "Number of rs6000 builtins",
+	   (int)RS6000_BUILTIN_COUNT);
+  fprintf (stderr, DEBUG_FMT_X, "Builtin mask", rs6000_builtin_mask);
 }
 
 /* Initialize the various global tables that are based on register size.  */
@@ -2493,6 +2552,27 @@  darwin_rs6000_override_options (void)
 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
 #endif
 
+/* Return the builtin mask of the various options used that could affect which
+   builtins were used.  In the past we used target_flags, but we've run out of
+   bits, and some options like SPE and PAIRED are no longer in
+   target_flags.  */
+
+unsigned
+rs6000_builtin_mask_calculate (void)
+{
+  return (((TARGET_ALTIVEC)		    ? RS6000_BTM_ALTIVEC  : 0)
+	  | ((TARGET_VSX)		    ? RS6000_BTM_VSX	  : 0)
+	  | ((TARGET_SPE)		    ? RS6000_BTM_SPE	  : 0)
+	  | ((TARGET_PAIRED_FLOAT)	    ? RS6000_BTM_PAIRED	  : 0)
+	  | ((TARGET_FRE)		    ? RS6000_BTM_FRE	  : 0)
+	  | ((TARGET_FRES)		    ? RS6000_BTM_FRES	  : 0)
+	  | ((TARGET_FRSQRTE)		    ? RS6000_BTM_FRSQRTE  : 0)
+	  | ((TARGET_FRSQRTES)		    ? RS6000_BTM_FRSQRTES : 0)
+	  | ((TARGET_POPCNTD)		    ? RS6000_BTM_POPCNTD  : 0)
+	  | ((TARGET_POWERPC)		    ? RS6000_BTM_POWERPC  : 0)
+	  | ((rs6000_cpu == PROCESSOR_CELL) ? RS6000_BTM_CELL     : 0));
+}
+
 /* Override command line options.  Mostly we process the processor type and
    sometimes adjust other TARGET_ options.  */
 
@@ -3232,6 +3312,19 @@  rs6000_option_override_internal (bool gl
 	}
     }
 
+  /* Set the builtin mask of the various options used that could affect which
+     builtins were used.  In the past we used target_flags, but we've run out
+     of bits, and some options like SPE and PAIRED are no longer in
+     target_flags.  */
+  rs6000_builtin_mask = rs6000_builtin_mask_calculate ();
+  if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
+    fprintf (stderr, "new builtin mask = 0x%x%s%s%s%s\n", rs6000_builtin_mask,
+	     (rs6000_builtin_mask & RS6000_BTM_ALTIVEC) ? ", altivec" : "",
+	     (rs6000_builtin_mask & RS6000_BTM_VSX)     ? ", vsx"     : "",
+	     (rs6000_builtin_mask & RS6000_BTM_PAIRED)  ? ", paired"  : "",
+	     (rs6000_builtin_mask & RS6000_BTM_SPE)     ? ", spe" : "");
+
+  /* Initialize all of the registers.  */
   rs6000_init_hard_regno_mode_ok (global_init_p);
 
   /* Save the initial options in case the user does function specific options */
@@ -3327,8 +3420,8 @@  rs6000_builtin_conversion (unsigned int 
 	    return NULL_TREE;
 
 	  return TYPE_UNSIGNED (dest_type)
-	    ? rs6000_builtin_decls[VECTOR_BUILTIN_FIXUNS_V4SF_V4SI]
-	    : rs6000_builtin_decls[VECTOR_BUILTIN_FIX_V4SF_V4SI];
+	    ? rs6000_builtin_decls[ALTIVEC_BUILTIN_FIXUNS_V4SF_V4SI]
+	    : rs6000_builtin_decls[ALTIVEC_BUILTIN_FIX_V4SF_V4SI];
 
 	default:
 	  return NULL_TREE;
@@ -3350,8 +3443,8 @@  rs6000_builtin_conversion (unsigned int 
 	    return NULL_TREE;
 
 	  return TYPE_UNSIGNED (src_type)
-	    ? rs6000_builtin_decls[VECTOR_BUILTIN_UNSFLOAT_V4SI_V4SF]
-	    : rs6000_builtin_decls[VECTOR_BUILTIN_FLOAT_V4SI_V4SF];
+	    ? rs6000_builtin_decls[ALTIVEC_BUILTIN_UNSFLOAT_V4SI_V4SF]
+	    : rs6000_builtin_decls[ALTIVEC_BUILTIN_FLOAT_V4SI_V4SF];
 
 	default:
 	  return NULL_TREE;
@@ -3917,7 +4010,7 @@  rs6000_builtin_vectorized_function (tree
 	  if (VECTOR_UNIT_VSX_P (V2DFmode)
 	      && out_mode == DFmode && out_n == 2
 	      && in_mode == DFmode && in_n == 2)
-	    return rs6000_builtin_decls[VSX_BUILTIN_VEC_RSQRT_V2DF];
+	    return rs6000_builtin_decls[VSX_BUILTIN_RSQRT_2DF];
 	  break;
 	case RS6000_BUILTIN_RECIPF:
 	  if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
@@ -9357,931 +9450,361 @@  rs6000_gimplify_va_arg (tree valist, tre
 /* Builtins.  */
 
 static void
-def_builtin (int mask, const char *name, tree type, int code)
+def_builtin (const char *name, tree type, enum rs6000_builtins code)
 {
-  if ((mask & target_flags) || TARGET_PAIRED_FLOAT)
-    {
-      tree t;
-      if (rs6000_builtin_decls[code])
-	fatal_error ("internal error: builtin function to %s already processed",
-		     name);
-
-      rs6000_builtin_decls[code] = t =
-        add_builtin_function (name, type, code, BUILT_IN_MD,
-			      NULL, NULL_TREE);
+  tree t;
+  unsigned classify = rs6000_builtin_info[(int)code].mask;
+  const char *attr_string = "";
 
-      gcc_assert (code >= 0 && code < (int)RS6000_BUILTIN_COUNT);
-      switch (builtin_classify[code])
-	{
-	default:
-	  gcc_unreachable ();
+  gcc_assert (name != NULL);
+  gcc_assert (IN_RANGE ((int)code, 0, (int)RS6000_BUILTIN_COUNT));
 
-	  /* assume builtin can do anything.  */
-	case RS6000_BTC_MISC:
-	  break;
+  if (rs6000_builtin_decls[(int)code])
+    fatal_error ("internal error: builtin function %s already processed", name);
 
-	  /* const function, function only depends on the inputs.  */
-	case RS6000_BTC_CONST:
-	  TREE_READONLY (t) = 1;
-	  TREE_NOTHROW (t) = 1;
-	  break;
-
-	  /* pure function, function can read global memory.  */
-	case RS6000_BTC_PURE:
+  rs6000_builtin_decls[(int)code] = t =
+    add_builtin_function (name, type, (int)code, BUILT_IN_MD, NULL, NULL_TREE);
+
+  /* Set any special attributes.  */
+  if ((classify & RS6000_BTC_CONST) != 0)
+    {
+      /* const function, function only depends on the inputs.  */
+      TREE_READONLY (t) = 1;
+      TREE_NOTHROW (t) = 1;
+      attr_string = ", pure";
+    }
+  else if ((classify & RS6000_BTC_PURE) != 0)
+    {
+      /* pure function, function can read global memory, but does not set any
+	 external state.  */
+      DECL_PURE_P (t) = 1;
+      TREE_NOTHROW (t) = 1;
+      attr_string = ", const";
+    }
+  else if ((classify & RS6000_BTC_FP) != 0)
+    {
+      /* Function is a math function.  If rounding mode is on, then treat the
+	 function as not reading global memory, but it can have arbitrary side
+	 effects.  If it is off, then assume the function is a const function.
+	 This mimics the ATTR_MATHFN_FPROUNDING attribute in
+	 builtin-attribute.def that is used for the math functions. */
+      TREE_NOTHROW (t) = 1;
+      if (flag_rounding_math)
+	{
 	  DECL_PURE_P (t) = 1;
-	  TREE_NOTHROW (t) = 1;
-	  break;
-
-	  /* Function is a math function.  If rounding mode is on, then treat
-	     the function as not reading global memory, but it can have
-	     arbitrary side effects.  If it is off, then assume the function is
-	     a const function.  This mimics the ATTR_MATHFN_FPROUNDING
-	     attribute in builtin-attribute.def that is used for the math
-	     functions. */
-	case RS6000_BTC_FP_PURE:
-	  TREE_NOTHROW (t) = 1;
-	  if (flag_rounding_math)
-	    {
-	      DECL_PURE_P (t) = 1;
-	      DECL_IS_NOVOPS (t) = 1;
-	    }
-	  else
-	    TREE_READONLY (t) = 1;
-	  break;
+	  DECL_IS_NOVOPS (t) = 1;
+	  attr_string = ", fp, pure";
+	}
+      else
+	{
+	  TREE_READONLY (t) = 1;
+	  attr_string = ", fp, const";
 	}
     }
+  else if ((classify & RS6000_BTC_ATTR_MASK) != 0)
+    gcc_unreachable ();
+
+  if (TARGET_DEBUG_BUILTIN)
+    fprintf (stderr, "rs6000_builtin, code = %4d, %s%s\n",
+	     (int)code, name, attr_string);
 }
 
 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc).  */
 
+#undef RS6000_BUILTIN_1
+#undef RS6000_BUILTIN_2
+#undef RS6000_BUILTIN_3
+#undef RS6000_BUILTIN_A
+#undef RS6000_BUILTIN_D
+#undef RS6000_BUILTIN_E
+#undef RS6000_BUILTIN_P
+#undef RS6000_BUILTIN_Q
+#undef RS6000_BUILTIN_S
+#undef RS6000_BUILTIN_X
+
+#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
+#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
+#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
+  { MASK, ICODE, NAME, ENUM },
+
+#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
+#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
+#define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
+#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
+#define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
+#define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
+#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
+
 static const struct builtin_description bdesc_3arg[] =
 {
-  { MASK_ALTIVEC, CODE_FOR_fmav4sf4, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vmhaddshs, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vmhraddshs, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vmladduhm, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM},
-  { MASK_ALTIVEC, CODE_FOR_altivec_vmsumubm, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vmsummbm, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhm, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshm, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhs, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshs, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS },
-  { MASK_ALTIVEC, CODE_FOR_nfmsv4sf4, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v2df, "__builtin_altivec_vperm_2df", ALTIVEC_BUILTIN_VPERM_2DF },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v2di, "__builtin_altivec_vperm_2di", ALTIVEC_BUILTIN_VPERM_2DI },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4sf, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4si, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v8hi, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v16qi_uns, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v2di_uns, "__builtin_altivec_vperm_2di_uns", ALTIVEC_BUILTIN_VPERM_2DI_UNS },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4si_uns, "__builtin_altivec_vperm_4si_uns", ALTIVEC_BUILTIN_VPERM_4SI_UNS },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v8hi_uns, "__builtin_altivec_vperm_8hi_uns", ALTIVEC_BUILTIN_VPERM_8HI_UNS },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v16qi_uns, "__builtin_altivec_vperm_16qi_uns", ALTIVEC_BUILTIN_VPERM_16QI_UNS },
-  { MASK_ALTIVEC, CODE_FOR_vector_select_v4sf, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF },
-  { MASK_ALTIVEC, CODE_FOR_vector_select_v4si, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI },
-  { MASK_ALTIVEC, CODE_FOR_vector_select_v8hi, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI },
-  { MASK_ALTIVEC, CODE_FOR_vector_select_v16qi, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI },
-  { MASK_ALTIVEC, CODE_FOR_vector_select_v2df, "__builtin_altivec_vsel_2df", ALTIVEC_BUILTIN_VSEL_2DF },
-  { MASK_ALTIVEC, CODE_FOR_vector_select_v2di, "__builtin_altivec_vsel_2di", ALTIVEC_BUILTIN_VSEL_2DI },
-  { MASK_ALTIVEC, CODE_FOR_vector_select_v4si_uns, "__builtin_altivec_vsel_4si_uns", ALTIVEC_BUILTIN_VSEL_4SI_UNS },
-  { MASK_ALTIVEC, CODE_FOR_vector_select_v8hi_uns, "__builtin_altivec_vsel_8hi_uns", ALTIVEC_BUILTIN_VSEL_8HI_UNS },
-  { MASK_ALTIVEC, CODE_FOR_vector_select_v16qi_uns, "__builtin_altivec_vsel_16qi_uns", ALTIVEC_BUILTIN_VSEL_16QI_UNS },
-  { MASK_ALTIVEC, CODE_FOR_vector_select_v2di_uns, "__builtin_altivec_vsel_2di_uns", ALTIVEC_BUILTIN_VSEL_2DI_UNS },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v16qi, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v8hi, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4si, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4sf, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF },
-
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_madd", ALTIVEC_BUILTIN_VEC_MADD },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_madds", ALTIVEC_BUILTIN_VEC_MADDS },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mladd", ALTIVEC_BUILTIN_VEC_MLADD },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mradds", ALTIVEC_BUILTIN_VEC_MRADDS },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_msum", ALTIVEC_BUILTIN_VEC_MSUM },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumshm", ALTIVEC_BUILTIN_VEC_VMSUMSHM },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumuhm", ALTIVEC_BUILTIN_VEC_VMSUMUHM },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsummbm", ALTIVEC_BUILTIN_VEC_VMSUMMBM },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumubm", ALTIVEC_BUILTIN_VEC_VMSUMUBM },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_msums", ALTIVEC_BUILTIN_VEC_MSUMS },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumshs", ALTIVEC_BUILTIN_VEC_VMSUMSHS },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumuhs", ALTIVEC_BUILTIN_VEC_VMSUMUHS },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_nmsub", ALTIVEC_BUILTIN_VEC_NMSUB },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_perm", ALTIVEC_BUILTIN_VEC_PERM },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sel", ALTIVEC_BUILTIN_VEC_SEL },
-
-  { MASK_VSX, CODE_FOR_fmav2df4, "__builtin_vsx_xvmadddp", VSX_BUILTIN_XVMADDDP },
-  { MASK_VSX, CODE_FOR_fmsv2df4, "__builtin_vsx_xvmsubdp", VSX_BUILTIN_XVMSUBDP },
-  { MASK_VSX, CODE_FOR_nfmav2df4, "__builtin_vsx_xvnmadddp", VSX_BUILTIN_XVNMADDDP },
-  { MASK_VSX, CODE_FOR_nfmsv2df4, "__builtin_vsx_xvnmsubdp", VSX_BUILTIN_XVNMSUBDP },
-
-  { MASK_VSX, CODE_FOR_fmav4sf4, "__builtin_vsx_xvmaddsp", VSX_BUILTIN_XVMADDSP },
-  { MASK_VSX, CODE_FOR_fmsv4sf4, "__builtin_vsx_xvmsubsp", VSX_BUILTIN_XVMSUBSP },
-  { MASK_VSX, CODE_FOR_nfmav4sf4, "__builtin_vsx_xvnmaddsp", VSX_BUILTIN_XVNMADDSP },
-  { MASK_VSX, CODE_FOR_nfmsv4sf4, "__builtin_vsx_xvnmsubsp", VSX_BUILTIN_XVNMSUBSP },
-
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_msub", VSX_BUILTIN_VEC_MSUB },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_nmadd", VSX_BUILTIN_VEC_NMADD },
-
-  { MASK_VSX, CODE_FOR_vector_select_v2di, "__builtin_vsx_xxsel_2di", VSX_BUILTIN_XXSEL_2DI },
-  { MASK_VSX, CODE_FOR_vector_select_v2df, "__builtin_vsx_xxsel_2df", VSX_BUILTIN_XXSEL_2DF },
-  { MASK_VSX, CODE_FOR_vector_select_v4sf, "__builtin_vsx_xxsel_4sf", VSX_BUILTIN_XXSEL_4SF },
-  { MASK_VSX, CODE_FOR_vector_select_v4si, "__builtin_vsx_xxsel_4si", VSX_BUILTIN_XXSEL_4SI },
-  { MASK_VSX, CODE_FOR_vector_select_v8hi, "__builtin_vsx_xxsel_8hi", VSX_BUILTIN_XXSEL_8HI },
-  { MASK_VSX, CODE_FOR_vector_select_v16qi, "__builtin_vsx_xxsel_16qi", VSX_BUILTIN_XXSEL_16QI },
-  { MASK_VSX, CODE_FOR_vector_select_v2di_uns, "__builtin_vsx_xxsel_2di_uns", VSX_BUILTIN_XXSEL_2DI_UNS },
-  { MASK_VSX, CODE_FOR_vector_select_v4si_uns, "__builtin_vsx_xxsel_4si_uns", VSX_BUILTIN_XXSEL_4SI_UNS },
-  { MASK_VSX, CODE_FOR_vector_select_v8hi_uns, "__builtin_vsx_xxsel_8hi_uns", VSX_BUILTIN_XXSEL_8HI_UNS },
-  { MASK_VSX, CODE_FOR_vector_select_v16qi_uns, "__builtin_vsx_xxsel_16qi_uns", VSX_BUILTIN_XXSEL_16QI_UNS },
-
-  { MASK_VSX, CODE_FOR_altivec_vperm_v2di, "__builtin_vsx_vperm_2di", VSX_BUILTIN_VPERM_2DI },
-  { MASK_VSX, CODE_FOR_altivec_vperm_v2df, "__builtin_vsx_vperm_2df", VSX_BUILTIN_VPERM_2DF },
-  { MASK_VSX, CODE_FOR_altivec_vperm_v4sf, "__builtin_vsx_vperm_4sf", VSX_BUILTIN_VPERM_4SF },
-  { MASK_VSX, CODE_FOR_altivec_vperm_v4si, "__builtin_vsx_vperm_4si", VSX_BUILTIN_VPERM_4SI },
-  { MASK_VSX, CODE_FOR_altivec_vperm_v8hi, "__builtin_vsx_vperm_8hi", VSX_BUILTIN_VPERM_8HI },
-  { MASK_VSX, CODE_FOR_altivec_vperm_v16qi, "__builtin_vsx_vperm_16qi", VSX_BUILTIN_VPERM_16QI },
-  { MASK_VSX, CODE_FOR_altivec_vperm_v2di_uns, "__builtin_vsx_vperm_2di_uns", VSX_BUILTIN_VPERM_2DI_UNS },
-  { MASK_VSX, CODE_FOR_altivec_vperm_v4si_uns, "__builtin_vsx_vperm_4si_uns", VSX_BUILTIN_VPERM_4SI_UNS },
-  { MASK_VSX, CODE_FOR_altivec_vperm_v8hi_uns, "__builtin_vsx_vperm_8hi_uns", VSX_BUILTIN_VPERM_8HI_UNS },
-  { MASK_VSX, CODE_FOR_altivec_vperm_v16qi_uns, "__builtin_vsx_vperm_16qi_uns", VSX_BUILTIN_VPERM_16QI_UNS },
-
-  { MASK_VSX, CODE_FOR_vsx_xxpermdi_v2df, "__builtin_vsx_xxpermdi_2df", VSX_BUILTIN_XXPERMDI_2DF },
-  { MASK_VSX, CODE_FOR_vsx_xxpermdi_v2di, "__builtin_vsx_xxpermdi_2di", VSX_BUILTIN_XXPERMDI_2DI },
-  { MASK_VSX, CODE_FOR_vsx_xxpermdi_v4sf, "__builtin_vsx_xxpermdi_4sf", VSX_BUILTIN_XXPERMDI_4SF },
-  { MASK_VSX, CODE_FOR_vsx_xxpermdi_v4si, "__builtin_vsx_xxpermdi_4si", VSX_BUILTIN_XXPERMDI_4SI },
-  { MASK_VSX, CODE_FOR_vsx_xxpermdi_v8hi, "__builtin_vsx_xxpermdi_8hi", VSX_BUILTIN_XXPERMDI_8HI },
-  { MASK_VSX, CODE_FOR_vsx_xxpermdi_v16qi, "__builtin_vsx_xxpermdi_16qi", VSX_BUILTIN_XXPERMDI_16QI },
-  { MASK_VSX, CODE_FOR_nothing, "__builtin_vsx_xxpermdi", VSX_BUILTIN_VEC_XXPERMDI },
-  { MASK_VSX, CODE_FOR_vsx_set_v2df, "__builtin_vsx_set_2df", VSX_BUILTIN_SET_2DF },
-  { MASK_VSX, CODE_FOR_vsx_set_v2di, "__builtin_vsx_set_2di", VSX_BUILTIN_SET_2DI },
-
-  { MASK_VSX, CODE_FOR_vsx_xxsldwi_v2di, "__builtin_vsx_xxsldwi_2di", VSX_BUILTIN_XXSLDWI_2DI },
-  { MASK_VSX, CODE_FOR_vsx_xxsldwi_v2df, "__builtin_vsx_xxsldwi_2df", VSX_BUILTIN_XXSLDWI_2DF },
-  { MASK_VSX, CODE_FOR_vsx_xxsldwi_v4sf, "__builtin_vsx_xxsldwi_4sf", VSX_BUILTIN_XXSLDWI_4SF },
-  { MASK_VSX, CODE_FOR_vsx_xxsldwi_v4si, "__builtin_vsx_xxsldwi_4si", VSX_BUILTIN_XXSLDWI_4SI },
-  { MASK_VSX, CODE_FOR_vsx_xxsldwi_v8hi, "__builtin_vsx_xxsldwi_8hi", VSX_BUILTIN_XXSLDWI_8HI },
-  { MASK_VSX, CODE_FOR_vsx_xxsldwi_v16qi, "__builtin_vsx_xxsldwi_16qi", VSX_BUILTIN_XXSLDWI_16QI },
-  { MASK_VSX, CODE_FOR_nothing, "__builtin_vsx_xxsldwi", VSX_BUILTIN_VEC_XXSLDWI },
-
-  { 0, CODE_FOR_fmsv2sf4, "__builtin_paired_msub", PAIRED_BUILTIN_MSUB },
-  { 0, CODE_FOR_fmav2sf4, "__builtin_paired_madd", PAIRED_BUILTIN_MADD },
-  { 0, CODE_FOR_paired_madds0, "__builtin_paired_madds0", PAIRED_BUILTIN_MADDS0 },
-  { 0, CODE_FOR_paired_madds1, "__builtin_paired_madds1", PAIRED_BUILTIN_MADDS1 },
-  { 0, CODE_FOR_nfmsv2sf4, "__builtin_paired_nmsub", PAIRED_BUILTIN_NMSUB },
-  { 0, CODE_FOR_nfmav2sf4, "__builtin_paired_nmadd", PAIRED_BUILTIN_NMADD },
-  { 0, CODE_FOR_paired_sum0, "__builtin_paired_sum0", PAIRED_BUILTIN_SUM0 },
-  { 0, CODE_FOR_paired_sum1, "__builtin_paired_sum1", PAIRED_BUILTIN_SUM1 },
-  { 0, CODE_FOR_selv2sf4, "__builtin_paired_selv2sf4", PAIRED_BUILTIN_SELV2SF4 },
+#include "rs6000-builtin.def"
 };
 
 /* DST operations: void foo (void *, const int, const char).  */
 
+#undef RS6000_BUILTIN_1
+#undef RS6000_BUILTIN_2
+#undef RS6000_BUILTIN_3
+#undef RS6000_BUILTIN_A
+#undef RS6000_BUILTIN_D
+#undef RS6000_BUILTIN_E
+#undef RS6000_BUILTIN_P
+#undef RS6000_BUILTIN_Q
+#undef RS6000_BUILTIN_S
+#undef RS6000_BUILTIN_X
+
+#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
+#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
+#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
+#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
+#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
+  { MASK, ICODE, NAME, ENUM },
+
+#define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
+#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
+#define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
+#define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
+#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
+
 static const struct builtin_description bdesc_dst[] =
 {
-  { MASK_ALTIVEC, CODE_FOR_altivec_dst, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST },
-  { MASK_ALTIVEC, CODE_FOR_altivec_dstt, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT },
-  { MASK_ALTIVEC, CODE_FOR_altivec_dstst, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST },
-  { MASK_ALTIVEC, CODE_FOR_altivec_dststt, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT },
-
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dst", ALTIVEC_BUILTIN_VEC_DST },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dstt", ALTIVEC_BUILTIN_VEC_DSTT },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dstst", ALTIVEC_BUILTIN_VEC_DSTST },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dststt", ALTIVEC_BUILTIN_VEC_DSTSTT }
+#include "rs6000-builtin.def"
 };
 
 /* Simple binary operations: VECc = foo (VECa, VECb).  */
 
-static struct builtin_description bdesc_2arg[] =
-{
-  { MASK_ALTIVEC, CODE_FOR_addv16qi3, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM },
-  { MASK_ALTIVEC, CODE_FOR_addv8hi3, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM },
-  { MASK_ALTIVEC, CODE_FOR_addv4si3, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM },
-  { MASK_ALTIVEC, CODE_FOR_addv4sf3, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vaddcuw, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vaddubs, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vaddsbs, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vadduhs, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vaddshs, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vadduws, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vaddsws, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS },
-  { MASK_ALTIVEC, CODE_FOR_andv4si3, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND },
-  { MASK_ALTIVEC, CODE_FOR_andcv4si3, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vavgub, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vavgsb, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vavguh, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vavgsh, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vavguw, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vavgsw, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vcfux, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vcfsx, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vcmpbfp, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP },
-  { MASK_ALTIVEC, CODE_FOR_vector_eqv16qi, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB },
-  { MASK_ALTIVEC, CODE_FOR_vector_eqv8hi, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH },
-  { MASK_ALTIVEC, CODE_FOR_vector_eqv4si, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW },
-  { MASK_ALTIVEC, CODE_FOR_vector_eqv4sf, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP },
-  { MASK_ALTIVEC, CODE_FOR_vector_gev4sf, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP },
-  { MASK_ALTIVEC, CODE_FOR_vector_gtuv16qi, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB },
-  { MASK_ALTIVEC, CODE_FOR_vector_gtv16qi, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB },
-  { MASK_ALTIVEC, CODE_FOR_vector_gtuv8hi, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH },
-  { MASK_ALTIVEC, CODE_FOR_vector_gtv8hi, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH },
-  { MASK_ALTIVEC, CODE_FOR_vector_gtuv4si, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW },
-  { MASK_ALTIVEC, CODE_FOR_vector_gtv4si, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW },
-  { MASK_ALTIVEC, CODE_FOR_vector_gtv4sf, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vctsxs, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vctuxs, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS },
-  { MASK_ALTIVEC, CODE_FOR_umaxv16qi3, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB },
-  { MASK_ALTIVEC, CODE_FOR_smaxv16qi3, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB },
-  { MASK_ALTIVEC, CODE_FOR_umaxv8hi3, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH },
-  { MASK_ALTIVEC, CODE_FOR_smaxv8hi3, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH },
-  { MASK_ALTIVEC, CODE_FOR_umaxv4si3, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW },
-  { MASK_ALTIVEC, CODE_FOR_smaxv4si3, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW },
-  { MASK_ALTIVEC, CODE_FOR_smaxv4sf3, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vmrghb, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vmrghh, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vmrghw, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vmrglb, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vmrglh, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vmrglw, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW },
-  { MASK_ALTIVEC, CODE_FOR_uminv16qi3, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB },
-  { MASK_ALTIVEC, CODE_FOR_sminv16qi3, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB },
-  { MASK_ALTIVEC, CODE_FOR_uminv8hi3, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH },
-  { MASK_ALTIVEC, CODE_FOR_sminv8hi3, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH },
-  { MASK_ALTIVEC, CODE_FOR_uminv4si3, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW },
-  { MASK_ALTIVEC, CODE_FOR_sminv4si3, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW },
-  { MASK_ALTIVEC, CODE_FOR_sminv4sf3, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vmuleub, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vmuleub, "__builtin_altivec_vmuleub_uns", ALTIVEC_BUILTIN_VMULEUB_UNS },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vmulesb, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vmuleuh, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vmuleuh, "__builtin_altivec_vmuleuh_uns", ALTIVEC_BUILTIN_VMULEUH_UNS },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vmulesh, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vmuloub, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vmuloub, "__builtin_altivec_vmuloub_uns", ALTIVEC_BUILTIN_VMULOUB_UNS },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vmulosb, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh_uns", ALTIVEC_BUILTIN_VMULOUH_UNS },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vmulosh, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH },
-  { MASK_ALTIVEC, CODE_FOR_norv4si3, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR },
-  { MASK_ALTIVEC, CODE_FOR_iorv4si3, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vpkpx, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vpkshss, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vpkswss, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhus, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vpkshus, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwus, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vpkswus, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS },
-  { MASK_ALTIVEC, CODE_FOR_recipv4sf3, "__builtin_altivec_vrecipdivfp", ALTIVEC_BUILTIN_VRECIPFP },
-  { MASK_ALTIVEC, CODE_FOR_vrotlv16qi3, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB },
-  { MASK_ALTIVEC, CODE_FOR_vrotlv8hi3, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH },
-  { MASK_ALTIVEC, CODE_FOR_vrotlv4si3, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW },
-  { MASK_ALTIVEC, CODE_FOR_vashlv16qi3, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB },
-  { MASK_ALTIVEC, CODE_FOR_vashlv8hi3, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH },
-  { MASK_ALTIVEC, CODE_FOR_vashlv4si3, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vsl, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vslo, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vspltb, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vsplth, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vspltw, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW },
-  { MASK_ALTIVEC, CODE_FOR_vlshrv16qi3, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB },
-  { MASK_ALTIVEC, CODE_FOR_vlshrv8hi3, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH },
-  { MASK_ALTIVEC, CODE_FOR_vlshrv4si3, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW },
-  { MASK_ALTIVEC, CODE_FOR_vashrv16qi3, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB },
-  { MASK_ALTIVEC, CODE_FOR_vashrv8hi3, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH },
-  { MASK_ALTIVEC, CODE_FOR_vashrv4si3, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO },
-  { MASK_ALTIVEC, CODE_FOR_subv16qi3, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM },
-  { MASK_ALTIVEC, CODE_FOR_subv8hi3, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM },
-  { MASK_ALTIVEC, CODE_FOR_subv4si3, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM },
-  { MASK_ALTIVEC, CODE_FOR_subv4sf3, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vsubcuw, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vsububs, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vsubsbs, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vsubuhs, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vsubshs, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vsubuws, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vsubsws, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vsum4ubs, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vsum4sbs, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vsum4shs, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS },
-  { MASK_ALTIVEC, CODE_FOR_xorv4si3, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR },
-  { MASK_ALTIVEC, CODE_FOR_vector_copysignv4sf3, "__builtin_altivec_copysignfp", ALTIVEC_BUILTIN_COPYSIGN_V4SF },
-
-  { MASK_VSX, CODE_FOR_addv2df3, "__builtin_vsx_xvadddp", VSX_BUILTIN_XVADDDP },
-  { MASK_VSX, CODE_FOR_subv2df3, "__builtin_vsx_xvsubdp", VSX_BUILTIN_XVSUBDP },
-  { MASK_VSX, CODE_FOR_mulv2df3, "__builtin_vsx_xvmuldp", VSX_BUILTIN_XVMULDP },
-  { MASK_VSX, CODE_FOR_divv2df3, "__builtin_vsx_xvdivdp", VSX_BUILTIN_XVDIVDP },
-  { MASK_VSX, CODE_FOR_recipv2df3, "__builtin_vsx_xvrecipdivdp", VSX_BUILTIN_RECIP_V2DF },
-  { MASK_VSX, CODE_FOR_sminv2df3, "__builtin_vsx_xvmindp", VSX_BUILTIN_XVMINDP },
-  { MASK_VSX, CODE_FOR_smaxv2df3, "__builtin_vsx_xvmaxdp", VSX_BUILTIN_XVMAXDP },
-  { MASK_VSX, CODE_FOR_vsx_tdivv2df3_fe, "__builtin_vsx_xvtdivdp_fe", VSX_BUILTIN_XVTDIVDP_FE },
-  { MASK_VSX, CODE_FOR_vsx_tdivv2df3_fg, "__builtin_vsx_xvtdivdp_fg", VSX_BUILTIN_XVTDIVDP_FG },
-  { MASK_VSX, CODE_FOR_vector_eqv2df, "__builtin_vsx_xvcmpeqdp", VSX_BUILTIN_XVCMPEQDP },
-  { MASK_VSX, CODE_FOR_vector_gtv2df, "__builtin_vsx_xvcmpgtdp", VSX_BUILTIN_XVCMPGTDP },
-  { MASK_VSX, CODE_FOR_vector_gev2df, "__builtin_vsx_xvcmpgedp", VSX_BUILTIN_XVCMPGEDP },
-
-  { MASK_VSX, CODE_FOR_addv4sf3, "__builtin_vsx_xvaddsp", VSX_BUILTIN_XVADDSP },
-  { MASK_VSX, CODE_FOR_subv4sf3, "__builtin_vsx_xvsubsp", VSX_BUILTIN_XVSUBSP },
-  { MASK_VSX, CODE_FOR_mulv4sf3, "__builtin_vsx_xvmulsp", VSX_BUILTIN_XVMULSP },
-  { MASK_VSX, CODE_FOR_divv4sf3, "__builtin_vsx_xvdivsp", VSX_BUILTIN_XVDIVSP },
-  { MASK_VSX, CODE_FOR_recipv4sf3, "__builtin_vsx_xvrecipdivsp", VSX_BUILTIN_RECIP_V4SF },
-  { MASK_VSX, CODE_FOR_sminv4sf3, "__builtin_vsx_xvminsp", VSX_BUILTIN_XVMINSP },
-  { MASK_VSX, CODE_FOR_smaxv4sf3, "__builtin_vsx_xvmaxsp", VSX_BUILTIN_XVMAXSP },
-  { MASK_VSX, CODE_FOR_vsx_tdivv4sf3_fe, "__builtin_vsx_xvtdivsp_fe", VSX_BUILTIN_XVTDIVSP_FE },
-  { MASK_VSX, CODE_FOR_vsx_tdivv4sf3_fg, "__builtin_vsx_xvtdivsp_fg", VSX_BUILTIN_XVTDIVSP_FG },
-  { MASK_VSX, CODE_FOR_vector_eqv4sf, "__builtin_vsx_xvcmpeqsp", VSX_BUILTIN_XVCMPEQSP },
-  { MASK_VSX, CODE_FOR_vector_gtv4sf, "__builtin_vsx_xvcmpgtsp", VSX_BUILTIN_XVCMPGTSP },
-  { MASK_VSX, CODE_FOR_vector_gev4sf, "__builtin_vsx_xvcmpgesp", VSX_BUILTIN_XVCMPGESP },
-
-  { MASK_VSX, CODE_FOR_smindf3, "__builtin_vsx_xsmindp", VSX_BUILTIN_XSMINDP },
-  { MASK_VSX, CODE_FOR_smaxdf3, "__builtin_vsx_xsmaxdp", VSX_BUILTIN_XSMAXDP },
-  { MASK_VSX, CODE_FOR_vsx_tdivdf3_fe, "__builtin_vsx_xstdivdp_fe", VSX_BUILTIN_XSTDIVDP_FE },
-  { MASK_VSX, CODE_FOR_vsx_tdivdf3_fg, "__builtin_vsx_xstdivdp_fg", VSX_BUILTIN_XSTDIVDP_FG },
-  { MASK_VSX, CODE_FOR_vector_copysignv2df3, "__builtin_vsx_cpsgndp", VSX_BUILTIN_CPSGNDP },
-  { MASK_VSX, CODE_FOR_vector_copysignv4sf3, "__builtin_vsx_cpsgnsp", VSX_BUILTIN_CPSGNSP },
-
-  { MASK_VSX, CODE_FOR_vsx_concat_v2df, "__builtin_vsx_concat_2df", VSX_BUILTIN_CONCAT_2DF },
-  { MASK_VSX, CODE_FOR_vsx_concat_v2di, "__builtin_vsx_concat_2di", VSX_BUILTIN_CONCAT_2DI },
-  { MASK_VSX, CODE_FOR_vsx_splat_v2df, "__builtin_vsx_splat_2df", VSX_BUILTIN_SPLAT_2DF },
-  { MASK_VSX, CODE_FOR_vsx_splat_v2di, "__builtin_vsx_splat_2di", VSX_BUILTIN_SPLAT_2DI },
-  { MASK_VSX, CODE_FOR_vsx_xxmrghw_v4sf, "__builtin_vsx_xxmrghw", VSX_BUILTIN_XXMRGHW_4SF },
-  { MASK_VSX, CODE_FOR_vsx_xxmrghw_v4si, "__builtin_vsx_xxmrghw_4si", VSX_BUILTIN_XXMRGHW_4SI },
-  { MASK_VSX, CODE_FOR_vsx_xxmrglw_v4sf, "__builtin_vsx_xxmrglw", VSX_BUILTIN_XXMRGLW_4SF },
-  { MASK_VSX, CODE_FOR_vsx_xxmrglw_v4si, "__builtin_vsx_xxmrglw_4si", VSX_BUILTIN_XXMRGLW_4SI },
-  { MASK_VSX, CODE_FOR_vec_interleave_lowv2df, "__builtin_vsx_mergel_2df", VSX_BUILTIN_VEC_MERGEL_V2DF },
-  { MASK_VSX, CODE_FOR_vec_interleave_lowv2di, "__builtin_vsx_mergel_2di", VSX_BUILTIN_VEC_MERGEL_V2DI },
-  { MASK_VSX, CODE_FOR_vec_interleave_highv2df, "__builtin_vsx_mergeh_2df", VSX_BUILTIN_VEC_MERGEH_V2DF },
-  { MASK_VSX, CODE_FOR_vec_interleave_highv2di, "__builtin_vsx_mergeh_2di", VSX_BUILTIN_VEC_MERGEH_V2DI },
-
-  { MASK_ALTIVEC|MASK_VSX, CODE_FOR_nothing, "__builtin_vec_add", ALTIVEC_BUILTIN_VEC_ADD },
-  { MASK_ALTIVEC|MASK_VSX, CODE_FOR_nothing, "__builtin_vec_vaddfp", ALTIVEC_BUILTIN_VEC_VADDFP },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduwm", ALTIVEC_BUILTIN_VEC_VADDUWM },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduhm", ALTIVEC_BUILTIN_VEC_VADDUHM },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddubm", ALTIVEC_BUILTIN_VEC_VADDUBM },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_addc", ALTIVEC_BUILTIN_VEC_ADDC },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_adds", ALTIVEC_BUILTIN_VEC_ADDS },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddsws", ALTIVEC_BUILTIN_VEC_VADDSWS },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduws", ALTIVEC_BUILTIN_VEC_VADDUWS },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddshs", ALTIVEC_BUILTIN_VEC_VADDSHS },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduhs", ALTIVEC_BUILTIN_VEC_VADDUHS },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddsbs", ALTIVEC_BUILTIN_VEC_VADDSBS },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddubs", ALTIVEC_BUILTIN_VEC_VADDUBS },
-  { MASK_ALTIVEC|MASK_VSX, CODE_FOR_nothing, "__builtin_vec_and", ALTIVEC_BUILTIN_VEC_AND },
-  { MASK_ALTIVEC|MASK_VSX, CODE_FOR_nothing, "__builtin_vec_andc", ALTIVEC_BUILTIN_VEC_ANDC },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_avg", ALTIVEC_BUILTIN_VEC_AVG },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsw", ALTIVEC_BUILTIN_VEC_VAVGSW },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavguw", ALTIVEC_BUILTIN_VEC_VAVGUW },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsh", ALTIVEC_BUILTIN_VEC_VAVGSH },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavguh", ALTIVEC_BUILTIN_VEC_VAVGUH },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsb", ALTIVEC_BUILTIN_VEC_VAVGSB },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgub", ALTIVEC_BUILTIN_VEC_VAVGUB },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpb", ALTIVEC_BUILTIN_VEC_CMPB },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpeq", ALTIVEC_BUILTIN_VEC_CMPEQ },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpeqfp", ALTIVEC_BUILTIN_VEC_VCMPEQFP },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequw", ALTIVEC_BUILTIN_VEC_VCMPEQUW },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequh", ALTIVEC_BUILTIN_VEC_VCMPEQUH },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequb", ALTIVEC_BUILTIN_VEC_VCMPEQUB },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpge", ALTIVEC_BUILTIN_VEC_CMPGE },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpgt", ALTIVEC_BUILTIN_VEC_CMPGT },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtfp", ALTIVEC_BUILTIN_VEC_VCMPGTFP },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsw", ALTIVEC_BUILTIN_VEC_VCMPGTSW },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtuw", ALTIVEC_BUILTIN_VEC_VCMPGTUW },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsh", ALTIVEC_BUILTIN_VEC_VCMPGTSH },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtuh", ALTIVEC_BUILTIN_VEC_VCMPGTUH },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsb", ALTIVEC_BUILTIN_VEC_VCMPGTSB },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtub", ALTIVEC_BUILTIN_VEC_VCMPGTUB },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmple", ALTIVEC_BUILTIN_VEC_CMPLE },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmplt", ALTIVEC_BUILTIN_VEC_CMPLT },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_copysign", ALTIVEC_BUILTIN_VEC_COPYSIGN },
-  { MASK_ALTIVEC|MASK_VSX, CODE_FOR_nothing, "__builtin_vec_max", ALTIVEC_BUILTIN_VEC_MAX },
-  { MASK_ALTIVEC|MASK_VSX, CODE_FOR_nothing, "__builtin_vec_vmaxfp", ALTIVEC_BUILTIN_VEC_VMAXFP },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsw", ALTIVEC_BUILTIN_VEC_VMAXSW },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxuw", ALTIVEC_BUILTIN_VEC_VMAXUW },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsh", ALTIVEC_BUILTIN_VEC_VMAXSH },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxuh", ALTIVEC_BUILTIN_VEC_VMAXUH },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsb", ALTIVEC_BUILTIN_VEC_VMAXSB },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxub", ALTIVEC_BUILTIN_VEC_VMAXUB },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mergeh", ALTIVEC_BUILTIN_VEC_MERGEH },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghw", ALTIVEC_BUILTIN_VEC_VMRGHW },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghh", ALTIVEC_BUILTIN_VEC_VMRGHH },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghb", ALTIVEC_BUILTIN_VEC_VMRGHB },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mergel", ALTIVEC_BUILTIN_VEC_MERGEL },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglw", ALTIVEC_BUILTIN_VEC_VMRGLW },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglh", ALTIVEC_BUILTIN_VEC_VMRGLH },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglb", ALTIVEC_BUILTIN_VEC_VMRGLB },
-  { MASK_ALTIVEC|MASK_VSX, CODE_FOR_nothing, "__builtin_vec_min", ALTIVEC_BUILTIN_VEC_MIN },
-  { MASK_ALTIVEC|MASK_VSX, CODE_FOR_nothing, "__builtin_vec_vminfp", ALTIVEC_BUILTIN_VEC_VMINFP },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsw", ALTIVEC_BUILTIN_VEC_VMINSW },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminuw", ALTIVEC_BUILTIN_VEC_VMINUW },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsh", ALTIVEC_BUILTIN_VEC_VMINSH },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminuh", ALTIVEC_BUILTIN_VEC_VMINUH },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsb", ALTIVEC_BUILTIN_VEC_VMINSB },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminub", ALTIVEC_BUILTIN_VEC_VMINUB },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mule", ALTIVEC_BUILTIN_VEC_MULE },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuleub", ALTIVEC_BUILTIN_VEC_VMULEUB },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulesb", ALTIVEC_BUILTIN_VEC_VMULESB },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuleuh", ALTIVEC_BUILTIN_VEC_VMULEUH },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulesh", ALTIVEC_BUILTIN_VEC_VMULESH },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mulo", ALTIVEC_BUILTIN_VEC_MULO },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulosh", ALTIVEC_BUILTIN_VEC_VMULOSH },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulouh", ALTIVEC_BUILTIN_VEC_VMULOUH },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulosb", ALTIVEC_BUILTIN_VEC_VMULOSB },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuloub", ALTIVEC_BUILTIN_VEC_VMULOUB },
-  { MASK_ALTIVEC|MASK_VSX, CODE_FOR_nothing, "__builtin_vec_nor", ALTIVEC_BUILTIN_VEC_NOR },
-  { MASK_ALTIVEC|MASK_VSX, CODE_FOR_nothing, "__builtin_vec_or", ALTIVEC_BUILTIN_VEC_OR },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_pack", ALTIVEC_BUILTIN_VEC_PACK },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuwum", ALTIVEC_BUILTIN_VEC_VPKUWUM },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuhum", ALTIVEC_BUILTIN_VEC_VPKUHUM },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packpx", ALTIVEC_BUILTIN_VEC_PACKPX },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packs", ALTIVEC_BUILTIN_VEC_PACKS },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkswss", ALTIVEC_BUILTIN_VEC_VPKSWSS },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuwus", ALTIVEC_BUILTIN_VEC_VPKUWUS },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkshss", ALTIVEC_BUILTIN_VEC_VPKSHSS },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuhus", ALTIVEC_BUILTIN_VEC_VPKUHUS },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packsu", ALTIVEC_BUILTIN_VEC_PACKSU },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkswus", ALTIVEC_BUILTIN_VEC_VPKSWUS },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkshus", ALTIVEC_BUILTIN_VEC_VPKSHUS },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_recipdiv", ALTIVEC_BUILTIN_VEC_RECIP },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_rl", ALTIVEC_BUILTIN_VEC_RL },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlw", ALTIVEC_BUILTIN_VEC_VRLW },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlh", ALTIVEC_BUILTIN_VEC_VRLH },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlb", ALTIVEC_BUILTIN_VEC_VRLB },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sl", ALTIVEC_BUILTIN_VEC_SL },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslw", ALTIVEC_BUILTIN_VEC_VSLW },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslh", ALTIVEC_BUILTIN_VEC_VSLH },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslb", ALTIVEC_BUILTIN_VEC_VSLB },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sll", ALTIVEC_BUILTIN_VEC_SLL },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_slo", ALTIVEC_BUILTIN_VEC_SLO },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sr", ALTIVEC_BUILTIN_VEC_SR },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrw", ALTIVEC_BUILTIN_VEC_VSRW },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrh", ALTIVEC_BUILTIN_VEC_VSRH },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrb", ALTIVEC_BUILTIN_VEC_VSRB },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sra", ALTIVEC_BUILTIN_VEC_SRA },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsraw", ALTIVEC_BUILTIN_VEC_VSRAW },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrah", ALTIVEC_BUILTIN_VEC_VSRAH },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrab", ALTIVEC_BUILTIN_VEC_VSRAB },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_srl", ALTIVEC_BUILTIN_VEC_SRL },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sro", ALTIVEC_BUILTIN_VEC_SRO },
-  { MASK_ALTIVEC|MASK_VSX, CODE_FOR_nothing, "__builtin_vec_sub", ALTIVEC_BUILTIN_VEC_SUB },
-  { MASK_ALTIVEC|MASK_VSX, CODE_FOR_nothing, "__builtin_vec_vsubfp", ALTIVEC_BUILTIN_VEC_VSUBFP },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuwm", ALTIVEC_BUILTIN_VEC_VSUBUWM },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuhm", ALTIVEC_BUILTIN_VEC_VSUBUHM },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsububm", ALTIVEC_BUILTIN_VEC_VSUBUBM },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_subc", ALTIVEC_BUILTIN_VEC_SUBC },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_subs", ALTIVEC_BUILTIN_VEC_SUBS },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubsws", ALTIVEC_BUILTIN_VEC_VSUBSWS },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuws", ALTIVEC_BUILTIN_VEC_VSUBUWS },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubshs", ALTIVEC_BUILTIN_VEC_VSUBSHS },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuhs", ALTIVEC_BUILTIN_VEC_VSUBUHS },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubsbs", ALTIVEC_BUILTIN_VEC_VSUBSBS },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsububs", ALTIVEC_BUILTIN_VEC_VSUBUBS },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sum4s", ALTIVEC_BUILTIN_VEC_SUM4S },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4shs", ALTIVEC_BUILTIN_VEC_VSUM4SHS },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4sbs", ALTIVEC_BUILTIN_VEC_VSUM4SBS },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4ubs", ALTIVEC_BUILTIN_VEC_VSUM4UBS },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sum2s", ALTIVEC_BUILTIN_VEC_SUM2S },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sums", ALTIVEC_BUILTIN_VEC_SUMS },
-  { MASK_ALTIVEC|MASK_VSX, CODE_FOR_nothing, "__builtin_vec_xor", ALTIVEC_BUILTIN_VEC_XOR },
-
-  { MASK_VSX, CODE_FOR_nothing, "__builtin_vec_mul", VSX_BUILTIN_VEC_MUL },
-  { MASK_VSX, CODE_FOR_nothing, "__builtin_vec_div", VSX_BUILTIN_VEC_DIV },
-
-  { 0, CODE_FOR_paired_divv2sf3, "__builtin_paired_divv2sf3", PAIRED_BUILTIN_DIVV2SF3 },
-  { 0, CODE_FOR_paired_addv2sf3, "__builtin_paired_addv2sf3", PAIRED_BUILTIN_ADDV2SF3 },
-  { 0, CODE_FOR_paired_subv2sf3, "__builtin_paired_subv2sf3", PAIRED_BUILTIN_SUBV2SF3 },
-  { 0, CODE_FOR_paired_mulv2sf3, "__builtin_paired_mulv2sf3", PAIRED_BUILTIN_MULV2SF3 },
-  { 0, CODE_FOR_paired_muls0, "__builtin_paired_muls0", PAIRED_BUILTIN_MULS0 },
-  { 0, CODE_FOR_paired_muls1, "__builtin_paired_muls1", PAIRED_BUILTIN_MULS1 },
-  { 0, CODE_FOR_paired_merge00, "__builtin_paired_merge00", PAIRED_BUILTIN_MERGE00 },
-  { 0, CODE_FOR_paired_merge01, "__builtin_paired_merge01", PAIRED_BUILTIN_MERGE01 },
-  { 0, CODE_FOR_paired_merge10, "__builtin_paired_merge10", PAIRED_BUILTIN_MERGE10 },
-  { 0, CODE_FOR_paired_merge11, "__builtin_paired_merge11", PAIRED_BUILTIN_MERGE11 },
-
-  /* Place holder, leave as first spe builtin.  */
-  { 0, CODE_FOR_addv2si3, "__builtin_spe_evaddw", SPE_BUILTIN_EVADDW },
-  { 0, CODE_FOR_andv2si3, "__builtin_spe_evand", SPE_BUILTIN_EVAND },
-  { 0, CODE_FOR_spe_evandc, "__builtin_spe_evandc", SPE_BUILTIN_EVANDC },
-  { 0, CODE_FOR_divv2si3, "__builtin_spe_evdivws", SPE_BUILTIN_EVDIVWS },
-  { 0, CODE_FOR_spe_evdivwu, "__builtin_spe_evdivwu", SPE_BUILTIN_EVDIVWU },
-  { 0, CODE_FOR_spe_eveqv, "__builtin_spe_eveqv", SPE_BUILTIN_EVEQV },
-  { 0, CODE_FOR_spe_evfsadd, "__builtin_spe_evfsadd", SPE_BUILTIN_EVFSADD },
-  { 0, CODE_FOR_spe_evfsdiv, "__builtin_spe_evfsdiv", SPE_BUILTIN_EVFSDIV },
-  { 0, CODE_FOR_spe_evfsmul, "__builtin_spe_evfsmul", SPE_BUILTIN_EVFSMUL },
-  { 0, CODE_FOR_spe_evfssub, "__builtin_spe_evfssub", SPE_BUILTIN_EVFSSUB },
-  { 0, CODE_FOR_spe_evmergehi, "__builtin_spe_evmergehi", SPE_BUILTIN_EVMERGEHI },
-  { 0, CODE_FOR_spe_evmergehilo, "__builtin_spe_evmergehilo", SPE_BUILTIN_EVMERGEHILO },
-  { 0, CODE_FOR_spe_evmergelo, "__builtin_spe_evmergelo", SPE_BUILTIN_EVMERGELO },
-  { 0, CODE_FOR_spe_evmergelohi, "__builtin_spe_evmergelohi", SPE_BUILTIN_EVMERGELOHI },
-  { 0, CODE_FOR_spe_evmhegsmfaa, "__builtin_spe_evmhegsmfaa", SPE_BUILTIN_EVMHEGSMFAA },
-  { 0, CODE_FOR_spe_evmhegsmfan, "__builtin_spe_evmhegsmfan", SPE_BUILTIN_EVMHEGSMFAN },
-  { 0, CODE_FOR_spe_evmhegsmiaa, "__builtin_spe_evmhegsmiaa", SPE_BUILTIN_EVMHEGSMIAA },
-  { 0, CODE_FOR_spe_evmhegsmian, "__builtin_spe_evmhegsmian", SPE_BUILTIN_EVMHEGSMIAN },
-  { 0, CODE_FOR_spe_evmhegumiaa, "__builtin_spe_evmhegumiaa", SPE_BUILTIN_EVMHEGUMIAA },
-  { 0, CODE_FOR_spe_evmhegumian, "__builtin_spe_evmhegumian", SPE_BUILTIN_EVMHEGUMIAN },
-  { 0, CODE_FOR_spe_evmhesmf, "__builtin_spe_evmhesmf", SPE_BUILTIN_EVMHESMF },
-  { 0, CODE_FOR_spe_evmhesmfa, "__builtin_spe_evmhesmfa", SPE_BUILTIN_EVMHESMFA },
-  { 0, CODE_FOR_spe_evmhesmfaaw, "__builtin_spe_evmhesmfaaw", SPE_BUILTIN_EVMHESMFAAW },
-  { 0, CODE_FOR_spe_evmhesmfanw, "__builtin_spe_evmhesmfanw", SPE_BUILTIN_EVMHESMFANW },
-  { 0, CODE_FOR_spe_evmhesmi, "__builtin_spe_evmhesmi", SPE_BUILTIN_EVMHESMI },
-  { 0, CODE_FOR_spe_evmhesmia, "__builtin_spe_evmhesmia", SPE_BUILTIN_EVMHESMIA },
-  { 0, CODE_FOR_spe_evmhesmiaaw, "__builtin_spe_evmhesmiaaw", SPE_BUILTIN_EVMHESMIAAW },
-  { 0, CODE_FOR_spe_evmhesmianw, "__builtin_spe_evmhesmianw", SPE_BUILTIN_EVMHESMIANW },
-  { 0, CODE_FOR_spe_evmhessf, "__builtin_spe_evmhessf", SPE_BUILTIN_EVMHESSF },
-  { 0, CODE_FOR_spe_evmhessfa, "__builtin_spe_evmhessfa", SPE_BUILTIN_EVMHESSFA },
-  { 0, CODE_FOR_spe_evmhessfaaw, "__builtin_spe_evmhessfaaw", SPE_BUILTIN_EVMHESSFAAW },
-  { 0, CODE_FOR_spe_evmhessfanw, "__builtin_spe_evmhessfanw", SPE_BUILTIN_EVMHESSFANW },
-  { 0, CODE_FOR_spe_evmhessiaaw, "__builtin_spe_evmhessiaaw", SPE_BUILTIN_EVMHESSIAAW },
-  { 0, CODE_FOR_spe_evmhessianw, "__builtin_spe_evmhessianw", SPE_BUILTIN_EVMHESSIANW },
-  { 0, CODE_FOR_spe_evmheumi, "__builtin_spe_evmheumi", SPE_BUILTIN_EVMHEUMI },
-  { 0, CODE_FOR_spe_evmheumia, "__builtin_spe_evmheumia", SPE_BUILTIN_EVMHEUMIA },
-  { 0, CODE_FOR_spe_evmheumiaaw, "__builtin_spe_evmheumiaaw", SPE_BUILTIN_EVMHEUMIAAW },
-  { 0, CODE_FOR_spe_evmheumianw, "__builtin_spe_evmheumianw", SPE_BUILTIN_EVMHEUMIANW },
-  { 0, CODE_FOR_spe_evmheusiaaw, "__builtin_spe_evmheusiaaw", SPE_BUILTIN_EVMHEUSIAAW },
-  { 0, CODE_FOR_spe_evmheusianw, "__builtin_spe_evmheusianw", SPE_BUILTIN_EVMHEUSIANW },
-  { 0, CODE_FOR_spe_evmhogsmfaa, "__builtin_spe_evmhogsmfaa", SPE_BUILTIN_EVMHOGSMFAA },
-  { 0, CODE_FOR_spe_evmhogsmfan, "__builtin_spe_evmhogsmfan", SPE_BUILTIN_EVMHOGSMFAN },
-  { 0, CODE_FOR_spe_evmhogsmiaa, "__builtin_spe_evmhogsmiaa", SPE_BUILTIN_EVMHOGSMIAA },
-  { 0, CODE_FOR_spe_evmhogsmian, "__builtin_spe_evmhogsmian", SPE_BUILTIN_EVMHOGSMIAN },
-  { 0, CODE_FOR_spe_evmhogumiaa, "__builtin_spe_evmhogumiaa", SPE_BUILTIN_EVMHOGUMIAA },
-  { 0, CODE_FOR_spe_evmhogumian, "__builtin_spe_evmhogumian", SPE_BUILTIN_EVMHOGUMIAN },
-  { 0, CODE_FOR_spe_evmhosmf, "__builtin_spe_evmhosmf", SPE_BUILTIN_EVMHOSMF },
-  { 0, CODE_FOR_spe_evmhosmfa, "__builtin_spe_evmhosmfa", SPE_BUILTIN_EVMHOSMFA },
-  { 0, CODE_FOR_spe_evmhosmfaaw, "__builtin_spe_evmhosmfaaw", SPE_BUILTIN_EVMHOSMFAAW },
-  { 0, CODE_FOR_spe_evmhosmfanw, "__builtin_spe_evmhosmfanw", SPE_BUILTIN_EVMHOSMFANW },
-  { 0, CODE_FOR_spe_evmhosmi, "__builtin_spe_evmhosmi", SPE_BUILTIN_EVMHOSMI },
-  { 0, CODE_FOR_spe_evmhosmia, "__builtin_spe_evmhosmia", SPE_BUILTIN_EVMHOSMIA },
-  { 0, CODE_FOR_spe_evmhosmiaaw, "__builtin_spe_evmhosmiaaw", SPE_BUILTIN_EVMHOSMIAAW },
-  { 0, CODE_FOR_spe_evmhosmianw, "__builtin_spe_evmhosmianw", SPE_BUILTIN_EVMHOSMIANW },
-  { 0, CODE_FOR_spe_evmhossf, "__builtin_spe_evmhossf", SPE_BUILTIN_EVMHOSSF },
-  { 0, CODE_FOR_spe_evmhossfa, "__builtin_spe_evmhossfa", SPE_BUILTIN_EVMHOSSFA },
-  { 0, CODE_FOR_spe_evmhossfaaw, "__builtin_spe_evmhossfaaw", SPE_BUILTIN_EVMHOSSFAAW },
-  { 0, CODE_FOR_spe_evmhossfanw, "__builtin_spe_evmhossfanw", SPE_BUILTIN_EVMHOSSFANW },
-  { 0, CODE_FOR_spe_evmhossiaaw, "__builtin_spe_evmhossiaaw", SPE_BUILTIN_EVMHOSSIAAW },
-  { 0, CODE_FOR_spe_evmhossianw, "__builtin_spe_evmhossianw", SPE_BUILTIN_EVMHOSSIANW },
-  { 0, CODE_FOR_spe_evmhoumi, "__builtin_spe_evmhoumi", SPE_BUILTIN_EVMHOUMI },
-  { 0, CODE_FOR_spe_evmhoumia, "__builtin_spe_evmhoumia", SPE_BUILTIN_EVMHOUMIA },
-  { 0, CODE_FOR_spe_evmhoumiaaw, "__builtin_spe_evmhoumiaaw", SPE_BUILTIN_EVMHOUMIAAW },
-  { 0, CODE_FOR_spe_evmhoumianw, "__builtin_spe_evmhoumianw", SPE_BUILTIN_EVMHOUMIANW },
-  { 0, CODE_FOR_spe_evmhousiaaw, "__builtin_spe_evmhousiaaw", SPE_BUILTIN_EVMHOUSIAAW },
-  { 0, CODE_FOR_spe_evmhousianw, "__builtin_spe_evmhousianw", SPE_BUILTIN_EVMHOUSIANW },
-  { 0, CODE_FOR_spe_evmwhsmf, "__builtin_spe_evmwhsmf", SPE_BUILTIN_EVMWHSMF },
-  { 0, CODE_FOR_spe_evmwhsmfa, "__builtin_spe_evmwhsmfa", SPE_BUILTIN_EVMWHSMFA },
-  { 0, CODE_FOR_spe_evmwhsmi, "__builtin_spe_evmwhsmi", SPE_BUILTIN_EVMWHSMI },
-  { 0, CODE_FOR_spe_evmwhsmia, "__builtin_spe_evmwhsmia", SPE_BUILTIN_EVMWHSMIA },
-  { 0, CODE_FOR_spe_evmwhssf, "__builtin_spe_evmwhssf", SPE_BUILTIN_EVMWHSSF },
-  { 0, CODE_FOR_spe_evmwhssfa, "__builtin_spe_evmwhssfa", SPE_BUILTIN_EVMWHSSFA },
-  { 0, CODE_FOR_spe_evmwhumi, "__builtin_spe_evmwhumi", SPE_BUILTIN_EVMWHUMI },
-  { 0, CODE_FOR_spe_evmwhumia, "__builtin_spe_evmwhumia", SPE_BUILTIN_EVMWHUMIA },
-  { 0, CODE_FOR_spe_evmwlsmiaaw, "__builtin_spe_evmwlsmiaaw", SPE_BUILTIN_EVMWLSMIAAW },
-  { 0, CODE_FOR_spe_evmwlsmianw, "__builtin_spe_evmwlsmianw", SPE_BUILTIN_EVMWLSMIANW },
-  { 0, CODE_FOR_spe_evmwlssiaaw, "__builtin_spe_evmwlssiaaw", SPE_BUILTIN_EVMWLSSIAAW },
-  { 0, CODE_FOR_spe_evmwlssianw, "__builtin_spe_evmwlssianw", SPE_BUILTIN_EVMWLSSIANW },
-  { 0, CODE_FOR_spe_evmwlumi, "__builtin_spe_evmwlumi", SPE_BUILTIN_EVMWLUMI },
-  { 0, CODE_FOR_spe_evmwlumia, "__builtin_spe_evmwlumia", SPE_BUILTIN_EVMWLUMIA },
-  { 0, CODE_FOR_spe_evmwlumiaaw, "__builtin_spe_evmwlumiaaw", SPE_BUILTIN_EVMWLUMIAAW },
-  { 0, CODE_FOR_spe_evmwlumianw, "__builtin_spe_evmwlumianw", SPE_BUILTIN_EVMWLUMIANW },
-  { 0, CODE_FOR_spe_evmwlusiaaw, "__builtin_spe_evmwlusiaaw", SPE_BUILTIN_EVMWLUSIAAW },
-  { 0, CODE_FOR_spe_evmwlusianw, "__builtin_spe_evmwlusianw", SPE_BUILTIN_EVMWLUSIANW },
-  { 0, CODE_FOR_spe_evmwsmf, "__builtin_spe_evmwsmf", SPE_BUILTIN_EVMWSMF },
-  { 0, CODE_FOR_spe_evmwsmfa, "__builtin_spe_evmwsmfa", SPE_BUILTIN_EVMWSMFA },
-  { 0, CODE_FOR_spe_evmwsmfaa, "__builtin_spe_evmwsmfaa", SPE_BUILTIN_EVMWSMFAA },
-  { 0, CODE_FOR_spe_evmwsmfan, "__builtin_spe_evmwsmfan", SPE_BUILTIN_EVMWSMFAN },
-  { 0, CODE_FOR_spe_evmwsmi, "__builtin_spe_evmwsmi", SPE_BUILTIN_EVMWSMI },
-  { 0, CODE_FOR_spe_evmwsmia, "__builtin_spe_evmwsmia", SPE_BUILTIN_EVMWSMIA },
-  { 0, CODE_FOR_spe_evmwsmiaa, "__builtin_spe_evmwsmiaa", SPE_BUILTIN_EVMWSMIAA },
-  { 0, CODE_FOR_spe_evmwsmian, "__builtin_spe_evmwsmian", SPE_BUILTIN_EVMWSMIAN },
-  { 0, CODE_FOR_spe_evmwssf, "__builtin_spe_evmwssf", SPE_BUILTIN_EVMWSSF },
-  { 0, CODE_FOR_spe_evmwssfa, "__builtin_spe_evmwssfa", SPE_BUILTIN_EVMWSSFA },
-  { 0, CODE_FOR_spe_evmwssfaa, "__builtin_spe_evmwssfaa", SPE_BUILTIN_EVMWSSFAA },
-  { 0, CODE_FOR_spe_evmwssfan, "__builtin_spe_evmwssfan", SPE_BUILTIN_EVMWSSFAN },
-  { 0, CODE_FOR_spe_evmwumi, "__builtin_spe_evmwumi", SPE_BUILTIN_EVMWUMI },
-  { 0, CODE_FOR_spe_evmwumia, "__builtin_spe_evmwumia", SPE_BUILTIN_EVMWUMIA },
-  { 0, CODE_FOR_spe_evmwumiaa, "__builtin_spe_evmwumiaa", SPE_BUILTIN_EVMWUMIAA },
-  { 0, CODE_FOR_spe_evmwumian, "__builtin_spe_evmwumian", SPE_BUILTIN_EVMWUMIAN },
-  { 0, CODE_FOR_spe_evnand, "__builtin_spe_evnand", SPE_BUILTIN_EVNAND },
-  { 0, CODE_FOR_spe_evnor, "__builtin_spe_evnor", SPE_BUILTIN_EVNOR },
-  { 0, CODE_FOR_spe_evor, "__builtin_spe_evor", SPE_BUILTIN_EVOR },
-  { 0, CODE_FOR_spe_evorc, "__builtin_spe_evorc", SPE_BUILTIN_EVORC },
-  { 0, CODE_FOR_spe_evrlw, "__builtin_spe_evrlw", SPE_BUILTIN_EVRLW },
-  { 0, CODE_FOR_spe_evslw, "__builtin_spe_evslw", SPE_BUILTIN_EVSLW },
-  { 0, CODE_FOR_spe_evsrws, "__builtin_spe_evsrws", SPE_BUILTIN_EVSRWS },
-  { 0, CODE_FOR_spe_evsrwu, "__builtin_spe_evsrwu", SPE_BUILTIN_EVSRWU },
-  { 0, CODE_FOR_subv2si3, "__builtin_spe_evsubfw", SPE_BUILTIN_EVSUBFW },
-
-  /* SPE binary operations expecting a 5-bit unsigned literal.  */
-  { 0, CODE_FOR_spe_evaddiw, "__builtin_spe_evaddiw", SPE_BUILTIN_EVADDIW },
-
-  { 0, CODE_FOR_spe_evrlwi, "__builtin_spe_evrlwi", SPE_BUILTIN_EVRLWI },
-  { 0, CODE_FOR_spe_evslwi, "__builtin_spe_evslwi", SPE_BUILTIN_EVSLWI },
-  { 0, CODE_FOR_spe_evsrwis, "__builtin_spe_evsrwis", SPE_BUILTIN_EVSRWIS },
-  { 0, CODE_FOR_spe_evsrwiu, "__builtin_spe_evsrwiu", SPE_BUILTIN_EVSRWIU },
-  { 0, CODE_FOR_spe_evsubifw, "__builtin_spe_evsubifw", SPE_BUILTIN_EVSUBIFW },
-  { 0, CODE_FOR_spe_evmwhssfaa, "__builtin_spe_evmwhssfaa", SPE_BUILTIN_EVMWHSSFAA },
-  { 0, CODE_FOR_spe_evmwhssmaa, "__builtin_spe_evmwhssmaa", SPE_BUILTIN_EVMWHSSMAA },
-  { 0, CODE_FOR_spe_evmwhsmfaa, "__builtin_spe_evmwhsmfaa", SPE_BUILTIN_EVMWHSMFAA },
-  { 0, CODE_FOR_spe_evmwhsmiaa, "__builtin_spe_evmwhsmiaa", SPE_BUILTIN_EVMWHSMIAA },
-  { 0, CODE_FOR_spe_evmwhusiaa, "__builtin_spe_evmwhusiaa", SPE_BUILTIN_EVMWHUSIAA },
-  { 0, CODE_FOR_spe_evmwhumiaa, "__builtin_spe_evmwhumiaa", SPE_BUILTIN_EVMWHUMIAA },
-  { 0, CODE_FOR_spe_evmwhssfan, "__builtin_spe_evmwhssfan", SPE_BUILTIN_EVMWHSSFAN },
-  { 0, CODE_FOR_spe_evmwhssian, "__builtin_spe_evmwhssian", SPE_BUILTIN_EVMWHSSIAN },
-  { 0, CODE_FOR_spe_evmwhsmfan, "__builtin_spe_evmwhsmfan", SPE_BUILTIN_EVMWHSMFAN },
-  { 0, CODE_FOR_spe_evmwhsmian, "__builtin_spe_evmwhsmian", SPE_BUILTIN_EVMWHSMIAN },
-  { 0, CODE_FOR_spe_evmwhusian, "__builtin_spe_evmwhusian", SPE_BUILTIN_EVMWHUSIAN },
-  { 0, CODE_FOR_spe_evmwhumian, "__builtin_spe_evmwhumian", SPE_BUILTIN_EVMWHUMIAN },
-  { 0, CODE_FOR_spe_evmwhgssfaa, "__builtin_spe_evmwhgssfaa", SPE_BUILTIN_EVMWHGSSFAA },
-  { 0, CODE_FOR_spe_evmwhgsmfaa, "__builtin_spe_evmwhgsmfaa", SPE_BUILTIN_EVMWHGSMFAA },
-  { 0, CODE_FOR_spe_evmwhgsmiaa, "__builtin_spe_evmwhgsmiaa", SPE_BUILTIN_EVMWHGSMIAA },
-  { 0, CODE_FOR_spe_evmwhgumiaa, "__builtin_spe_evmwhgumiaa", SPE_BUILTIN_EVMWHGUMIAA },
-  { 0, CODE_FOR_spe_evmwhgssfan, "__builtin_spe_evmwhgssfan", SPE_BUILTIN_EVMWHGSSFAN },
-  { 0, CODE_FOR_spe_evmwhgsmfan, "__builtin_spe_evmwhgsmfan", SPE_BUILTIN_EVMWHGSMFAN },
-  { 0, CODE_FOR_spe_evmwhgsmian, "__builtin_spe_evmwhgsmian", SPE_BUILTIN_EVMWHGSMIAN },
-  { 0, CODE_FOR_spe_evmwhgumian, "__builtin_spe_evmwhgumian", SPE_BUILTIN_EVMWHGUMIAN },
-  { 0, CODE_FOR_spe_brinc, "__builtin_spe_brinc", SPE_BUILTIN_BRINC },
+#undef RS6000_BUILTIN_1
+#undef RS6000_BUILTIN_2
+#undef RS6000_BUILTIN_3
+#undef RS6000_BUILTIN_A
+#undef RS6000_BUILTIN_D
+#undef RS6000_BUILTIN_E
+#undef RS6000_BUILTIN_P
+#undef RS6000_BUILTIN_Q
+#undef RS6000_BUILTIN_S
+#undef RS6000_BUILTIN_X
+
+#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
+#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
+  { MASK, ICODE, NAME, ENUM },
+
+#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
+#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
+#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
+#define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
+#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
+#define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
+#define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
+#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
 
-  /* Place-holder.  Leave as last binary SPE builtin.  */
-  { 0, CODE_FOR_xorv2si3, "__builtin_spe_evxor", SPE_BUILTIN_EVXOR }
+static const struct builtin_description bdesc_2arg[] =
+{
+#include "rs6000-builtin.def"
 };
 
-/* AltiVec predicates.  */
+#undef RS6000_BUILTIN_1
+#undef RS6000_BUILTIN_2
+#undef RS6000_BUILTIN_3
+#undef RS6000_BUILTIN_A
+#undef RS6000_BUILTIN_D
+#undef RS6000_BUILTIN_E
+#undef RS6000_BUILTIN_P
+#undef RS6000_BUILTIN_Q
+#undef RS6000_BUILTIN_S
+#undef RS6000_BUILTIN_X
+
+#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
+#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
+#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
+#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
+#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
+#define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
+#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
+  { MASK, ICODE, NAME, ENUM },
+
+#define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
+#define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
+#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
 
-struct builtin_description_predicates
-{
-  const unsigned int mask;
-  const enum insn_code icode;
-  const char *const name;
-  const enum rs6000_builtins code;
-};
+/* AltiVec predicates.  */
 
-static const struct builtin_description_predicates bdesc_altivec_preds[] =
+static const struct builtin_description bdesc_altivec_preds[] =
 {
-  { MASK_ALTIVEC, CODE_FOR_altivec_vcmpbfp_p, "__builtin_altivec_vcmpbfp_p",
-    ALTIVEC_BUILTIN_VCMPBFP_P },
-  { MASK_ALTIVEC|MASK_VSX, CODE_FOR_vector_eq_v4sf_p,
-    "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P },
-  { MASK_ALTIVEC|MASK_VSX, CODE_FOR_vector_ge_v4sf_p,
-    "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P },
-  { MASK_ALTIVEC|MASK_VSX, CODE_FOR_vector_gt_v4sf_p,
-    "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P },
-  { MASK_ALTIVEC, CODE_FOR_vector_eq_v4si_p, "__builtin_altivec_vcmpequw_p",
-    ALTIVEC_BUILTIN_VCMPEQUW_P },
-  { MASK_ALTIVEC, CODE_FOR_vector_gt_v4si_p, "__builtin_altivec_vcmpgtsw_p",
-    ALTIVEC_BUILTIN_VCMPGTSW_P },
-  { MASK_ALTIVEC, CODE_FOR_vector_gtu_v4si_p, "__builtin_altivec_vcmpgtuw_p",
-    ALTIVEC_BUILTIN_VCMPGTUW_P },
-  { MASK_ALTIVEC, CODE_FOR_vector_eq_v8hi_p, "__builtin_altivec_vcmpequh_p",
-    ALTIVEC_BUILTIN_VCMPEQUH_P },
-  { MASK_ALTIVEC, CODE_FOR_vector_gt_v8hi_p, "__builtin_altivec_vcmpgtsh_p",
-    ALTIVEC_BUILTIN_VCMPGTSH_P },
-  { MASK_ALTIVEC, CODE_FOR_vector_gtu_v8hi_p, "__builtin_altivec_vcmpgtuh_p",
-    ALTIVEC_BUILTIN_VCMPGTUH_P },
-  { MASK_ALTIVEC, CODE_FOR_vector_eq_v16qi_p, "__builtin_altivec_vcmpequb_p",
-    ALTIVEC_BUILTIN_VCMPEQUB_P },
-  { MASK_ALTIVEC, CODE_FOR_vector_gt_v16qi_p, "__builtin_altivec_vcmpgtsb_p",
-    ALTIVEC_BUILTIN_VCMPGTSB_P },
-  { MASK_ALTIVEC, CODE_FOR_vector_gtu_v16qi_p, "__builtin_altivec_vcmpgtub_p",
-    ALTIVEC_BUILTIN_VCMPGTUB_P },
-
-  { MASK_VSX, CODE_FOR_vector_eq_v4sf_p, "__builtin_vsx_xvcmpeqsp_p",
-    VSX_BUILTIN_XVCMPEQSP_P },
-  { MASK_VSX, CODE_FOR_vector_ge_v4sf_p, "__builtin_vsx_xvcmpgesp_p",
-    VSX_BUILTIN_XVCMPGESP_P },
-  { MASK_VSX, CODE_FOR_vector_gt_v4sf_p, "__builtin_vsx_xvcmpgtsp_p",
-    VSX_BUILTIN_XVCMPGTSP_P },
-  { MASK_VSX, CODE_FOR_vector_eq_v2df_p, "__builtin_vsx_xvcmpeqdp_p",
-    VSX_BUILTIN_XVCMPEQDP_P },
-  { MASK_VSX, CODE_FOR_vector_ge_v2df_p, "__builtin_vsx_xvcmpgedp_p",
-    VSX_BUILTIN_XVCMPGEDP_P },
-  { MASK_VSX, CODE_FOR_vector_gt_v2df_p, "__builtin_vsx_xvcmpgtdp_p",
-    VSX_BUILTIN_XVCMPGTDP_P },
-
-  { MASK_ALTIVEC|MASK_VSX, CODE_FOR_nothing, "__builtin_vec_vcmpeq_p",
-    ALTIVEC_BUILTIN_VCMPEQ_P },
-  { MASK_ALTIVEC|MASK_VSX, CODE_FOR_nothing, "__builtin_vec_vcmpgt_p",
-    ALTIVEC_BUILTIN_VCMPGT_P },
-  { MASK_ALTIVEC|MASK_VSX, CODE_FOR_nothing, "__builtin_vec_vcmpge_p",
-    ALTIVEC_BUILTIN_VCMPGE_P }
+#include "rs6000-builtin.def"
 };
 
 /* SPE predicates.  */
-static struct builtin_description bdesc_spe_predicates[] =
+#undef RS6000_BUILTIN_1
+#undef RS6000_BUILTIN_2
+#undef RS6000_BUILTIN_3
+#undef RS6000_BUILTIN_A
+#undef RS6000_BUILTIN_D
+#undef RS6000_BUILTIN_E
+#undef RS6000_BUILTIN_P
+#undef RS6000_BUILTIN_Q
+#undef RS6000_BUILTIN_S
+#undef RS6000_BUILTIN_X
+
+#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
+#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
+#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
+#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
+#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
+#define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
+#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
+#define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
+#define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) \
+  { MASK, ICODE, NAME, ENUM },
+
+#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
+
+static const struct builtin_description bdesc_spe_predicates[] =
 {
-  /* Place-holder.  Leave as first.  */
-  { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evcmpeq", SPE_BUILTIN_EVCMPEQ },
-  { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evcmpgts", SPE_BUILTIN_EVCMPGTS },
-  { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evcmpgtu", SPE_BUILTIN_EVCMPGTU },
-  { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evcmplts", SPE_BUILTIN_EVCMPLTS },
-  { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evcmpltu", SPE_BUILTIN_EVCMPLTU },
-  { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evfscmpeq", SPE_BUILTIN_EVFSCMPEQ },
-  { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evfscmpgt", SPE_BUILTIN_EVFSCMPGT },
-  { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evfscmplt", SPE_BUILTIN_EVFSCMPLT },
-  { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evfststeq", SPE_BUILTIN_EVFSTSTEQ },
-  { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evfststgt", SPE_BUILTIN_EVFSTSTGT },
-  /* Place-holder.  Leave as last.  */
-  { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evfststlt", SPE_BUILTIN_EVFSTSTLT },
+#include "rs6000-builtin.def"
 };
 
 /* SPE evsel predicates.  */
-static struct builtin_description bdesc_spe_evsel[] =
+#undef RS6000_BUILTIN_1
+#undef RS6000_BUILTIN_2
+#undef RS6000_BUILTIN_3
+#undef RS6000_BUILTIN_A
+#undef RS6000_BUILTIN_D
+#undef RS6000_BUILTIN_E
+#undef RS6000_BUILTIN_P
+#undef RS6000_BUILTIN_Q
+#undef RS6000_BUILTIN_S
+#undef RS6000_BUILTIN_X
+
+#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
+#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
+#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
+#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
+#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
+#define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) \
+  { MASK, ICODE, NAME, ENUM },
+
+#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
+#define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
+#define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
+#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
+
+static const struct builtin_description bdesc_spe_evsel[] =
 {
-  /* Place-holder.  Leave as first.  */
-  { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evsel_gts", SPE_BUILTIN_EVSEL_CMPGTS },
-  { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evsel_gtu", SPE_BUILTIN_EVSEL_CMPGTU },
-  { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evsel_lts", SPE_BUILTIN_EVSEL_CMPLTS },
-  { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evsel_ltu", SPE_BUILTIN_EVSEL_CMPLTU },
-  { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evsel_eq", SPE_BUILTIN_EVSEL_CMPEQ },
-  { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evsel_fsgt", SPE_BUILTIN_EVSEL_FSCMPGT },
-  { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evsel_fslt", SPE_BUILTIN_EVSEL_FSCMPLT },
-  { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evsel_fseq", SPE_BUILTIN_EVSEL_FSCMPEQ },
-  { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evsel_fststgt", SPE_BUILTIN_EVSEL_FSTSTGT },
-  { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evsel_fststlt", SPE_BUILTIN_EVSEL_FSTSTLT },
-  /* Place-holder.  Leave as last.  */
-  { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evsel_fststeq", SPE_BUILTIN_EVSEL_FSTSTEQ },
+#include "rs6000-builtin.def"
 };
 
 /* PAIRED predicates.  */
+#undef RS6000_BUILTIN_1
+#undef RS6000_BUILTIN_2
+#undef RS6000_BUILTIN_3
+#undef RS6000_BUILTIN_A
+#undef RS6000_BUILTIN_D
+#undef RS6000_BUILTIN_E
+#undef RS6000_BUILTIN_P
+#undef RS6000_BUILTIN_Q
+#undef RS6000_BUILTIN_S
+#undef RS6000_BUILTIN_X
+
+#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
+#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
+#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
+#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
+#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
+#define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
+#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
+#define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) \
+  { MASK, ICODE, NAME, ENUM },
+
+#define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
+#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
+
 static const struct builtin_description bdesc_paired_preds[] =
 {
-  /* Place-holder.  Leave as first.  */
-  { 0, CODE_FOR_paired_cmpu0, "__builtin_paired_cmpu0", PAIRED_BUILTIN_CMPU0 },
-  /* Place-holder.  Leave as last.  */
-  { 0, CODE_FOR_paired_cmpu1, "__builtin_paired_cmpu1", PAIRED_BUILTIN_CMPU1 },
+#include "rs6000-builtin.def"
 };
 
 /* ABS* operations.  */
 
+#undef RS6000_BUILTIN_1
+#undef RS6000_BUILTIN_2
+#undef RS6000_BUILTIN_3
+#undef RS6000_BUILTIN_A
+#undef RS6000_BUILTIN_D
+#undef RS6000_BUILTIN_E
+#undef RS6000_BUILTIN_P
+#undef RS6000_BUILTIN_Q
+#undef RS6000_BUILTIN_S
+#undef RS6000_BUILTIN_X
+
+#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
+#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
+#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
+#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
+  { MASK, ICODE, NAME, ENUM },
+
+#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
+#define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
+#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
+#define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
+#define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
+#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
+
 static const struct builtin_description bdesc_abs[] =
 {
-  { MASK_ALTIVEC, CODE_FOR_absv4si2, "__builtin_altivec_abs_v4si", ALTIVEC_BUILTIN_ABS_V4SI },
-  { MASK_ALTIVEC, CODE_FOR_absv8hi2, "__builtin_altivec_abs_v8hi", ALTIVEC_BUILTIN_ABS_V8HI },
-  { MASK_ALTIVEC, CODE_FOR_absv4sf2, "__builtin_altivec_abs_v4sf", ALTIVEC_BUILTIN_ABS_V4SF },
-  { MASK_ALTIVEC, CODE_FOR_absv16qi2, "__builtin_altivec_abs_v16qi", ALTIVEC_BUILTIN_ABS_V16QI },
-  { MASK_ALTIVEC, CODE_FOR_altivec_abss_v4si, "__builtin_altivec_abss_v4si", ALTIVEC_BUILTIN_ABSS_V4SI },
-  { MASK_ALTIVEC, CODE_FOR_altivec_abss_v8hi, "__builtin_altivec_abss_v8hi", ALTIVEC_BUILTIN_ABSS_V8HI },
-  { MASK_ALTIVEC, CODE_FOR_altivec_abss_v16qi, "__builtin_altivec_abss_v16qi", ALTIVEC_BUILTIN_ABSS_V16QI },
-  { MASK_VSX, CODE_FOR_absv2df2, "__builtin_vsx_xvabsdp", VSX_BUILTIN_XVABSDP },
-  { MASK_VSX, CODE_FOR_vsx_nabsv2df2, "__builtin_vsx_xvnabsdp", VSX_BUILTIN_XVNABSDP },
-  { MASK_VSX, CODE_FOR_absv4sf2, "__builtin_vsx_xvabssp", VSX_BUILTIN_XVABSSP },
-  { MASK_VSX, CODE_FOR_vsx_nabsv4sf2, "__builtin_vsx_xvnabssp", VSX_BUILTIN_XVNABSSP },
+#include "rs6000-builtin.def"
 };
 
 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
    foo (VECa).  */
 
-static struct builtin_description bdesc_1arg[] =
+#undef RS6000_BUILTIN_1
+#undef RS6000_BUILTIN_2
+#undef RS6000_BUILTIN_3
+#undef RS6000_BUILTIN_A
+#undef RS6000_BUILTIN_E
+#undef RS6000_BUILTIN_D
+#undef RS6000_BUILTIN_P
+#undef RS6000_BUILTIN_Q
+#undef RS6000_BUILTIN_S
+#undef RS6000_BUILTIN_X
+
+#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
+  { MASK, ICODE, NAME, ENUM },
+
+#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
+#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
+#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
+#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
+#define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
+#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
+#define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
+#define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
+#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
+
+static const struct builtin_description bdesc_1arg[] =
 {
-  { MASK_ALTIVEC, CODE_FOR_altivec_vexptefp, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vlogefp, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP },
-  { MASK_ALTIVEC, CODE_FOR_rev4sf2, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP },
-  { MASK_ALTIVEC, CODE_FOR_vector_floorv4sf2, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vrfin, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN },
-  { MASK_ALTIVEC, CODE_FOR_vector_ceilv4sf2, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP },
-  { MASK_ALTIVEC, CODE_FOR_vector_btruncv4sf2, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ },
-  { MASK_ALTIVEC, CODE_FOR_rsqrtv4sf2, "__builtin_altivec_vrsqrtfp", ALTIVEC_BUILTIN_VRSQRTFP },
-  { MASK_ALTIVEC, CODE_FOR_rsqrtev4sf2, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vspltisb, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vspltish, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vspltisw, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsb, "__builtin_altivec_vupkhsb", ALTIVEC_BUILTIN_VUPKHSB },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vupkhpx, "__builtin_altivec_vupkhpx", ALTIVEC_BUILTIN_VUPKHPX },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsh, "__builtin_altivec_vupkhsh", ALTIVEC_BUILTIN_VUPKHSH },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vupklsb, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vupklpx, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vupklsh, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH },
-
-  { MASK_VSX, CODE_FOR_negv2df2, "__builtin_vsx_xvnegdp", VSX_BUILTIN_XVNEGDP },
-  { MASK_VSX, CODE_FOR_sqrtv2df2, "__builtin_vsx_xvsqrtdp", VSX_BUILTIN_XVSQRTDP },
-  { MASK_VSX, CODE_FOR_rsqrtv2df2, "__builtin_vsx_xvrsqrtdp", VSX_BUILTIN_VEC_RSQRT_V2DF },
-  { MASK_VSX, CODE_FOR_rsqrtev2df2, "__builtin_vsx_xvrsqrtedp", VSX_BUILTIN_XVRSQRTEDP },
-  { MASK_VSX, CODE_FOR_vsx_tsqrtv2df2_fe, "__builtin_vsx_xvtsqrtdp_fe", VSX_BUILTIN_XVTSQRTDP_FE },
-  { MASK_VSX, CODE_FOR_vsx_tsqrtv2df2_fg, "__builtin_vsx_xvtsqrtdp_fg", VSX_BUILTIN_XVTSQRTDP_FG },
-  { MASK_VSX, CODE_FOR_vsx_frev2df2, "__builtin_vsx_xvredp", VSX_BUILTIN_XVREDP },
-
-  { MASK_VSX, CODE_FOR_negv4sf2, "__builtin_vsx_xvnegsp", VSX_BUILTIN_XVNEGSP },
-  { MASK_VSX, CODE_FOR_sqrtv4sf2, "__builtin_vsx_xvsqrtsp", VSX_BUILTIN_XVSQRTSP },
-  { MASK_VSX, CODE_FOR_rsqrtv4sf2, "__builtin_vsx_xvrsqrtsp", VSX_BUILTIN_VEC_RSQRT_V4SF },
-  { MASK_VSX, CODE_FOR_rsqrtev4sf2, "__builtin_vsx_xvrsqrtesp", VSX_BUILTIN_XVRSQRTESP },
-  { MASK_VSX, CODE_FOR_vsx_tsqrtv4sf2_fe, "__builtin_vsx_xvtsqrtsp_fe", VSX_BUILTIN_XVTSQRTSP_FE },
-  { MASK_VSX, CODE_FOR_vsx_tsqrtv4sf2_fg, "__builtin_vsx_xvtsqrtsp_fg", VSX_BUILTIN_XVTSQRTSP_FG },
-  { MASK_VSX, CODE_FOR_vsx_frev4sf2, "__builtin_vsx_xvresp", VSX_BUILTIN_XVRESP },
-
-  { MASK_VSX, CODE_FOR_vsx_xscvdpsp, "__builtin_vsx_xscvdpsp", VSX_BUILTIN_XSCVDPSP },
-  { MASK_VSX, CODE_FOR_vsx_xscvdpsp, "__builtin_vsx_xscvspdp", VSX_BUILTIN_XSCVSPDP },
-  { MASK_VSX, CODE_FOR_vsx_xvcvdpsp, "__builtin_vsx_xvcvdpsp", VSX_BUILTIN_XVCVDPSP },
-  { MASK_VSX, CODE_FOR_vsx_xvcvspdp, "__builtin_vsx_xvcvspdp", VSX_BUILTIN_XVCVSPDP },
-  { MASK_VSX, CODE_FOR_vsx_tsqrtdf2_fe, "__builtin_vsx_xstsqrtdp_fe", VSX_BUILTIN_XSTSQRTDP_FE },
-  { MASK_VSX, CODE_FOR_vsx_tsqrtdf2_fg, "__builtin_vsx_xstsqrtdp_fg", VSX_BUILTIN_XSTSQRTDP_FG },
-
-  { MASK_VSX, CODE_FOR_vsx_fix_truncv2dfv2di2, "__builtin_vsx_xvcvdpsxds", VSX_BUILTIN_XVCVDPSXDS },
-  { MASK_VSX, CODE_FOR_vsx_fixuns_truncv2dfv2di2, "__builtin_vsx_xvcvdpuxds", VSX_BUILTIN_XVCVDPUXDS },
-  { MASK_VSX, CODE_FOR_vsx_fixuns_truncv2dfv2di2, "__builtin_vsx_xvcvdpuxds_uns", VSX_BUILTIN_XVCVDPUXDS_UNS },
-  { MASK_VSX, CODE_FOR_vsx_floatv2div2df2, "__builtin_vsx_xvcvsxddp", VSX_BUILTIN_XVCVSXDDP },
-  { MASK_VSX, CODE_FOR_vsx_floatunsv2div2df2, "__builtin_vsx_xvcvuxddp", VSX_BUILTIN_XVCVUXDDP },
-  { MASK_VSX, CODE_FOR_vsx_floatunsv2div2df2, "__builtin_vsx_xvcvuxddp_uns", VSX_BUILTIN_XVCVUXDDP_UNS },
-
-  { MASK_VSX, CODE_FOR_vsx_fix_truncv4sfv4si2, "__builtin_vsx_xvcvspsxws", VSX_BUILTIN_XVCVSPSXWS },
-  { MASK_VSX, CODE_FOR_vsx_fixuns_truncv4sfv4si2, "__builtin_vsx_xvcvspuxws", VSX_BUILTIN_XVCVSPUXWS },
-  { MASK_VSX, CODE_FOR_vsx_floatv4siv4sf2, "__builtin_vsx_xvcvsxwsp", VSX_BUILTIN_XVCVSXWSP },
-  { MASK_VSX, CODE_FOR_vsx_floatunsv4siv4sf2, "__builtin_vsx_xvcvuxwsp", VSX_BUILTIN_XVCVUXWSP },
-
-  { MASK_VSX, CODE_FOR_vsx_xvcvdpsxws, "__builtin_vsx_xvcvdpsxws", VSX_BUILTIN_XVCVDPSXWS },
-  { MASK_VSX, CODE_FOR_vsx_xvcvdpuxws, "__builtin_vsx_xvcvdpuxws", VSX_BUILTIN_XVCVDPUXWS },
-  { MASK_VSX, CODE_FOR_vsx_xvcvsxwdp, "__builtin_vsx_xvcvsxwdp", VSX_BUILTIN_XVCVSXWDP },
-  { MASK_VSX, CODE_FOR_vsx_xvcvuxwdp, "__builtin_vsx_xvcvuxwdp", VSX_BUILTIN_XVCVUXWDP },
-  { MASK_VSX, CODE_FOR_vsx_xvrdpi, "__builtin_vsx_xvrdpi", VSX_BUILTIN_XVRDPI },
-  { MASK_VSX, CODE_FOR_vsx_xvrdpic, "__builtin_vsx_xvrdpic", VSX_BUILTIN_XVRDPIC },
-  { MASK_VSX, CODE_FOR_vsx_floorv2df2, "__builtin_vsx_xvrdpim", VSX_BUILTIN_XVRDPIM },
-  { MASK_VSX, CODE_FOR_vsx_ceilv2df2, "__builtin_vsx_xvrdpip", VSX_BUILTIN_XVRDPIP },
-  { MASK_VSX, CODE_FOR_vsx_btruncv2df2, "__builtin_vsx_xvrdpiz", VSX_BUILTIN_XVRDPIZ },
-
-  { MASK_VSX, CODE_FOR_vsx_xvcvspsxds, "__builtin_vsx_xvcvspsxds", VSX_BUILTIN_XVCVSPSXDS },
-  { MASK_VSX, CODE_FOR_vsx_xvcvspuxds, "__builtin_vsx_xvcvspuxds", VSX_BUILTIN_XVCVSPUXDS },
-  { MASK_VSX, CODE_FOR_vsx_xvcvsxdsp, "__builtin_vsx_xvcvsxdsp", VSX_BUILTIN_XVCVSXDSP },
-  { MASK_VSX, CODE_FOR_vsx_xvcvuxdsp, "__builtin_vsx_xvcvuxdsp", VSX_BUILTIN_XVCVUXDSP },
-  { MASK_VSX, CODE_FOR_vsx_xvrspi, "__builtin_vsx_xvrspi", VSX_BUILTIN_XVRSPI },
-  { MASK_VSX, CODE_FOR_vsx_xvrspic, "__builtin_vsx_xvrspic", VSX_BUILTIN_XVRSPIC },
-  { MASK_VSX, CODE_FOR_vsx_floorv4sf2, "__builtin_vsx_xvrspim", VSX_BUILTIN_XVRSPIM },
-  { MASK_VSX, CODE_FOR_vsx_ceilv4sf2, "__builtin_vsx_xvrspip", VSX_BUILTIN_XVRSPIP },
-  { MASK_VSX, CODE_FOR_vsx_btruncv4sf2, "__builtin_vsx_xvrspiz", VSX_BUILTIN_XVRSPIZ },
-
-  { MASK_VSX, CODE_FOR_vsx_xsrdpi, "__builtin_vsx_xsrdpi", VSX_BUILTIN_XSRDPI },
-  { MASK_VSX, CODE_FOR_vsx_xsrdpic, "__builtin_vsx_xsrdpic", VSX_BUILTIN_XSRDPIC },
-  { MASK_VSX, CODE_FOR_vsx_floordf2, "__builtin_vsx_xsrdpim", VSX_BUILTIN_XSRDPIM },
-  { MASK_VSX, CODE_FOR_vsx_ceildf2, "__builtin_vsx_xsrdpip", VSX_BUILTIN_XSRDPIP },
-  { MASK_VSX, CODE_FOR_vsx_btruncdf2, "__builtin_vsx_xsrdpiz", VSX_BUILTIN_XSRDPIZ },
-
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_abs", ALTIVEC_BUILTIN_VEC_ABS },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_abss", ALTIVEC_BUILTIN_VEC_ABSS },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_ceil", ALTIVEC_BUILTIN_VEC_CEIL },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_expte", ALTIVEC_BUILTIN_VEC_EXPTE },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_floor", ALTIVEC_BUILTIN_VEC_FLOOR },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_loge", ALTIVEC_BUILTIN_VEC_LOGE },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mtvscr", ALTIVEC_BUILTIN_VEC_MTVSCR },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_re", ALTIVEC_BUILTIN_VEC_RE },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_round", ALTIVEC_BUILTIN_VEC_ROUND },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_rsqrt", ALTIVEC_BUILTIN_VEC_RSQRT },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_rsqrte", ALTIVEC_BUILTIN_VEC_RSQRTE },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_trunc", ALTIVEC_BUILTIN_VEC_TRUNC },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_unpackh", ALTIVEC_BUILTIN_VEC_UNPACKH },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhsh", ALTIVEC_BUILTIN_VEC_VUPKHSH },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhpx", ALTIVEC_BUILTIN_VEC_VUPKHPX },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhsb", ALTIVEC_BUILTIN_VEC_VUPKHSB },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_unpackl", ALTIVEC_BUILTIN_VEC_UNPACKL },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklpx", ALTIVEC_BUILTIN_VEC_VUPKLPX },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklsh", ALTIVEC_BUILTIN_VEC_VUPKLSH },
-  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklsb", ALTIVEC_BUILTIN_VEC_VUPKLSB },
-
-  { MASK_VSX, CODE_FOR_nothing, "__builtin_vec_nearbyint", ALTIVEC_BUILTIN_VEC_NEARBYINT },
-  { MASK_VSX, CODE_FOR_nothing, "__builtin_vec_rint", ALTIVEC_BUILTIN_VEC_RINT },
-  { MASK_VSX, CODE_FOR_nothing, "__builtin_vec_sqrt", ALTIVEC_BUILTIN_VEC_SQRT },
-
-  { MASK_ALTIVEC|MASK_VSX, CODE_FOR_floatv4siv4sf2, "__builtin_vec_float_sisf", VECTOR_BUILTIN_FLOAT_V4SI_V4SF },
-  { MASK_ALTIVEC|MASK_VSX, CODE_FOR_unsigned_floatv4siv4sf2, "__builtin_vec_uns_float_sisf", VECTOR_BUILTIN_UNSFLOAT_V4SI_V4SF },
-  { MASK_ALTIVEC|MASK_VSX, CODE_FOR_fix_truncv4sfv4si2, "__builtin_vec_fix_sfsi", VECTOR_BUILTIN_FIX_V4SF_V4SI },
-  { MASK_ALTIVEC|MASK_VSX, CODE_FOR_fixuns_truncv4sfv4si2, "__builtin_vec_fixuns_sfsi", VECTOR_BUILTIN_FIXUNS_V4SF_V4SI },
-
-  /* The SPE unary builtins must start with SPE_BUILTIN_EVABS and
-     end with SPE_BUILTIN_EVSUBFUSIAAW.  */
-  { 0, CODE_FOR_absv2si2, "__builtin_spe_evabs", SPE_BUILTIN_EVABS },
-  { 0, CODE_FOR_spe_evaddsmiaaw, "__builtin_spe_evaddsmiaaw", SPE_BUILTIN_EVADDSMIAAW },
-  { 0, CODE_FOR_spe_evaddssiaaw, "__builtin_spe_evaddssiaaw", SPE_BUILTIN_EVADDSSIAAW },
-  { 0, CODE_FOR_spe_evaddumiaaw, "__builtin_spe_evaddumiaaw", SPE_BUILTIN_EVADDUMIAAW },
-  { 0, CODE_FOR_spe_evaddusiaaw, "__builtin_spe_evaddusiaaw", SPE_BUILTIN_EVADDUSIAAW },
-  { 0, CODE_FOR_spe_evcntlsw, "__builtin_spe_evcntlsw", SPE_BUILTIN_EVCNTLSW },
-  { 0, CODE_FOR_spe_evcntlzw, "__builtin_spe_evcntlzw", SPE_BUILTIN_EVCNTLZW },
-  { 0, CODE_FOR_spe_evextsb, "__builtin_spe_evextsb", SPE_BUILTIN_EVEXTSB },
-  { 0, CODE_FOR_spe_evextsh, "__builtin_spe_evextsh", SPE_BUILTIN_EVEXTSH },
-  { 0, CODE_FOR_spe_evfsabs, "__builtin_spe_evfsabs", SPE_BUILTIN_EVFSABS },
-  { 0, CODE_FOR_spe_evfscfsf, "__builtin_spe_evfscfsf", SPE_BUILTIN_EVFSCFSF },
-  { 0, CODE_FOR_spe_evfscfsi, "__builtin_spe_evfscfsi", SPE_BUILTIN_EVFSCFSI },
-  { 0, CODE_FOR_spe_evfscfuf, "__builtin_spe_evfscfuf", SPE_BUILTIN_EVFSCFUF },
-  { 0, CODE_FOR_spe_evfscfui, "__builtin_spe_evfscfui", SPE_BUILTIN_EVFSCFUI },
-  { 0, CODE_FOR_spe_evfsctsf, "__builtin_spe_evfsctsf", SPE_BUILTIN_EVFSCTSF },
-  { 0, CODE_FOR_spe_evfsctsi, "__builtin_spe_evfsctsi", SPE_BUILTIN_EVFSCTSI },
-  { 0, CODE_FOR_spe_evfsctsiz, "__builtin_spe_evfsctsiz", SPE_BUILTIN_EVFSCTSIZ },
-  { 0, CODE_FOR_spe_evfsctuf, "__builtin_spe_evfsctuf", SPE_BUILTIN_EVFSCTUF },
-  { 0, CODE_FOR_spe_evfsctui, "__builtin_spe_evfsctui", SPE_BUILTIN_EVFSCTUI },
-  { 0, CODE_FOR_spe_evfsctuiz, "__builtin_spe_evfsctuiz", SPE_BUILTIN_EVFSCTUIZ },
-  { 0, CODE_FOR_spe_evfsnabs, "__builtin_spe_evfsnabs", SPE_BUILTIN_EVFSNABS },
-  { 0, CODE_FOR_spe_evfsneg, "__builtin_spe_evfsneg", SPE_BUILTIN_EVFSNEG },
-  { 0, CODE_FOR_spe_evmra, "__builtin_spe_evmra", SPE_BUILTIN_EVMRA },
-  { 0, CODE_FOR_negv2si2, "__builtin_spe_evneg", SPE_BUILTIN_EVNEG },
-  { 0, CODE_FOR_spe_evrndw, "__builtin_spe_evrndw", SPE_BUILTIN_EVRNDW },
-  { 0, CODE_FOR_spe_evsubfsmiaaw, "__builtin_spe_evsubfsmiaaw", SPE_BUILTIN_EVSUBFSMIAAW },
-  { 0, CODE_FOR_spe_evsubfssiaaw, "__builtin_spe_evsubfssiaaw", SPE_BUILTIN_EVSUBFSSIAAW },
-  { 0, CODE_FOR_spe_evsubfumiaaw, "__builtin_spe_evsubfumiaaw", SPE_BUILTIN_EVSUBFUMIAAW },
-
-  /* Place-holder.  Leave as last unary SPE builtin.  */
-  { 0, CODE_FOR_spe_evsubfusiaaw, "__builtin_spe_evsubfusiaaw", SPE_BUILTIN_EVSUBFUSIAAW },
-
-  { 0, CODE_FOR_paired_absv2sf2, "__builtin_paired_absv2sf2", PAIRED_BUILTIN_ABSV2SF2 },
-  { 0, CODE_FOR_nabsv2sf2, "__builtin_paired_nabsv2sf2", PAIRED_BUILTIN_NABSV2SF2 },
-  { 0, CODE_FOR_paired_negv2sf2, "__builtin_paired_negv2sf2", PAIRED_BUILTIN_NEGV2SF2 },
-  { 0, CODE_FOR_sqrtv2sf2, "__builtin_paired_sqrtv2sf2", PAIRED_BUILTIN_SQRTV2SF2 },
-  { 0, CODE_FOR_resv2sf2, "__builtin_paired_resv2sf2", PAIRED_BUILTIN_RESV2SF2 }
+#include "rs6000-builtin.def"
 };
 
+#undef RS6000_BUILTIN_1
+#undef RS6000_BUILTIN_2
+#undef RS6000_BUILTIN_3
+#undef RS6000_BUILTIN_A
+#undef RS6000_BUILTIN_D
+#undef RS6000_BUILTIN_E
+#undef RS6000_BUILTIN_P
+#undef RS6000_BUILTIN_Q
+#undef RS6000_BUILTIN_S
+#undef RS6000_BUILTIN_X
+
+/* Return true if a builtin function is overloaded.  */
+bool
+rs6000_overloaded_builtin_p (enum rs6000_builtins fncode)
+{
+  return (rs6000_builtin_info[(int)fncode].attr & RS6000_BTC_OVERLOADED) != 0;
+}
+
+
 static rtx
 rs6000_expand_unop_builtin (enum insn_code icode, tree exp, rtx target)
 {
@@ -11103,19 +10626,16 @@  static rtx
 altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
 {
   const struct builtin_description *d;
-  const struct builtin_description_predicates *dp;
   size_t i;
   enum insn_code icode;
   tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
   tree arg0;
   rtx op0, pat;
   enum machine_mode tmode, mode0;
-  unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
+  enum rs6000_builtins fcode
+    = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
 
-  if ((fcode >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
-       && fcode <= ALTIVEC_BUILTIN_OVERLOADED_LAST)
-      || (fcode >= VSX_BUILTIN_OVERLOADED_FIRST
-	  && fcode <= VSX_BUILTIN_OVERLOADED_LAST))
+  if (rs6000_overloaded_builtin_p (fcode))
     {
       *expandedp = true;
       error ("unresolved overload for Altivec builtin %qF", fndecl);
@@ -11268,10 +10788,10 @@  altivec_expand_builtin (tree exp, rtx ta
       return altivec_expand_abs_builtin (d->icode, exp, target);
 
   /* Expand the AltiVec predicates.  */
-  dp = bdesc_altivec_preds;
-  for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
-    if (dp->code == fcode)
-      return altivec_expand_predicate_builtin (dp->icode, exp, target);
+  d = bdesc_altivec_preds;
+  for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, d++)
+    if (d->code == fcode)
+      return altivec_expand_predicate_builtin (d->icode, exp, target);
 
   /* LV* are funky.  We initialized them differently.  */
   switch (fcode)
@@ -11372,30 +10892,30 @@  paired_expand_builtin (tree exp, rtx tar
 
 /* Binops that need to be initialized manually, but can be expanded
    automagically by rs6000_expand_binop_builtin.  */
-static struct builtin_description bdesc_2arg_spe[] =
+static const struct builtin_description bdesc_2arg_spe[] =
 {
-  { 0, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX },
-  { 0, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX },
-  { 0, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX },
-  { 0, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX },
-  { 0, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX },
-  { 0, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX },
-  { 0, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX },
-  { 0, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX },
-  { 0, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX },
-  { 0, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX },
-  { 0, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX },
-  { 0, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD },
-  { 0, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW },
-  { 0, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH },
-  { 0, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE },
-  { 0, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU },
-  { 0, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS },
-  { 0, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT },
-  { 0, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT },
-  { 0, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT },
-  { 0, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT },
-  { 0, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT }
+  { RS6000_BTM_SPE, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX },
+  { RS6000_BTM_SPE, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX },
+  { RS6000_BTM_SPE, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX },
+  { RS6000_BTM_SPE, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX },
+  { RS6000_BTM_SPE, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX },
+  { RS6000_BTM_SPE, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX },
+  { RS6000_BTM_SPE, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX },
+  { RS6000_BTM_SPE, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX },
+  { RS6000_BTM_SPE, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX },
+  { RS6000_BTM_SPE, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX },
+  { RS6000_BTM_SPE, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX },
+  { RS6000_BTM_SPE, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD },
+  { RS6000_BTM_SPE, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW },
+  { RS6000_BTM_SPE, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH },
+  { RS6000_BTM_SPE, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE },
+  { RS6000_BTM_SPE, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU },
+  { RS6000_BTM_SPE, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS },
+  { RS6000_BTM_SPE, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT },
+  { RS6000_BTM_SPE, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT },
+  { RS6000_BTM_SPE, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT },
+  { RS6000_BTM_SPE, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT },
+  { RS6000_BTM_SPE, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT }
 };
 
 /* Expand the builtin in EXP and store the result in TARGET.  Store
@@ -11412,7 +10932,7 @@  spe_expand_builtin (tree exp, rtx target
   enum insn_code icode;
   enum machine_mode tmode, mode0;
   rtx pat, op0;
-  struct builtin_description *d;
+  const struct builtin_description *d;
   size_t i;
 
   *expandedp = true;
@@ -11452,17 +10972,17 @@  spe_expand_builtin (tree exp, rtx target
       break;
     }
 
-  d = (struct builtin_description *) bdesc_2arg_spe;
+  d = bdesc_2arg_spe;
   for (i = 0; i < ARRAY_SIZE (bdesc_2arg_spe); ++i, ++d)
     if (d->code == fcode)
       return rs6000_expand_binop_builtin (d->icode, exp, target);
 
-  d = (struct builtin_description *) bdesc_spe_predicates;
+  d = bdesc_spe_predicates;
   for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, ++d)
     if (d->code == fcode)
       return spe_expand_predicate_builtin (d->icode, exp, target);
 
-  d = (struct builtin_description *) bdesc_spe_evsel;
+  d = bdesc_spe_evsel;
   for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, ++d)
     if (d->code == fcode)
       return spe_expand_evsel_builtin (d->icode, exp, target);
@@ -11765,6 +11285,32 @@  spe_expand_evsel_builtin (enum insn_code
   return target;
 }
 
+/* Raise an error message for a builtin function that is called without the
+   appropriate target options being set.  */
+
+static void
+rs6000_invalid_builtin (enum rs6000_builtins fncode)
+{
+  size_t uns_fncode = (size_t)fncode;
+  const char *name = rs6000_builtin_info[uns_fncode].name;
+  unsigned fnmask = rs6000_builtin_info[uns_fncode].mask;
+
+  gcc_assert (name != NULL);
+  if ((fnmask & RS6000_BTM_CELL) != 0)
+    error ("Builtin function %s is only valid for the cell processor", name);
+  else if ((fnmask & RS6000_BTM_VSX) != 0)
+    error ("Builtin function %s requires the -mvsx option", name);
+  else if ((fnmask & RS6000_BTM_ALTIVEC) != 0)
+    error ("Builtin function %s requires the -maltivec option", name);
+  else if ((fnmask & RS6000_BTM_PAIRED) != 0)
+    error ("Builtin function %s requires the -mpaired option", name);
+  else if ((fnmask & RS6000_BTM_SPE) != 0)
+    error ("Builtin function %s requires the -mspe option", name);
+  else
+    error ("Builtin function %s is not supported with the current options",
+	   name);
+}
+
 /* Expand an expression EXP that calls a built-in function,
    with result going to TARGET if that's convenient
    (and in mode MODE if that's convenient).
@@ -11777,11 +11323,52 @@  rs6000_expand_builtin (tree exp, rtx tar
 		       int ignore ATTRIBUTE_UNUSED)
 {
   tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
-  unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
+  enum rs6000_builtins fcode
+    = (enum rs6000_builtins)DECL_FUNCTION_CODE (fndecl);
+  size_t uns_fcode = (size_t)fcode;
   const struct builtin_description *d;
   size_t i;
   rtx ret;
   bool success;
+  unsigned mask = rs6000_builtin_info[uns_fcode].mask;
+  bool func_valid_p = ((rs6000_builtin_mask & mask) == mask);
+
+  if (TARGET_DEBUG_BUILTIN)
+    {
+      enum insn_code icode = rs6000_builtin_info[uns_fcode].icode;
+      const char *name1 = rs6000_builtin_info[uns_fcode].name;
+      const char *name2 = ((icode != CODE_FOR_nothing)
+			   ? get_insn_name ((int)icode)
+			   : "nothing");
+      const char *name3;
+
+      switch (rs6000_builtin_info[uns_fcode].attr & RS6000_BTC_TYPE_MASK)
+	{
+	default:		   name3 = "unknown";	break;
+	case RS6000_BTC_SPECIAL:   name3 = "special";	break;
+	case RS6000_BTC_UNARY:	   name3 = "unary";	break;
+	case RS6000_BTC_BINARY:	   name3 = "binary";	break;
+	case RS6000_BTC_TERNARY:   name3 = "ternary";	break;
+	case RS6000_BTC_PREDICATE: name3 = "predicate";	break;
+	case RS6000_BTC_ABS:	   name3 = "abs";	break;
+	case RS6000_BTC_EVSEL:	   name3 = "evsel";	break;
+	case RS6000_BTC_DST:	   name3 = "dst";	break;
+	}
+
+
+      fprintf (stderr,
+	       "rs6000_expand_builtin, %s (%d), insn = %s (%d), type=%s%s\n",
+	       (name1) ? name1 : "---", fcode,
+	       (name2) ? name2 : "---", (int)icode,
+	       name3,
+	       func_valid_p ? "" : ", not valid");
+    }	     
+
+  if (!func_valid_p)
+    {
+      rs6000_invalid_builtin (fcode);
+      return NULL_RTX;
+    }
 
   switch (fcode)
     {
@@ -11887,13 +11474,13 @@  rs6000_expand_builtin (tree exp, rtx tar
   gcc_assert (TARGET_ALTIVEC || TARGET_VSX || TARGET_SPE || TARGET_PAIRED_FLOAT);
 
   /* Handle simple unary operations.  */
-  d = (struct builtin_description *) bdesc_1arg;
+  d = bdesc_1arg;
   for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
     if (d->code == fcode)
       return rs6000_expand_unop_builtin (d->icode, exp, target);
 
   /* Handle simple binary operations.  */
-  d = (struct builtin_description *) bdesc_2arg;
+  d = bdesc_2arg;
   for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
     if (d->code == fcode)
       return rs6000_expand_binop_builtin (d->icode, exp, target);
@@ -11912,6 +11499,14 @@  rs6000_init_builtins (void)
 {
   tree tdecl;
   tree ftype;
+  enum machine_mode mode;
+
+  if (TARGET_DEBUG_BUILTIN)
+    fprintf (stderr, "rs6000_init_builtins%s%s%s%s\n",
+	     (TARGET_PAIRED_FLOAT) ? ", paired"	 : "",
+	     (TARGET_SPE)	   ? ", spe"	 : "",
+	     (TARGET_ALTIVEC)	   ? ", altivec" : "",
+	     (TARGET_VSX)	   ? ", vsx"	 : "");
 
   V2SI_type_node = build_vector_type (intSI_type_node, 2);
   V2SF_type_node = build_vector_type (float_type_node, 2);
@@ -12068,91 +11663,70 @@  rs6000_init_builtins (void)
   TYPE_NAME (pixel_V8HI_type_node) = tdecl;
   (*lang_hooks.decls.pushdecl) (tdecl);
 
-  if (TARGET_VSX)
-    {
-      tdecl = build_decl (BUILTINS_LOCATION,
-			  TYPE_DECL, get_identifier ("__vector double"),
-			  V2DF_type_node);
-      TYPE_NAME (V2DF_type_node) = tdecl;
-      (*lang_hooks.decls.pushdecl) (tdecl);
-
-      tdecl = build_decl (BUILTINS_LOCATION,
-			  TYPE_DECL, get_identifier ("__vector long"),
-			  V2DI_type_node);
-      TYPE_NAME (V2DI_type_node) = tdecl;
-      (*lang_hooks.decls.pushdecl) (tdecl);
-
-      tdecl = build_decl (BUILTINS_LOCATION,
-			  TYPE_DECL, get_identifier ("__vector unsigned long"),
-			  unsigned_V2DI_type_node);
-      TYPE_NAME (unsigned_V2DI_type_node) = tdecl;
-      (*lang_hooks.decls.pushdecl) (tdecl);
-
-      tdecl = build_decl (BUILTINS_LOCATION,
-			  TYPE_DECL, get_identifier ("__vector __bool long"),
-			  bool_V2DI_type_node);
-      TYPE_NAME (bool_V2DI_type_node) = tdecl;
-      (*lang_hooks.decls.pushdecl) (tdecl);
-    }
+  tdecl = build_decl (BUILTINS_LOCATION,
+		      TYPE_DECL, get_identifier ("__vector double"),
+		      V2DF_type_node);
+  TYPE_NAME (V2DF_type_node) = tdecl;
+  (*lang_hooks.decls.pushdecl) (tdecl);
 
+  tdecl = build_decl (BUILTINS_LOCATION,
+		      TYPE_DECL, get_identifier ("__vector long"),
+		      V2DI_type_node);
+  TYPE_NAME (V2DI_type_node) = tdecl;
+  (*lang_hooks.decls.pushdecl) (tdecl);
+
+  tdecl = build_decl (BUILTINS_LOCATION,
+		      TYPE_DECL, get_identifier ("__vector unsigned long"),
+		      unsigned_V2DI_type_node);
+  TYPE_NAME (unsigned_V2DI_type_node) = tdecl;
+  (*lang_hooks.decls.pushdecl) (tdecl);
+
+  tdecl = build_decl (BUILTINS_LOCATION,
+		      TYPE_DECL, get_identifier ("__vector __bool long"),
+		      bool_V2DI_type_node);
+  TYPE_NAME (bool_V2DI_type_node) = tdecl;
+  (*lang_hooks.decls.pushdecl) (tdecl);
+
+  /* Paired and SPE builtins are only available if you build a compiler with
+     the appropriate options, so only create those builtins with the
+     appropriate compiler option.  Create Altivec and VSX builtins on machines
+     with at least the general purpose extensions (970 and newer) to allow the
+     use of the target attribute.  */
   if (TARGET_PAIRED_FLOAT)
     paired_init_builtins ();
   if (TARGET_SPE)
     spe_init_builtins ();
-  if (TARGET_ALTIVEC)
+  if (TARGET_EXTRA_BUILTINS)
     altivec_init_builtins ();
-  if (TARGET_ALTIVEC || TARGET_SPE || TARGET_PAIRED_FLOAT || TARGET_VSX)
+  if (TARGET_EXTRA_BUILTINS || TARGET_SPE || TARGET_PAIRED_FLOAT)
     rs6000_common_init_builtins ();
-  if (TARGET_FRE)
-    {
-      ftype = builtin_function_type (DFmode, DFmode, DFmode, VOIDmode,
-				     RS6000_BUILTIN_RECIP,
-				     "__builtin_recipdiv");
-      def_builtin (MASK_POPCNTB, "__builtin_recipdiv", ftype,
-		   RS6000_BUILTIN_RECIP);
-    }
-  if (TARGET_FRES)
-    {
-      ftype = builtin_function_type (SFmode, SFmode, SFmode, VOIDmode,
-				     RS6000_BUILTIN_RECIPF,
-				     "__builtin_recipdivf");
-      def_builtin (MASK_PPC_GFXOPT, "__builtin_recipdivf", ftype,
-		   RS6000_BUILTIN_RECIPF);
-    }
-  if (TARGET_FRSQRTE)
-    {
-      ftype = builtin_function_type (DFmode, DFmode, VOIDmode, VOIDmode,
-				     RS6000_BUILTIN_RSQRT,
-				     "__builtin_rsqrt");
-      def_builtin (MASK_PPC_GFXOPT, "__builtin_rsqrt", ftype,
-		   RS6000_BUILTIN_RSQRT);
-    }
-  if (TARGET_FRSQRTES)
-    {
-      ftype = builtin_function_type (SFmode, SFmode, VOIDmode, VOIDmode,
-				     RS6000_BUILTIN_RSQRTF,
-				     "__builtin_rsqrtf");
-      def_builtin (MASK_PPC_GFXOPT, "__builtin_rsqrtf", ftype,
-		   RS6000_BUILTIN_RSQRTF);
-    }
-  if (TARGET_POPCNTD)
-    {
-      enum machine_mode mode = (TARGET_64BIT) ? DImode : SImode;
-      tree ftype = builtin_function_type (mode, mode, mode, VOIDmode,
-					  POWER7_BUILTIN_BPERMD,
-					  "__builtin_bpermd");
-      def_builtin (MASK_POPCNTD, "__builtin_bpermd", ftype,
-		   POWER7_BUILTIN_BPERMD);
-    }
-  if (TARGET_POWERPC)
-    {
+
+  ftype = builtin_function_type (DFmode, DFmode, DFmode, VOIDmode,
+				 RS6000_BUILTIN_RECIP, "__builtin_recipdiv");
+  def_builtin ("__builtin_recipdiv", ftype, RS6000_BUILTIN_RECIP);
+
+  ftype = builtin_function_type (SFmode, SFmode, SFmode, VOIDmode,
+				 RS6000_BUILTIN_RECIPF, "__builtin_recipdivf");
+  def_builtin ("__builtin_recipdivf", ftype, RS6000_BUILTIN_RECIPF);
+
+  ftype = builtin_function_type (DFmode, DFmode, VOIDmode, VOIDmode,
+				 RS6000_BUILTIN_RSQRT, "__builtin_rsqrt");
+  def_builtin ("__builtin_rsqrt", ftype, RS6000_BUILTIN_RSQRT);
+
+  ftype = builtin_function_type (SFmode, SFmode, VOIDmode, VOIDmode,
+				 RS6000_BUILTIN_RSQRTF, "__builtin_rsqrtf");
+  def_builtin ("__builtin_rsqrtf", ftype, RS6000_BUILTIN_RSQRTF);
+
+  mode = (TARGET_64BIT) ? DImode : SImode;
+  ftype = builtin_function_type (mode, mode, mode, VOIDmode,
+				 POWER7_BUILTIN_BPERMD, "__builtin_bpermd");
+  def_builtin ("__builtin_bpermd", ftype, POWER7_BUILTIN_BPERMD);
+
       /* Don't use builtin_function_type here, as it maps HI/QI to SI.  */
-      tree ftype = build_function_type_list (unsigned_intHI_type_node,
-					     unsigned_intHI_type_node,
-					     NULL_TREE);
-      def_builtin (MASK_POWERPC, "__builtin_bswap16", ftype,
-		   RS6000_BUILTIN_BSWAP_HI);
-    }
+  ftype = build_function_type_list (unsigned_intHI_type_node,
+				    unsigned_intHI_type_node,
+				    NULL_TREE);
+  def_builtin ("__builtin_bswap16", ftype, RS6000_BUILTIN_BSWAP_HI);
 
 #if TARGET_XCOFF
   /* AIX libm provides clog as __clog.  */
@@ -12170,38 +11744,19 @@  rs6000_init_builtins (void)
 static tree
 rs6000_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED)
 {
+  unsigned fnmask;
+
   if (code >= RS6000_BUILTIN_COUNT)
     return error_mark_node;
 
-  return rs6000_builtin_decls[code];
-}
-
-/* Search through a set of builtins and enable the mask bits.
-   DESC is an array of builtins.
-   SIZE is the total number of builtins.
-   START is the builtin enum at which to start.
-   END is the builtin enum at which to end.  */
-static void
-enable_mask_for_builtins (struct builtin_description *desc, int size,
-			  enum rs6000_builtins start,
-			  enum rs6000_builtins end)
-{
-  int i;
-
-  for (i = 0; i < size; ++i)
-    if (desc[i].code == start)
-      break;
-
-  if (i == size)
-    return;
-
-  for (; i < size; ++i)
+  fnmask = rs6000_builtin_info[code].mask;
+  if ((fnmask & rs6000_builtin_mask) != fnmask)
     {
-      /* Flip all the bits on.  */
-      desc[i].mask = target_flags;
-      if (desc[i].code == end)
-	break;
+      rs6000_invalid_builtin ((enum rs6000_builtins)code);
+      return error_mark_node;
     }
+
+  return rs6000_builtin_decls[code];
 }
 
 static void
@@ -12209,7 +11764,7 @@  spe_init_builtins (void)
 {
   tree puint_type_node = build_pointer_type (unsigned_type_node);
   tree pushort_type_node = build_pointer_type (short_unsigned_type_node);
-  struct builtin_description *d;
+  const struct builtin_description *d;
   size_t i;
 
   tree v2si_ftype_4_v2si
@@ -12299,28 +11854,6 @@  spe_init_builtins (void)
                                 signed_char_type_node,
                                 NULL_TREE);
 
-  /* The initialization of the simple binary and unary builtins is
-     done in rs6000_common_init_builtins, but we have to enable the
-     mask bits here manually because we have run out of `target_flags'
-     bits.  We really need to redesign this mask business.  */
-
-  enable_mask_for_builtins ((struct builtin_description *) bdesc_2arg,
-			    ARRAY_SIZE (bdesc_2arg),
-			    SPE_BUILTIN_EVADDW,
-			    SPE_BUILTIN_EVXOR);
-  enable_mask_for_builtins ((struct builtin_description *) bdesc_1arg,
-			    ARRAY_SIZE (bdesc_1arg),
-			    SPE_BUILTIN_EVABS,
-			    SPE_BUILTIN_EVSUBFUSIAAW);
-  enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_predicates,
-			    ARRAY_SIZE (bdesc_spe_predicates),
-			    SPE_BUILTIN_EVCMPEQ,
-			    SPE_BUILTIN_EVFSTSTLT);
-  enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_evsel,
-			    ARRAY_SIZE (bdesc_spe_evsel),
-			    SPE_BUILTIN_EVSEL_CMPGTS,
-			    SPE_BUILTIN_EVSEL_FSTSTEQ);
-
   (*lang_hooks.decls.pushdecl)
     (build_decl (BUILTINS_LOCATION, TYPE_DECL,
 		 get_identifier ("__ev64_opaque__"),
@@ -12328,51 +11861,51 @@  spe_init_builtins (void)
 
   /* Initialize irregular SPE builtins.  */
 
-  def_builtin (target_flags, "__builtin_spe_mtspefscr", void_ftype_int, SPE_BUILTIN_MTSPEFSCR);
-  def_builtin (target_flags, "__builtin_spe_mfspefscr", int_ftype_void, SPE_BUILTIN_MFSPEFSCR);
-  def_builtin (target_flags, "__builtin_spe_evstddx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDDX);
-  def_builtin (target_flags, "__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDHX);
-  def_builtin (target_flags, "__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDWX);
-  def_builtin (target_flags, "__builtin_spe_evstwhex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHEX);
-  def_builtin (target_flags, "__builtin_spe_evstwhox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHOX);
-  def_builtin (target_flags, "__builtin_spe_evstwwex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWEX);
-  def_builtin (target_flags, "__builtin_spe_evstwwox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWOX);
-  def_builtin (target_flags, "__builtin_spe_evstdd", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDD);
-  def_builtin (target_flags, "__builtin_spe_evstdh", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDH);
-  def_builtin (target_flags, "__builtin_spe_evstdw", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDW);
-  def_builtin (target_flags, "__builtin_spe_evstwhe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHE);
-  def_builtin (target_flags, "__builtin_spe_evstwho", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHO);
-  def_builtin (target_flags, "__builtin_spe_evstwwe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWE);
-  def_builtin (target_flags, "__builtin_spe_evstwwo", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWO);
-  def_builtin (target_flags, "__builtin_spe_evsplatfi", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATFI);
-  def_builtin (target_flags, "__builtin_spe_evsplati", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATI);
+  def_builtin ("__builtin_spe_mtspefscr", void_ftype_int, SPE_BUILTIN_MTSPEFSCR);
+  def_builtin ("__builtin_spe_mfspefscr", int_ftype_void, SPE_BUILTIN_MFSPEFSCR);
+  def_builtin ("__builtin_spe_evstddx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDDX);
+  def_builtin ("__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDHX);
+  def_builtin ("__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDWX);
+  def_builtin ("__builtin_spe_evstwhex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHEX);
+  def_builtin ("__builtin_spe_evstwhox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHOX);
+  def_builtin ("__builtin_spe_evstwwex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWEX);
+  def_builtin ("__builtin_spe_evstwwox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWOX);
+  def_builtin ("__builtin_spe_evstdd", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDD);
+  def_builtin ("__builtin_spe_evstdh", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDH);
+  def_builtin ("__builtin_spe_evstdw", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDW);
+  def_builtin ("__builtin_spe_evstwhe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHE);
+  def_builtin ("__builtin_spe_evstwho", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHO);
+  def_builtin ("__builtin_spe_evstwwe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWE);
+  def_builtin ("__builtin_spe_evstwwo", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWO);
+  def_builtin ("__builtin_spe_evsplatfi", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATFI);
+  def_builtin ("__builtin_spe_evsplati", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATI);
 
   /* Loads.  */
-  def_builtin (target_flags, "__builtin_spe_evlddx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDDX);
-  def_builtin (target_flags, "__builtin_spe_evldwx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDWX);
-  def_builtin (target_flags, "__builtin_spe_evldhx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDHX);
-  def_builtin (target_flags, "__builtin_spe_evlwhex", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHEX);
-  def_builtin (target_flags, "__builtin_spe_evlwhoux", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOUX);
-  def_builtin (target_flags, "__builtin_spe_evlwhosx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOSX);
-  def_builtin (target_flags, "__builtin_spe_evlwwsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLATX);
-  def_builtin (target_flags, "__builtin_spe_evlwhsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLATX);
-  def_builtin (target_flags, "__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLATX);
-  def_builtin (target_flags, "__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLATX);
-  def_builtin (target_flags, "__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLATX);
-  def_builtin (target_flags, "__builtin_spe_evldd", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDD);
-  def_builtin (target_flags, "__builtin_spe_evldw", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDW);
-  def_builtin (target_flags, "__builtin_spe_evldh", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDH);
-  def_builtin (target_flags, "__builtin_spe_evlhhesplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLAT);
-  def_builtin (target_flags, "__builtin_spe_evlhhossplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLAT);
-  def_builtin (target_flags, "__builtin_spe_evlhhousplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLAT);
-  def_builtin (target_flags, "__builtin_spe_evlwhe", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHE);
-  def_builtin (target_flags, "__builtin_spe_evlwhos", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOS);
-  def_builtin (target_flags, "__builtin_spe_evlwhou", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOU);
-  def_builtin (target_flags, "__builtin_spe_evlwhsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLAT);
-  def_builtin (target_flags, "__builtin_spe_evlwwsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLAT);
+  def_builtin ("__builtin_spe_evlddx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDDX);
+  def_builtin ("__builtin_spe_evldwx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDWX);
+  def_builtin ("__builtin_spe_evldhx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDHX);
+  def_builtin ("__builtin_spe_evlwhex", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHEX);
+  def_builtin ("__builtin_spe_evlwhoux", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOUX);
+  def_builtin ("__builtin_spe_evlwhosx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOSX);
+  def_builtin ("__builtin_spe_evlwwsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLATX);
+  def_builtin ("__builtin_spe_evlwhsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLATX);
+  def_builtin ("__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLATX);
+  def_builtin ("__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLATX);
+  def_builtin ("__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLATX);
+  def_builtin ("__builtin_spe_evldd", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDD);
+  def_builtin ("__builtin_spe_evldw", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDW);
+  def_builtin ("__builtin_spe_evldh", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDH);
+  def_builtin ("__builtin_spe_evlhhesplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLAT);
+  def_builtin ("__builtin_spe_evlhhossplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLAT);
+  def_builtin ("__builtin_spe_evlhhousplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLAT);
+  def_builtin ("__builtin_spe_evlwhe", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHE);
+  def_builtin ("__builtin_spe_evlwhos", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOS);
+  def_builtin ("__builtin_spe_evlwhou", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOU);
+  def_builtin ("__builtin_spe_evlwhsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLAT);
+  def_builtin ("__builtin_spe_evlwwsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLAT);
 
   /* Predicates.  */
-  d = (struct builtin_description *) bdesc_spe_predicates;
+  d = bdesc_spe_predicates;
   for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, d++)
     {
       tree type;
@@ -12389,11 +11922,11 @@  spe_init_builtins (void)
 	  gcc_unreachable ();
 	}
 
-      def_builtin (d->mask, d->name, type, d->code);
+      def_builtin (d->name, type, d->code);
     }
 
   /* Evsel predicates.  */
-  d = (struct builtin_description *) bdesc_spe_evsel;
+  d = bdesc_spe_evsel;
   for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, d++)
     {
       tree type;
@@ -12410,7 +11943,7 @@  spe_init_builtins (void)
 	  gcc_unreachable ();
 	}
 
-      def_builtin (d->mask, d->name, type, d->code);
+      def_builtin (d->name, type, d->code);
     }
 }
 
@@ -12442,11 +11975,11 @@  paired_init_builtins (void)
 			      NULL_TREE);
 
 
-  def_builtin (0, "__builtin_paired_lx", v2sf_ftype_long_pcfloat,
+  def_builtin ("__builtin_paired_lx", v2sf_ftype_long_pcfloat,
 	       PAIRED_BUILTIN_LX);
 
 
-  def_builtin (0, "__builtin_paired_stx", void_ftype_v2sf_long_pcfloat,
+  def_builtin ("__builtin_paired_stx", void_ftype_v2sf_long_pcfloat,
 	       PAIRED_BUILTIN_STX);
 
   /* Predicates.  */
@@ -12455,6 +11988,11 @@  paired_init_builtins (void)
     {
       tree type;
 
+      if (TARGET_DEBUG_BUILTIN)
+	fprintf (stderr, "paired pred #%d, insn = %s [%d], mode = %s\n",
+		 (int)i, get_insn_name (d->icode), (int)d->icode,
+		 GET_MODE_NAME (insn_data[d->icode].operand[1].mode));
+
       switch (insn_data[d->icode].operand[1].mode)
 	{
 	case V2SFmode:
@@ -12464,7 +12002,7 @@  paired_init_builtins (void)
 	  gcc_unreachable ();
 	}
 
-      def_builtin (d->mask, d->name, type, d->code);
+      def_builtin (d->name, type, d->code);
     }
 }
 
@@ -12472,9 +12010,9 @@  static void
 altivec_init_builtins (void)
 {
   const struct builtin_description *d;
-  const struct builtin_description_predicates *dp;
   size_t i;
   tree ftype;
+  tree decl;
 
   tree pvoid_type_node = build_pointer_type (void_type_node);
 
@@ -12599,125 +12137,120 @@  altivec_init_builtins (void)
 				pcvoid_type_node, integer_type_node,
 				integer_type_node, NULL_TREE);
 
-  def_builtin (MASK_ALTIVEC, "__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
-  def_builtin (MASK_ALTIVEC, "__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
-  def_builtin (MASK_ALTIVEC, "__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
-  def_builtin (MASK_ALTIVEC, "__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS);
-  def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL);
-  def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR);
-  def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX);
-  def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
-  def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
-  def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
-  def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
-  def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
-  def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
-  def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
-  def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
-  def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
-  def_builtin (MASK_ALTIVEC, "__builtin_vec_ld", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LD);
-  def_builtin (MASK_ALTIVEC, "__builtin_vec_lde", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDE);
-  def_builtin (MASK_ALTIVEC, "__builtin_vec_ldl", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDL);
-  def_builtin (MASK_ALTIVEC, "__builtin_vec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSL);
-  def_builtin (MASK_ALTIVEC, "__builtin_vec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSR);
-  def_builtin (MASK_ALTIVEC, "__builtin_vec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEBX);
-  def_builtin (MASK_ALTIVEC, "__builtin_vec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEHX);
-  def_builtin (MASK_ALTIVEC, "__builtin_vec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEWX);
-  def_builtin (MASK_ALTIVEC, "__builtin_vec_st", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_ST);
-  def_builtin (MASK_ALTIVEC, "__builtin_vec_ste", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STE);
-  def_builtin (MASK_ALTIVEC, "__builtin_vec_stl", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STL);
-  def_builtin (MASK_ALTIVEC, "__builtin_vec_stvewx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEWX);
-  def_builtin (MASK_ALTIVEC, "__builtin_vec_stvebx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEBX);
-  def_builtin (MASK_ALTIVEC, "__builtin_vec_stvehx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEHX);
+  def_builtin ("__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
+  def_builtin ("__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
+  def_builtin ("__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
+  def_builtin ("__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS);
+  def_builtin ("__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL);
+  def_builtin ("__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR);
+  def_builtin ("__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX);
+  def_builtin ("__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
+  def_builtin ("__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
+  def_builtin ("__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
+  def_builtin ("__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
+  def_builtin ("__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
+  def_builtin ("__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
+  def_builtin ("__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
+  def_builtin ("__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
+  def_builtin ("__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
+  def_builtin ("__builtin_vec_ld", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LD);
+  def_builtin ("__builtin_vec_lde", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDE);
+  def_builtin ("__builtin_vec_ldl", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDL);
+  def_builtin ("__builtin_vec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSL);
+  def_builtin ("__builtin_vec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSR);
+  def_builtin ("__builtin_vec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEBX);
+  def_builtin ("__builtin_vec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEHX);
+  def_builtin ("__builtin_vec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEWX);
+  def_builtin ("__builtin_vec_st", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_ST);
+  def_builtin ("__builtin_vec_ste", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STE);
+  def_builtin ("__builtin_vec_stl", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STL);
+  def_builtin ("__builtin_vec_stvewx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEWX);
+  def_builtin ("__builtin_vec_stvebx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEBX);
+  def_builtin ("__builtin_vec_stvehx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEHX);
 
-  def_builtin (MASK_VSX, "__builtin_vsx_lxvd2x_v2df", v2df_ftype_long_pcvoid,
+  def_builtin ("__builtin_vsx_lxvd2x_v2df", v2df_ftype_long_pcvoid,
 	       VSX_BUILTIN_LXVD2X_V2DF);
-  def_builtin (MASK_VSX, "__builtin_vsx_lxvd2x_v2di", v2di_ftype_long_pcvoid,
+  def_builtin ("__builtin_vsx_lxvd2x_v2di", v2di_ftype_long_pcvoid,
 	       VSX_BUILTIN_LXVD2X_V2DI);
-  def_builtin (MASK_VSX, "__builtin_vsx_lxvw4x_v4sf", v4sf_ftype_long_pcvoid,
+  def_builtin ("__builtin_vsx_lxvw4x_v4sf", v4sf_ftype_long_pcvoid,
 	       VSX_BUILTIN_LXVW4X_V4SF);
-  def_builtin (MASK_VSX, "__builtin_vsx_lxvw4x_v4si", v4si_ftype_long_pcvoid,
+  def_builtin ("__builtin_vsx_lxvw4x_v4si", v4si_ftype_long_pcvoid,
 	       VSX_BUILTIN_LXVW4X_V4SI);
-  def_builtin (MASK_VSX, "__builtin_vsx_lxvw4x_v8hi",
-	       v8hi_ftype_long_pcvoid, VSX_BUILTIN_LXVW4X_V8HI);
-  def_builtin (MASK_VSX, "__builtin_vsx_lxvw4x_v16qi",
-	       v16qi_ftype_long_pcvoid, VSX_BUILTIN_LXVW4X_V16QI);
-  def_builtin (MASK_VSX, "__builtin_vsx_stxvd2x_v2df",
-	       void_ftype_v2df_long_pvoid, VSX_BUILTIN_STXVD2X_V2DF);
-  def_builtin (MASK_VSX, "__builtin_vsx_stxvd2x_v2di",
-	       void_ftype_v2di_long_pvoid, VSX_BUILTIN_STXVD2X_V2DI);
-  def_builtin (MASK_VSX, "__builtin_vsx_stxvw4x_v4sf",
-	       void_ftype_v4sf_long_pvoid, VSX_BUILTIN_STXVW4X_V4SF);
-  def_builtin (MASK_VSX, "__builtin_vsx_stxvw4x_v4si",
-	       void_ftype_v4si_long_pvoid, VSX_BUILTIN_STXVW4X_V4SI);
-  def_builtin (MASK_VSX, "__builtin_vsx_stxvw4x_v8hi",
-	       void_ftype_v8hi_long_pvoid, VSX_BUILTIN_STXVW4X_V8HI);
-  def_builtin (MASK_VSX, "__builtin_vsx_stxvw4x_v16qi",
-	       void_ftype_v16qi_long_pvoid, VSX_BUILTIN_STXVW4X_V16QI);
-  def_builtin (MASK_VSX, "__builtin_vec_vsx_ld", opaque_ftype_long_pcvoid,
+  def_builtin ("__builtin_vsx_lxvw4x_v8hi", v8hi_ftype_long_pcvoid,
+	       VSX_BUILTIN_LXVW4X_V8HI);
+  def_builtin ("__builtin_vsx_lxvw4x_v16qi", v16qi_ftype_long_pcvoid,
+	       VSX_BUILTIN_LXVW4X_V16QI);
+  def_builtin ("__builtin_vsx_stxvd2x_v2df", void_ftype_v2df_long_pvoid,
+	       VSX_BUILTIN_STXVD2X_V2DF);
+  def_builtin ("__builtin_vsx_stxvd2x_v2di", void_ftype_v2di_long_pvoid,
+	       VSX_BUILTIN_STXVD2X_V2DI);
+  def_builtin ("__builtin_vsx_stxvw4x_v4sf", void_ftype_v4sf_long_pvoid,
+	       VSX_BUILTIN_STXVW4X_V4SF);
+  def_builtin ("__builtin_vsx_stxvw4x_v4si", void_ftype_v4si_long_pvoid,
+	       VSX_BUILTIN_STXVW4X_V4SI);
+  def_builtin ("__builtin_vsx_stxvw4x_v8hi", void_ftype_v8hi_long_pvoid,
+	       VSX_BUILTIN_STXVW4X_V8HI);
+  def_builtin ("__builtin_vsx_stxvw4x_v16qi", void_ftype_v16qi_long_pvoid,
+	       VSX_BUILTIN_STXVW4X_V16QI);
+  def_builtin ("__builtin_vec_vsx_ld", opaque_ftype_long_pcvoid,
 	       VSX_BUILTIN_VEC_LD);
-  def_builtin (MASK_VSX, "__builtin_vec_vsx_st", void_ftype_opaque_long_pvoid,
+  def_builtin ("__builtin_vec_vsx_st", void_ftype_opaque_long_pvoid,
 	       VSX_BUILTIN_VEC_ST);
 
-  if (rs6000_cpu == PROCESSOR_CELL)
-    {
-      def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvlx",  v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVLX);
-      def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvlxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVLXL);
-      def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvrx",  v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVRX);
-      def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvrxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVRXL);
-
-      def_builtin (MASK_ALTIVEC, "__builtin_vec_lvlx",  v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVLX);
-      def_builtin (MASK_ALTIVEC, "__builtin_vec_lvlxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVLXL);
-      def_builtin (MASK_ALTIVEC, "__builtin_vec_lvrx",  v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVRX);
-      def_builtin (MASK_ALTIVEC, "__builtin_vec_lvrxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVRXL);
-
-      def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvlx",  void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVLX);
-      def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvlxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVLXL);
-      def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvrx",  void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVRX);
-      def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvrxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVRXL);
-
-      def_builtin (MASK_ALTIVEC, "__builtin_vec_stvlx",  void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVLX);
-      def_builtin (MASK_ALTIVEC, "__builtin_vec_stvlxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVLXL);
-      def_builtin (MASK_ALTIVEC, "__builtin_vec_stvrx",  void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVRX);
-      def_builtin (MASK_ALTIVEC, "__builtin_vec_stvrxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVRXL);
-    }
-  def_builtin (MASK_ALTIVEC, "__builtin_vec_step", int_ftype_opaque, ALTIVEC_BUILTIN_VEC_STEP);
-  def_builtin (MASK_ALTIVEC, "__builtin_vec_splats", opaque_ftype_opaque, ALTIVEC_BUILTIN_VEC_SPLATS);
-  def_builtin (MASK_ALTIVEC, "__builtin_vec_promote", opaque_ftype_opaque, ALTIVEC_BUILTIN_VEC_PROMOTE);
-
-  def_builtin (MASK_ALTIVEC, "__builtin_vec_sld", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_SLD);
-  def_builtin (MASK_ALTIVEC, "__builtin_vec_splat", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_SPLAT);
-  def_builtin (MASK_ALTIVEC, "__builtin_vec_extract", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_EXTRACT);
-  def_builtin (MASK_ALTIVEC, "__builtin_vec_insert", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_INSERT);
-  def_builtin (MASK_ALTIVEC, "__builtin_vec_vspltw", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTW);
-  def_builtin (MASK_ALTIVEC, "__builtin_vec_vsplth", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTH);
-  def_builtin (MASK_ALTIVEC, "__builtin_vec_vspltb", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTB);
-  def_builtin (MASK_ALTIVEC, "__builtin_vec_ctf", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTF);
-  def_builtin (MASK_ALTIVEC, "__builtin_vec_vcfsx", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFSX);
-  def_builtin (MASK_ALTIVEC, "__builtin_vec_vcfux", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFUX);
-  def_builtin (MASK_ALTIVEC, "__builtin_vec_cts", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTS);
-  def_builtin (MASK_ALTIVEC, "__builtin_vec_ctu", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTU);
+  def_builtin ("__builtin_vec_step", int_ftype_opaque, ALTIVEC_BUILTIN_VEC_STEP);
+  def_builtin ("__builtin_vec_splats", opaque_ftype_opaque, ALTIVEC_BUILTIN_VEC_SPLATS);
+  def_builtin ("__builtin_vec_promote", opaque_ftype_opaque, ALTIVEC_BUILTIN_VEC_PROMOTE);
+
+  def_builtin ("__builtin_vec_sld", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_SLD);
+  def_builtin ("__builtin_vec_splat", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_SPLAT);
+  def_builtin ("__builtin_vec_extract", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_EXTRACT);
+  def_builtin ("__builtin_vec_insert", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_INSERT);
+  def_builtin ("__builtin_vec_vspltw", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTW);
+  def_builtin ("__builtin_vec_vsplth", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTH);
+  def_builtin ("__builtin_vec_vspltb", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTB);
+  def_builtin ("__builtin_vec_ctf", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTF);
+  def_builtin ("__builtin_vec_vcfsx", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFSX);
+  def_builtin ("__builtin_vec_vcfux", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFUX);
+  def_builtin ("__builtin_vec_cts", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTS);
+  def_builtin ("__builtin_vec_ctu", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTU);
+
+  /* Cell builtins.  */
+  def_builtin ("__builtin_altivec_lvlx",  v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVLX);
+  def_builtin ("__builtin_altivec_lvlxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVLXL);
+  def_builtin ("__builtin_altivec_lvrx",  v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVRX);
+  def_builtin ("__builtin_altivec_lvrxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVRXL);
+
+  def_builtin ("__builtin_vec_lvlx",  v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVLX);
+  def_builtin ("__builtin_vec_lvlxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVLXL);
+  def_builtin ("__builtin_vec_lvrx",  v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVRX);
+  def_builtin ("__builtin_vec_lvrxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVRXL);
+
+  def_builtin ("__builtin_altivec_stvlx",  void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVLX);
+  def_builtin ("__builtin_altivec_stvlxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVLXL);
+  def_builtin ("__builtin_altivec_stvrx",  void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVRX);
+  def_builtin ("__builtin_altivec_stvrxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVRXL);
+
+  def_builtin ("__builtin_vec_stvlx",  void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVLX);
+  def_builtin ("__builtin_vec_stvlxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVLXL);
+  def_builtin ("__builtin_vec_stvrx",  void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVRX);
+  def_builtin ("__builtin_vec_stvrxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVRXL);
 
   /* Add the DST variants.  */
   d = bdesc_dst;
   for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
-    def_builtin (d->mask, d->name, void_ftype_pcvoid_int_int, d->code);
+    def_builtin (d->name, void_ftype_pcvoid_int_int, d->code);
 
   /* Initialize the predicates.  */
-  dp = bdesc_altivec_preds;
-  for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
+  d = bdesc_altivec_preds;
+  for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, d++)
     {
       enum machine_mode mode1;
       tree type;
-      bool is_overloaded = ((dp->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
-			     && dp->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST)
-			    || (dp->code >= VSX_BUILTIN_OVERLOADED_FIRST
-				&& dp->code <= VSX_BUILTIN_OVERLOADED_LAST));
 
-      if (is_overloaded)
+      if (rs6000_overloaded_builtin_p (d->code))
 	mode1 = VOIDmode;
       else
-	mode1 = insn_data[dp->icode].operand[1].mode;
+	mode1 = insn_data[d->icode].operand[1].mode;
 
       switch (mode1)
 	{
@@ -12743,7 +12276,7 @@  altivec_init_builtins (void)
 	  gcc_unreachable ();
 	}
 
-      def_builtin (dp->mask, dp->name, type, dp->code);
+      def_builtin (d->name, type, d->code);
     }
 
   /* Initialize the abs* operators.  */
@@ -12776,31 +12309,25 @@  altivec_init_builtins (void)
 	  gcc_unreachable ();
 	}
 
-      def_builtin (d->mask, d->name, type, d->code);
+      def_builtin (d->name, type, d->code);
     }
 
-  if (TARGET_ALTIVEC)
-    {
-      tree decl;
-
-      /* Initialize target builtin that implements
-         targetm.vectorize.builtin_mask_for_load.  */
+  /* Initialize target builtin that implements
+     targetm.vectorize.builtin_mask_for_load.  */
 
-      decl = add_builtin_function ("__builtin_altivec_mask_for_load",
-				   v16qi_ftype_long_pcvoid,
-				   ALTIVEC_BUILTIN_MASK_FOR_LOAD,
-				   BUILT_IN_MD, NULL, NULL_TREE);
-      TREE_READONLY (decl) = 1;
-      /* Record the decl. Will be used by rs6000_builtin_mask_for_load.  */
-      altivec_builtin_mask_for_load = decl;
-    }
+  decl = add_builtin_function ("__builtin_altivec_mask_for_load",
+			       v16qi_ftype_long_pcvoid,
+			       ALTIVEC_BUILTIN_MASK_FOR_LOAD,
+			       BUILT_IN_MD, NULL, NULL_TREE);
+  TREE_READONLY (decl) = 1;
+  /* Record the decl. Will be used by rs6000_builtin_mask_for_load.  */
+  altivec_builtin_mask_for_load = decl;
 
   /* Access to the vec_init patterns.  */
   ftype = build_function_type_list (V4SI_type_node, integer_type_node,
 				    integer_type_node, integer_type_node,
 				    integer_type_node, NULL_TREE);
-  def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v4si", ftype,
-	       ALTIVEC_BUILTIN_VEC_INIT_V4SI);
+  def_builtin ("__builtin_vec_init_v4si", ftype, ALTIVEC_BUILTIN_VEC_INIT_V4SI);
 
   ftype = build_function_type_list (V8HI_type_node, short_integer_type_node,
 				    short_integer_type_node,
@@ -12810,8 +12337,7 @@  altivec_init_builtins (void)
 				    short_integer_type_node,
 				    short_integer_type_node,
 				    short_integer_type_node, NULL_TREE);
-  def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v8hi", ftype,
-	       ALTIVEC_BUILTIN_VEC_INIT_V8HI);
+  def_builtin ("__builtin_vec_init_v8hi", ftype, ALTIVEC_BUILTIN_VEC_INIT_V8HI);
 
   ftype = build_function_type_list (V16QI_type_node, char_type_node,
 				    char_type_node, char_type_node,
@@ -12822,101 +12348,78 @@  altivec_init_builtins (void)
 				    char_type_node, char_type_node,
 				    char_type_node, char_type_node,
 				    char_type_node, NULL_TREE);
-  def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v16qi", ftype,
+  def_builtin ("__builtin_vec_init_v16qi", ftype,
 	       ALTIVEC_BUILTIN_VEC_INIT_V16QI);
 
   ftype = build_function_type_list (V4SF_type_node, float_type_node,
 				    float_type_node, float_type_node,
 				    float_type_node, NULL_TREE);
-  def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v4sf", ftype,
-	       ALTIVEC_BUILTIN_VEC_INIT_V4SF);
+  def_builtin ("__builtin_vec_init_v4sf", ftype, ALTIVEC_BUILTIN_VEC_INIT_V4SF);
 
-  if (TARGET_VSX)
-    {
-      ftype = build_function_type_list (V2DF_type_node, double_type_node,
-					double_type_node, NULL_TREE);
-      def_builtin (MASK_VSX, "__builtin_vec_init_v2df", ftype,
-		   VSX_BUILTIN_VEC_INIT_V2DF);
-
-      ftype = build_function_type_list (V2DI_type_node, intDI_type_node,
-					intDI_type_node, NULL_TREE);
-      def_builtin (MASK_VSX, "__builtin_vec_init_v2di", ftype,
-		   VSX_BUILTIN_VEC_INIT_V2DI);
-    }
+  /* VSX builtins.  */
+  ftype = build_function_type_list (V2DF_type_node, double_type_node,
+				    double_type_node, NULL_TREE);
+  def_builtin ("__builtin_vec_init_v2df", ftype, VSX_BUILTIN_VEC_INIT_V2DF);
+
+  ftype = build_function_type_list (V2DI_type_node, intDI_type_node,
+				    intDI_type_node, NULL_TREE);
+  def_builtin ("__builtin_vec_init_v2di", ftype, VSX_BUILTIN_VEC_INIT_V2DI);
 
   /* Access to the vec_set patterns.  */
   ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
 				    intSI_type_node,
 				    integer_type_node, NULL_TREE);
-  def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v4si", ftype,
-	       ALTIVEC_BUILTIN_VEC_SET_V4SI);
+  def_builtin ("__builtin_vec_set_v4si", ftype, ALTIVEC_BUILTIN_VEC_SET_V4SI);
 
   ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
 				    intHI_type_node,
 				    integer_type_node, NULL_TREE);
-  def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v8hi", ftype,
-	       ALTIVEC_BUILTIN_VEC_SET_V8HI);
+  def_builtin ("__builtin_vec_set_v8hi", ftype, ALTIVEC_BUILTIN_VEC_SET_V8HI);
 
   ftype = build_function_type_list (V16QI_type_node, V16QI_type_node,
 				    intQI_type_node,
 				    integer_type_node, NULL_TREE);
-  def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v16qi", ftype,
-	       ALTIVEC_BUILTIN_VEC_SET_V16QI);
+  def_builtin ("__builtin_vec_set_v16qi", ftype, ALTIVEC_BUILTIN_VEC_SET_V16QI);
 
   ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
 				    float_type_node,
 				    integer_type_node, NULL_TREE);
-  def_builtin (MASK_ALTIVEC|MASK_VSX, "__builtin_vec_set_v4sf", ftype,
-	       ALTIVEC_BUILTIN_VEC_SET_V4SF);
+  def_builtin ("__builtin_vec_set_v4sf", ftype, ALTIVEC_BUILTIN_VEC_SET_V4SF);
 
-  if (TARGET_VSX)
-    {
-      ftype = build_function_type_list (V2DF_type_node, V2DF_type_node,
-					double_type_node,
-					integer_type_node, NULL_TREE);
-      def_builtin (MASK_VSX, "__builtin_vec_set_v2df", ftype,
-		   VSX_BUILTIN_VEC_SET_V2DF);
-
-      ftype = build_function_type_list (V2DI_type_node, V2DI_type_node,
-					intDI_type_node,
-					integer_type_node, NULL_TREE);
-      def_builtin (MASK_VSX, "__builtin_vec_set_v2di", ftype,
-		   VSX_BUILTIN_VEC_SET_V2DI);
-    }
+  ftype = build_function_type_list (V2DF_type_node, V2DF_type_node,
+				    double_type_node,
+				    integer_type_node, NULL_TREE);
+  def_builtin ("__builtin_vec_set_v2df", ftype, VSX_BUILTIN_VEC_SET_V2DF);
+
+  ftype = build_function_type_list (V2DI_type_node, V2DI_type_node,
+				    intDI_type_node,
+				    integer_type_node, NULL_TREE);
+  def_builtin ("__builtin_vec_set_v2di", ftype, VSX_BUILTIN_VEC_SET_V2DI);
 
   /* Access to the vec_extract patterns.  */
   ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
 				    integer_type_node, NULL_TREE);
-  def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v4si", ftype,
-	       ALTIVEC_BUILTIN_VEC_EXT_V4SI);
+  def_builtin ("__builtin_vec_ext_v4si", ftype, ALTIVEC_BUILTIN_VEC_EXT_V4SI);
 
   ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
 				    integer_type_node, NULL_TREE);
-  def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v8hi", ftype,
-	       ALTIVEC_BUILTIN_VEC_EXT_V8HI);
+  def_builtin ("__builtin_vec_ext_v8hi", ftype, ALTIVEC_BUILTIN_VEC_EXT_V8HI);
 
   ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
 				    integer_type_node, NULL_TREE);
-  def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v16qi", ftype,
-	       ALTIVEC_BUILTIN_VEC_EXT_V16QI);
+  def_builtin ("__builtin_vec_ext_v16qi", ftype, ALTIVEC_BUILTIN_VEC_EXT_V16QI);
 
   ftype = build_function_type_list (float_type_node, V4SF_type_node,
 				    integer_type_node, NULL_TREE);
-  def_builtin (MASK_ALTIVEC|MASK_VSX, "__builtin_vec_ext_v4sf", ftype,
-	       ALTIVEC_BUILTIN_VEC_EXT_V4SF);
+  def_builtin ("__builtin_vec_ext_v4sf", ftype, ALTIVEC_BUILTIN_VEC_EXT_V4SF);
 
-  if (TARGET_VSX)
-    {
-      ftype = build_function_type_list (double_type_node, V2DF_type_node,
-					integer_type_node, NULL_TREE);
-      def_builtin (MASK_VSX, "__builtin_vec_ext_v2df", ftype,
-		   VSX_BUILTIN_VEC_EXT_V2DF);
-
-      ftype = build_function_type_list (intDI_type_node, V2DI_type_node,
-					integer_type_node, NULL_TREE);
-      def_builtin (MASK_VSX, "__builtin_vec_ext_v2di", ftype,
-		   VSX_BUILTIN_VEC_EXT_V2DI);
-    }
+  ftype = build_function_type_list (double_type_node, V2DF_type_node,
+				    integer_type_node, NULL_TREE);
+  def_builtin ("__builtin_vec_ext_v2df", ftype, VSX_BUILTIN_VEC_EXT_V2DF);
+
+  ftype = build_function_type_list (intDI_type_node, V2DI_type_node,
+				    integer_type_node, NULL_TREE);
+  def_builtin ("__builtin_vec_ext_v2di", ftype, VSX_BUILTIN_VEC_EXT_V2DI);
 }
 
 /* Hash function for builtin functions with up to 3 arguments and a return
@@ -13043,13 +12546,13 @@  builtin_function_type (enum machine_mode
 
       /* unsigned args, signed return.  */
     case VSX_BUILTIN_XVCVUXDDP_UNS:
-    case VECTOR_BUILTIN_UNSFLOAT_V4SI_V4SF:
+    case ALTIVEC_BUILTIN_UNSFLOAT_V4SI_V4SF:
       h.uns_p[1] = 1;
       break;
 
       /* signed args, unsigned return.  */
     case VSX_BUILTIN_XVCVDPUXDS_UNS:
-    case VECTOR_BUILTIN_FIXUNS_V4SF_V4SI:
+    case ALTIVEC_BUILTIN_FIXUNS_V4SF_V4SI:
       h.uns_p[0] = 1;
       break;
 
@@ -13116,6 +12619,7 @@  rs6000_common_init_builtins (void)
   tree v2si_ftype_qi = NULL_TREE;
   tree v2si_ftype_v2si_qi = NULL_TREE;
   tree v2si_ftype_int_qi = NULL_TREE;
+  unsigned builtin_mask = rs6000_builtin_mask;
 
   if (!TARGET_PAIRED_FLOAT)
     {
@@ -13123,21 +12627,30 @@  rs6000_common_init_builtins (void)
       builtin_mode_to_type[V2SFmode][0] = opaque_V2SF_type_node;
     }
 
+  /* Paired and SPE builtins are only available if you build a compiler with
+     the appropriate options, so only create those builtins with the
+     appropriate compiler option.  Create Altivec and VSX builtins on machines
+     with at least the general purpose extensions (970 and newer) to allow the
+     use of the target attribute..  */
+
+  if (TARGET_EXTRA_BUILTINS)
+    builtin_mask |= RS6000_BTM_COMMON;
+
   /* Add the ternary operators.  */
   d = bdesc_3arg;
   for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
     {
       tree type;
-      int mask = d->mask;
+      unsigned mask = d->mask;
 
-      if ((mask != 0 && (mask & target_flags) == 0)
-	  || (mask == 0 && !TARGET_PAIRED_FLOAT))
-	continue;
+      if ((mask & builtin_mask) != mask)
+	{
+	  if (TARGET_DEBUG_BUILTIN)
+	    fprintf (stderr, "rs6000_builtin, skip ternary %s\n", d->name);
+	  continue;
+	}
 
-      if ((d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
-	   && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST)
-	  || (d->code >= VSX_BUILTIN_OVERLOADED_FIRST
-	      && d->code <= VSX_BUILTIN_OVERLOADED_LAST))
+      if (rs6000_overloaded_builtin_p (d->code))
 	{
 	  if (! (type = opaque_ftype_opaque_opaque_opaque))
 	    type = opaque_ftype_opaque_opaque_opaque
@@ -13160,7 +12673,7 @@  rs6000_common_init_builtins (void)
 					d->code, d->name);
 	}
 
-      def_builtin (d->mask, d->name, type, d->code);
+      def_builtin (d->name, type, d->code);
     }
 
   /* Add the binary operators.  */
@@ -13169,16 +12682,16 @@  rs6000_common_init_builtins (void)
     {
       enum machine_mode mode0, mode1, mode2;
       tree type;
-      int mask = d->mask;
+      unsigned mask = d->mask;
 
-      if ((mask != 0 && (mask & target_flags) == 0)
-	  || (mask == 0 && !TARGET_PAIRED_FLOAT))
-	continue;
+      if ((mask & builtin_mask) != mask)
+	{
+	  if (TARGET_DEBUG_BUILTIN)
+	    fprintf (stderr, "rs6000_builtin, skip binary %s\n", d->name);
+	  continue;
+	}
 
-      if ((d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
-	   && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST)
-	  || (d->code >= VSX_BUILTIN_OVERLOADED_FIRST
-	      && d->code <= VSX_BUILTIN_OVERLOADED_LAST))
+      if (rs6000_overloaded_builtin_p (d->code))
 	{
 	  if (! (type = opaque_ftype_opaque_opaque))
 	    type = opaque_ftype_opaque_opaque
@@ -13223,25 +12736,25 @@  rs6000_common_init_builtins (void)
 					  d->code, d->name);
 	}
 
-      def_builtin (d->mask, d->name, type, d->code);
+      def_builtin (d->name, type, d->code);
     }
 
   /* Add the simple unary operators.  */
-  d = (struct builtin_description *) bdesc_1arg;
+  d = bdesc_1arg;
   for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
     {
       enum machine_mode mode0, mode1;
       tree type;
-      int mask = d->mask;
+      unsigned mask = d->mask;
 
-      if ((mask != 0 && (mask & target_flags) == 0)
-	  || (mask == 0 && !TARGET_PAIRED_FLOAT))
-	continue;
+      if ((mask & builtin_mask) != mask)
+	{
+	  if (TARGET_DEBUG_BUILTIN)
+	    fprintf (stderr, "rs6000_builtin, skip unary %s\n", d->name);
+	  continue;
+	}
 
-      if ((d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
-	   && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST)
-	  || (d->code >= VSX_BUILTIN_OVERLOADED_FIRST
-	      && d->code <= VSX_BUILTIN_OVERLOADED_LAST))
+      if (rs6000_overloaded_builtin_p (d->code))
 	{
 	  if (! (type = opaque_ftype_opaque))
 	    type = opaque_ftype_opaque
@@ -13272,7 +12785,7 @@  rs6000_common_init_builtins (void)
 					  d->code, d->name);
 	}
 
-      def_builtin (d->mask, d->name, type, d->code);
+      def_builtin (d->name, type, d->code);
     }
 }
 
@@ -26334,13 +25847,13 @@  rs6000_builtin_reciprocal (unsigned int 
 	if (!RS6000_RECIP_AUTO_RSQRTE_P (V2DFmode))
 	  return NULL_TREE;
 
-	return rs6000_builtin_decls[VSX_BUILTIN_VEC_RSQRT_V2DF];
+	return rs6000_builtin_decls[VSX_BUILTIN_RSQRT_2DF];
 
       case VSX_BUILTIN_XVSQRTSP:
 	if (!RS6000_RECIP_AUTO_RSQRTE_P (V4SFmode))
 	  return NULL_TREE;
 
-	return rs6000_builtin_decls[VSX_BUILTIN_VEC_RSQRT_V4SF];
+	return rs6000_builtin_decls[VSX_BUILTIN_RSQRT_4SF];
 
       default:
 	return NULL_TREE;
@@ -27213,6 +26726,22 @@  static struct rs6000_opt_mask const rs60
   { "string",		MASK_STRING,		false, false },
 };
 
+/* Builtin mask mapping for printing the flags.  */
+static struct rs6000_opt_mask const rs6000_builtin_mask_names[] =
+{
+  { "altivec",		 RS6000_BTM_ALTIVEC,	false, false },
+  { "vsx",		 RS6000_BTM_VSX,	false, false },
+  { "spe",		 RS6000_BTM_SPE,	false, false },
+  { "paired",		 RS6000_BTM_PAIRED,	false, false },
+  { "fre",		 RS6000_BTM_FRE,	false, false },
+  { "fres",		 RS6000_BTM_FRES,	false, false },
+  { "frsqrte",		 RS6000_BTM_FRSQRTE,	false, false },
+  { "frsqrtes",		 RS6000_BTM_FRSQRTES,	false, false },
+  { "popcntd",		 RS6000_BTM_POPCNTD,	false, false },
+  { "powerpc",		 RS6000_BTM_POWERPC,	false, false },
+  { "cell",		 RS6000_BTM_CELL,	false, false },
+};
+
 /* Option variables that we want to support inside attribute((target)) and
    #pragma GCC target operations.  */
 
@@ -27515,7 +27044,11 @@  rs6000_valid_attribute_p (tree fndecl,
 bool
 rs6000_pragma_target_parse (tree args, tree pop_target)
 {
+  tree prev_tree = build_target_option_node ();
   tree cur_tree;
+  struct cl_target_option *prev_opt, *cur_opt;
+  unsigned prev_bumask, cur_bumask, diff_bumask;
+  int prev_flags, cur_flags, diff_flags;
   bool ret;
 
   if (TARGET_DEBUG_TARGET)
@@ -27552,11 +27085,43 @@  rs6000_pragma_target_parse (tree args, t
       cur_tree = build_target_option_node ();
 
       if (!cur_tree)
-	ret = false;
+	{
+	  if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
+	    fprintf (stderr, "build_target_option_node returned NULL\n");
+	  return false;
+	}
     }
 
-  if (cur_tree)
-    target_option_current_node = cur_tree;
+  target_option_current_node = cur_tree;
+
+  /* If we have the preprocessor linked in (i.e. C or C++ languages), possibly
+     change the macros that are defined.  */
+  if (rs6000_target_modify_macros_ptr)
+    {
+      prev_opt    = TREE_TARGET_OPTION (prev_tree);
+      prev_bumask = prev_opt->x_rs6000_builtin_mask;
+      prev_flags  = prev_opt->x_target_flags;
+
+      cur_opt     = TREE_TARGET_OPTION (cur_tree);
+      cur_flags   = cur_opt->x_target_flags;
+      cur_bumask  = cur_opt->x_rs6000_builtin_mask;
+
+      diff_bumask = (prev_bumask ^ cur_bumask);
+      diff_flags  = (prev_flags  ^ cur_flags);
+
+      if ((diff_flags != 0) || (diff_bumask != 0))
+	{
+	  /* Delete old macros.  */
+	  rs6000_target_modify_macros_ptr (false,
+					   prev_flags & diff_flags,
+					   prev_bumask & diff_bumask);
+
+	  /* Define new macros.  */
+	  rs6000_target_modify_macros_ptr (true,
+					   cur_flags & diff_flags,
+					   cur_bumask & diff_bumask);
+	}
+    }
 
   return ret;
 }
@@ -27665,6 +27230,7 @@  rs6000_function_specific_print (FILE *fi
 {
   size_t i;
   int flags = ptr->x_target_flags;
+  unsigned bu_mask = ptr->x_rs6000_builtin_mask;
 
   /* Print the various mask options.  */
   for (i = 0; i < ARRAY_SIZE (rs6000_opt_masks); i++)
@@ -27684,6 +27250,15 @@  rs6000_function_specific_print (FILE *fi
 	fprintf (file, "%*s-m%s\n", indent, "",
 		 rs6000_opt_vars[i].name);
     }
+
+  /* Print the various builtin flags.  */
+  fprintf (file, "%*sbuiltin mask = 0x%x\n", indent, "", bu_mask);
+  for (i = 0; i < ARRAY_SIZE (rs6000_builtin_mask_names); i++)
+    if ((bu_mask & rs6000_builtin_mask_names[i].mask) != 0)
+      {
+	fprintf (file, "%*s%s builtins supported\n", indent, "",
+		 rs6000_builtin_mask_names[i].name);
+      }
 }
 
 
Index: gcc/config/rs6000/rs6000.h
===================================================================
--- gcc/config/rs6000/rs6000.h	(.../trunk)	(revision 181085)
+++ gcc/config/rs6000/rs6000.h	(.../branches/ibm/builtin2)	(revision 181121)
@@ -373,12 +373,14 @@  extern const char *host_detect_local_cpu
 #define MASK_DEBUG_ADDR		0x08	/* debug memory addressing */
 #define MASK_DEBUG_COST		0x10	/* debug rtx codes */
 #define MASK_DEBUG_TARGET	0x20	/* debug target attribute/pragma */
+#define MASK_DEBUG_BUILTIN	0x40	/* debug builtins */
 #define MASK_DEBUG_ALL		(MASK_DEBUG_STACK \
 				 | MASK_DEBUG_ARG \
 				 | MASK_DEBUG_REG \
 				 | MASK_DEBUG_ADDR \
 				 | MASK_DEBUG_COST \
-				 | MASK_DEBUG_TARGET)
+				 | MASK_DEBUG_TARGET \
+				 | MASK_DEBUG_BUILTIN)
 
 #define	TARGET_DEBUG_STACK	(rs6000_debug & MASK_DEBUG_STACK)
 #define	TARGET_DEBUG_ARG	(rs6000_debug & MASK_DEBUG_ARG)
@@ -386,6 +388,7 @@  extern const char *host_detect_local_cpu
 #define TARGET_DEBUG_ADDR	(rs6000_debug & MASK_DEBUG_ADDR)
 #define TARGET_DEBUG_COST	(rs6000_debug & MASK_DEBUG_COST)
 #define TARGET_DEBUG_TARGET	(rs6000_debug & MASK_DEBUG_TARGET)
+#define TARGET_DEBUG_BUILTIN	(rs6000_debug & MASK_DEBUG_BUILTIN)
 
 extern enum rs6000_vector rs6000_vector_unit[];
 
@@ -480,6 +483,24 @@  extern int rs6000_vector_align[];
 #define TARGET_FCTIDUZ	TARGET_POPCNTD
 #define TARGET_FCTIWUZ	TARGET_POPCNTD
 
+/* For power systems, we want to enable Altivec and VSX builtins even if the
+   user did not use -maltivec or -mvsx to allow the builtins to be used inside
+   of #pragma GCC target or the target attribute to change the code level for a
+   given system.  The SPE and Paired builtins are only enabled if you configure
+   the compiler for those builtins, and those machines don't support altivec or
+   VSX.  */
+
+#define TARGET_EXTRA_BUILTINS	(!TARGET_SPE && !TARGET_PAIRED_FLOAT	 \
+				 && ((TARGET_POWERPC64			 \
+				      || TARGET_PPC_GPOPT /* 970 */	 \
+				      || TARGET_POPCNTB	  /* ISA 2.02 */ \
+				      || TARGET_CMPB	  /* ISA 2.05 */ \
+				      || TARGET_POPCNTD	  /* ISA 2.06 */ \
+				      || TARGET_ALTIVEC			 \
+				      || TARGET_VSX)))
+
+
+
 /* E500 processors only support plain "sync", not lwsync.  */
 #define TARGET_NO_LWSYNC TARGET_E500
 
@@ -531,6 +552,7 @@  extern unsigned char rs6000_recip_bits[]
   c_register_pragma (0, "longcall", rs6000_pragma_longcall);	\
   targetm.target_option.pragma_parse = rs6000_pragma_target_parse; \
   targetm.resolve_overloaded_builtin = altivec_resolve_overloaded_builtin; \
+  rs6000_target_modify_macros_ptr = rs6000_target_modify_macros; \
 } while (0)
 
 /* Target #defines.  */
@@ -2271,24 +2293,83 @@  extern char rs6000_reg_names[][8];	/* re
 /* General flags.  */
 extern int frame_pointer_needed;
 
-/* Classification of the builtin functions to properly set the declaration tree
-   flags.  */
-enum rs6000_btc
-{
-  RS6000_BTC_MISC,		/* assume builtin can do anything */
-  RS6000_BTC_CONST,		/* builtin is a 'const' function.  */
-  RS6000_BTC_PURE,		/* builtin is a 'pure' function.  */
-  RS6000_BTC_FP_PURE		/* builtin is 'pure' if rounding math.  */
-};
+/* Classification of the builtin functions as to which switches enable the
+   builtin, and what attributes it should have.  We used to use the target
+   flags macros, but we've run out of bits, so we now map the options into new
+   settings used here.  */
+
+/* Builtin attributes.  */
+#define RS6000_BTC_SPECIAL	0x00000000	/* Special function.  */
+#define RS6000_BTC_UNARY	0x00000001	/* normal unary function.  */
+#define RS6000_BTC_BINARY	0x00000002	/* normal binary function.  */
+#define RS6000_BTC_TERNARY	0x00000003	/* normal ternary function.  */
+#define RS6000_BTC_PREDICATE	0x00000004	/* predicate function.  */
+#define RS6000_BTC_ABS		0x00000005	/* Altivec/VSX ABS function.  */
+#define RS6000_BTC_EVSEL	0x00000006	/* SPE EVSEL function.  */
+#define RS6000_BTC_DST		0x00000007	/* Altivec DST function.  */
+#define RS6000_BTC_TYPE_MASK	0x0000000f	/* Mask to isolate types */
+
+#define RS6000_BTC_MISC		0x00000000	/* No special attributes.  */
+#define RS6000_BTC_CONST	0x00000100	/* uses no global state.  */
+#define RS6000_BTC_PURE		0x00000200	/* reads global state/mem.  */
+#define RS6000_BTC_FP		0x00000400	/* depends on rounding mode.  */
+#define RS6000_BTC_ATTR_MASK	0x00000700	/* Mask of the attributes.  */
+
+/* Miscellaneous information.  */
+#define RS6000_BTC_OVERLOADED	0x4000000	/* function is overloaded.  */
 
 /* Convenience macros to document the instruction type.  */
-#define RS6000_BTC_MEM	RS6000_BTC_MISC	/* load/store touches memory */
-#define RS6000_BTC_SAT	RS6000_BTC_MISC	/* VMX saturate sets VSCR register */
+#define RS6000_BTC_MEM		RS6000_BTC_MISC	/* load/store touches mem.  */
+#define RS6000_BTC_SAT		RS6000_BTC_MISC	/* saturate sets VSCR.  */
 
-#undef RS6000_BUILTIN
-#undef RS6000_BUILTIN_EQUATE
-#define RS6000_BUILTIN(NAME, TYPE) NAME,
-#define RS6000_BUILTIN_EQUATE(NAME, VALUE) NAME = VALUE,
+/* Builtin targets.  For now, we reuse the masks for those options that are in
+   target flags, and pick two random bits for SPE and paired which aren't in
+   target_flags.  */
+#define RS6000_BTM_ALTIVEC	MASK_ALTIVEC	/* VMX/altivec vectors.  */
+#define RS6000_BTM_VSX		MASK_VSX	/* VSX (vector/scalar).  */
+#define RS6000_BTM_SPE		MASK_STRING	/* E500 */
+#define RS6000_BTM_PAIRED	MASK_MULHW	/* 750CL paired insns.  */
+#define RS6000_BTM_FRE		MASK_POPCNTB	/* FRE instruction.  */
+#define RS6000_BTM_FRES		MASK_PPC_GFXOPT	/* FRES instruction.  */
+#define RS6000_BTM_FRSQRTE	MASK_PPC_GFXOPT	/* FRSQRTE instruction.  */
+#define RS6000_BTM_FRSQRTES	MASK_POPCNTB	/* FRSQRTES instruction.  */
+#define RS6000_BTM_POPCNTD	MASK_POPCNTD	/* Target supports ISA 2.06.  */
+#define RS6000_BTM_POWERPC	MASK_POWERPC	/* Target is powerpc.  */
+#define RS6000_BTM_CELL		MASK_FPRND	/* Target is cell powerpc.  */
+
+#define RS6000_BTM_COMMON	(RS6000_BTM_ALTIVEC			\
+				 | RS6000_BTM_VSX			\
+				 | RS6000_BTM_FRE			\
+				 | RS6000_BTM_FRES			\
+				 | RS6000_BTM_FRSQRTE			\
+				 | RS6000_BTM_FRSQRTES			\
+				 | RS6000_BTM_POPCNTD			\
+				 | RS6000_BTM_POWERPC			\
+				 | RS6000_BTM_CELL)
+
+/* Define builtin enum index.  */
+
+#undef RS6000_BUILTIN_1
+#undef RS6000_BUILTIN_2
+#undef RS6000_BUILTIN_3
+#undef RS6000_BUILTIN_A
+#undef RS6000_BUILTIN_D
+#undef RS6000_BUILTIN_E
+#undef RS6000_BUILTIN_P
+#undef RS6000_BUILTIN_Q
+#undef RS6000_BUILTIN_S
+#undef RS6000_BUILTIN_X
+
+#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
+#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
+#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
+#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
+#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
+#define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
+#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
+#define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
+#define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
+#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
 
 enum rs6000_builtins
 {
@@ -2297,8 +2378,16 @@  enum rs6000_builtins
   RS6000_BUILTIN_COUNT
 };
 
-#undef RS6000_BUILTIN
-#undef RS6000_BUILTIN_EQUATE
+#undef RS6000_BUILTIN_1
+#undef RS6000_BUILTIN_2
+#undef RS6000_BUILTIN_3
+#undef RS6000_BUILTIN_A
+#undef RS6000_BUILTIN_D
+#undef RS6000_BUILTIN_E
+#undef RS6000_BUILTIN_P
+#undef RS6000_BUILTIN_Q
+#undef RS6000_BUILTIN_S
+#undef RS6000_BUILTIN_X
 
 enum rs6000_builtin_type_index
 {
Index: gcc/config/rs6000/rs6000-protos.h
===================================================================
--- gcc/config/rs6000/rs6000-protos.h	(.../trunk)	(revision 181085)
+++ gcc/config/rs6000/rs6000-protos.h	(.../branches/ibm/builtin2)	(revision 181121)
@@ -174,6 +174,8 @@  extern const char * output_isel (rtx *);
 extern void rs6000_call_indirect_aix (rtx, rtx, rtx);
 extern void rs6000_aix_asm_output_dwarf_table_ref (char *);
 extern void get_ppc476_thunk_name (char name[32]);
+extern bool rs6000_overloaded_builtin_p (enum rs6000_builtins);
+extern unsigned rs6000_builtin_mask_calculate (void);
 
 /* Declare functions in rs6000-c.c */
 
@@ -182,6 +184,8 @@  extern void rs6000_cpu_cpp_builtins (str
 #ifdef TREE_CODE
 extern bool rs6000_pragma_target_parse (tree, tree);
 #endif
+extern void rs6000_target_modify_macros (bool, int, unsigned);
+extern void (*rs6000_target_modify_macros_ptr) (bool, int, unsigned);
 
 #if TARGET_MACHO
 char *output_call (rtx, rtx *, int, int);