From patchwork Thu Feb 20 02:53:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Finley Xiao X-Patchwork-Id: 1241198 X-Patchwork-Delegate: ykai007@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rock-chips.com Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 48NM1V3BwZz9sRN for ; Thu, 20 Feb 2020 15:24:30 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id DA17081762; Thu, 20 Feb 2020 05:23:23 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=rock-chips.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 9F435813CC; Thu, 20 Feb 2020 03:54:36 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.2 Received: from lucky1.263xmail.com (lucky1.263xmail.com [211.157.147.130]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 6F8A9813C0 for ; Thu, 20 Feb 2020 03:54:30 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=rock-chips.com Authentication-Results: phobos.denx.de; spf=fail smtp.mailfrom=finley.xiao@rock-chips.com Received: from localhost (unknown [192.168.167.172]) by lucky1.263xmail.com (Postfix) with ESMTP id 1722383A45; Thu, 20 Feb 2020 10:54:26 +0800 (CST) X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-ADDR-CHECKED4: 1 X-ANTISPAM-LEVEL: 2 X-ABS-CHECKED: 0 Received: from localhost.localdomain (unknown [220.200.40.211]) by smtp.263.net (postfix) whith ESMTP id P24116T140474276898560S1582167236329407_; Thu, 20 Feb 2020 10:54:25 +0800 (CST) X-IP-DOMAINF: 1 X-UNIQUE-TAG: X-RL-SENDER: finley.xiao@rock-chips.com X-SENDER: xf@rock-chips.com X-LOGIN-NAME: finley.xiao@rock-chips.com X-FST-TO: yk@rock-chips.com X-SENDER-IP: 220.200.40.211 X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 From: Finley Xiao To: kever.yang@rock-chips.com Cc: chenjh@rock-chips.com, sjg@chromium.org, philipp.tomsich@theobroma-systems.com, u-boot@lists.denx.de, Finley Xiao Subject: [PATCH 2/2] rockchip: efuse: Add support for rk1808 non-secure efuse Date: Thu, 20 Feb 2020 10:53:48 +0800 Message-Id: <20200220025353.3158-4-finley.xiao@rock-chips.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20200220025353.3158-1-finley.xiao@rock-chips.com> References: <20200220025353.3158-1-finley.xiao@rock-chips.com> X-Mailman-Approved-At: Thu, 20 Feb 2020 05:22:17 +0100 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.30rc1 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de X-Virus-Status: Clean This adds the necessary data for handling eFuse on the rk1808. Signed-off-by: Finley Xiao --- drivers/misc/rockchip-efuse.c | 114 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 114 insertions(+) diff --git a/drivers/misc/rockchip-efuse.c b/drivers/misc/rockchip-efuse.c index 68762d3f6f..778e29f30d 100644 --- a/drivers/misc/rockchip-efuse.c +++ b/drivers/misc/rockchip-efuse.c @@ -16,6 +16,46 @@ #include #include +#define T_CSB_P_S 0 +#define T_PGENB_P_S 0 +#define T_LOAD_P_S 0 +#define T_ADDR_P_S 0 +#define T_STROBE_P_S (0 + 110) /* 1.1us */ +#define T_CSB_P_L (0 + 110 + 1000 + 20) /* 200ns */ +#define T_PGENB_P_L (0 + 110 + 1000 + 20) +#define T_LOAD_P_L (0 + 110 + 1000 + 20) +#define T_ADDR_P_L (0 + 110 + 1000 + 20) +#define T_STROBE_P_L (0 + 110 + 1000) /* 10us */ +#define T_CSB_R_S 0 +#define T_PGENB_R_S 0 +#define T_LOAD_R_S 0 +#define T_ADDR_R_S 2 +#define T_STROBE_R_S (2 + 3) +#define T_CSB_R_L (2 + 3 + 3 + 3) +#define T_PGENB_R_L (2 + 3 + 3 + 3) +#define T_LOAD_R_L (2 + 3 + 3 + 3) +#define T_ADDR_R_L (2 + 3 + 3 + 2) +#define T_STROBE_R_L (2 + 3 + 3) + +#define T_CSB_P 0x28 +#define T_PGENB_P 0x2c +#define T_LOAD_P 0x30 +#define T_ADDR_P 0x34 +#define T_STROBE_P 0x38 +#define T_CSB_R 0x3c +#define T_PGENB_R 0x40 +#define T_LOAD_R 0x44 +#define T_ADDR_R 0x48 +#define T_STROBE_R 0x4c + +#define RK1808_USER_MODE BIT(0) +#define RK1808_INT_FINISH BIT(0) +#define RK1808_AUTO_ENB BIT(0) +#define RK1808_AUTO_RD BIT(1) +#define RK1808_A_SHIFT 16 +#define RK1808_A_MASK 0x3ff +#define RK1808_NBYTES 4 + #define RK3288_A_SHIFT 6 #define RK3288_A_MASK 0x3ff #define RK3288_NFUSES 32 @@ -109,6 +149,76 @@ U_BOOT_CMD( ); #endif +static void rk1808_efuse_timing_init(void __iomem *base) +{ + static bool init; + + if (init) + return; + + /* enable auto mode */ + writel(readl(base) & (~RK1808_USER_MODE), base); + + /* setup efuse timing */ + writel((T_CSB_P_S << 16) | T_CSB_P_L, base + T_CSB_P); + writel((T_PGENB_P_S << 16) | T_PGENB_P_L, base + T_PGENB_P); + writel((T_LOAD_P_S << 16) | T_LOAD_P_L, base + T_LOAD_P); + writel((T_ADDR_P_S << 16) | T_ADDR_P_L, base + T_ADDR_P); + writel((T_STROBE_P_S << 16) | T_STROBE_P_L, base + T_STROBE_P); + writel((T_CSB_R_S << 16) | T_CSB_R_L, base + T_CSB_R); + writel((T_PGENB_R_S << 16) | T_PGENB_R_L, base + T_PGENB_R); + writel((T_LOAD_R_S << 16) | T_LOAD_R_L, base + T_LOAD_R); + writel((T_ADDR_R_S << 16) | T_ADDR_R_L, base + T_ADDR_R); + writel((T_STROBE_R_S << 16) | T_STROBE_R_L, base + T_STROBE_R); + + init = true; +} + +static int rockchip_rk1808_efuse_read(struct udevice *dev, int offset, + void *buf, int size) +{ + struct rockchip_efuse_platdata *plat = dev_get_platdata(dev); + struct rockchip_efuse_regs *efuse = + (struct rockchip_efuse_regs *)plat->base; + unsigned int addr_start, addr_end, addr_offset, addr_len; + u32 out_value, status; + u8 *buffer; + int ret = 0, i = 0; + + rk1808_efuse_timing_init(plat->base); + + addr_start = rounddown(offset, RK1808_NBYTES) / RK1808_NBYTES; + addr_end = roundup(offset + size, RK1808_NBYTES) / RK1808_NBYTES; + addr_offset = offset % RK1808_NBYTES; + addr_len = addr_end - addr_start; + + buffer = calloc(1, sizeof(*buffer) * addr_len * RK1808_NBYTES); + if (!buffer) + return -ENOMEM; + + while (addr_len--) { + writel(RK1808_AUTO_RD | RK1808_AUTO_ENB | + ((addr_start++ & RK1808_A_MASK) << RK1808_A_SHIFT), + &efuse->auto_ctrl); + udelay(2); + status = readl(&efuse->int_status); + if (!(status & RK1808_INT_FINISH)) { + ret = -EIO; + goto err; + } + out_value = readl(&efuse->dout2); + writel(RK1808_INT_FINISH, &efuse->int_status); + + memcpy(&buffer[i], &out_value, RK1808_NBYTES); + i += RK1808_NBYTES; + } + memcpy(buf, buffer + addr_offset, size); +err: + free(buffer); + + return ret; +} + static int rockchip_rk3288_efuse_read(struct udevice *dev, int offset, void *buf, int size) { @@ -273,6 +383,10 @@ static int rockchip_efuse_ofdata_to_platdata(struct udevice *dev) static const struct udevice_id rockchip_efuse_ids[] = { { + .compatible = "rockchip,rk1808-efuse", + .data = (ulong)&rockchip_rk1808_efuse_read, + }, + { .compatible = "rockchip,rk3066a-efuse", .data = (ulong)&rockchip_rk3288_efuse_read, },