Patchwork powerpc/p1023: set IRQ[4:6, 11] to high level sensitive for PCIe

login
register
mail settings
Submitter Zang Roy-R61911
Date Nov. 7, 2011, 8:32 a.m.
Message ID <1320654778-3294-1-git-send-email-tie-fei.zang@freescale.com>
Download mbox | patch
Permalink /patch/124012/
State Accepted
Delegated to: Kumar Gala
Headers show

Comments

Zang Roy-R61911 - Nov. 7, 2011, 8:32 a.m.
P1023 external IRQ[4:6, 11] do not pin out, but the interrupts are
shared with PCIe controller.
The silicon internally ties the interrupts to L, so change the
IRQ[4:6,11] to high level sensitive for PCIe.

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
---
 arch/powerpc/boot/dts/p1023rds.dts |    8 ++++----
 1 files changed, 4 insertions(+), 4 deletions(-)
Scott Wood - Nov. 7, 2011, 6:44 p.m.
On 11/07/2011 02:32 AM, Roy Zang wrote:
> P1023 external IRQ[4:6, 11] do not pin out, but the interrupts are
> shared with PCIe controller.
> The silicon internally ties the interrupts to L, so change the
> IRQ[4:6,11] to high level sensitive for PCIe.

Some extra commentary on why this works would be nice.

The manual says:

> If a PCI Express INTx interrupt is being used, then the PIC must be configured so that external interrupts
> are level-sensitive (EIVPRn[S] = 1).

and

> In general, these signals should be considered mutually exclusive. If a PCI Express INTx signal is being
> used, the PIC must be configured so that external interrupts are level sensitive (EIVPRn[S] = 1). If an IRQn
> signal is being used as edge-triggered (EIVPRn[S] = 0), the system must not allow inbound PCI Express
> INTx transactions.
>
> Note that it is possible to share IRQn and INTx if the external interrupt is level sensitive; however, if an
> interrupt occurs, the interrupt service routine must poll both the external sources connected to the IRQn
> input and the PCI Express INTx sources to determine from which path the external interrupt came. In any
> case, IRQn should be pulled to the negated state as determined by the associated polarity setting in
> EIVPRn[P].

So it looks like there's some magic whereby the configuration of the
MPIC affects how the PCIe feeds the interrupt in.

Is there (or will there be) an erratum, or anything in the manual
besides not being documented as external interrupts, about these
specific interrupts being tied low in silicon or needing to be active high?

-Scott
Zang Roy-R61911 - Nov. 8, 2011, 5:51 a.m.
> -----Original Message-----
> From: Wood Scott-B07421
> Sent: Tuesday, November 08, 2011 2:44 AM
> To: Zang Roy-R61911
> Cc: linuxppc-dev@lists.ozlabs.org
> Subject: Re: [PATCH] powerpc/p1023: set IRQ[4:6, 11] to high level sensitive for
> PCIe
> 
> On 11/07/2011 02:32 AM, Roy Zang wrote:
> > P1023 external IRQ[4:6, 11] do not pin out, but the interrupts are
> > shared with PCIe controller.
> > The silicon internally ties the interrupts to L, so change the
> > IRQ[4:6,11] to high level sensitive for PCIe.
> 
> Some extra commentary on why this works would be nice.
I do not know what kind of extra commentary you request. 
IRQ 4,5,6, 11 are internally tie to low by silicon. To use these interrupts for PCIe, they need to set high level sensitive.
It is clear enough for this patch.

> 
> The manual says:
> 
> > If a PCI Express INTx interrupt is being used, then the PIC must be configured
> so that external interrupts
> > are level-sensitive (EIVPRn[S] = 1).
That is true for all FSL powerpc silicon with PCIe controller beside P1023.

> 
> and
> 
> > In general, these signals should be considered mutually exclusive. If a PCI
> Express INTx signal is being
> > used, the PIC must be configured so that external interrupts are level
> sensitive (EIVPRn[S] = 1). If an IRQn
> > signal is being used as edge-triggered (EIVPRn[S] = 0), the system must not
> allow inbound PCI Express
> > INTx transactions.
> >
> > Note that it is possible to share IRQn and INTx if the external interrupt is
> level sensitive; however, if an
> > interrupt occurs, the interrupt service routine must poll both the external
> sources connected to the IRQn
> > input and the PCI Express INTx sources to determine from which path the
> external interrupt came. In any
> > case, IRQn should be pulled to the negated state as determined by the
> associated polarity setting in
> > EIVPRn[P].
> 
> So it looks like there's some magic whereby the configuration of the
> MPIC affects how the PCIe feeds the interrupt in.
> 
> Is there (or will there be) an erratum, or anything in the manual
> besides not being documented as external interrupts, about these
> specific interrupts being tied low in silicon or needing to be active high?
I do not think there is (will) an erratum. But I agree the manual needs to document this more clear.
thanks.
Roy
Scott Wood - Nov. 8, 2011, 4:54 p.m.
On 11/07/2011 11:51 PM, Zang Roy-R61911 wrote:
> 
> 
>> -----Original Message-----
>> From: Wood Scott-B07421
>> Sent: Tuesday, November 08, 2011 2:44 AM
>> To: Zang Roy-R61911
>> Cc: linuxppc-dev@lists.ozlabs.org
>> Subject: Re: [PATCH] powerpc/p1023: set IRQ[4:6, 11] to high level sensitive for
>> PCIe
>>
>> On 11/07/2011 02:32 AM, Roy Zang wrote:
>>> P1023 external IRQ[4:6, 11] do not pin out, but the interrupts are
>>> shared with PCIe controller.
>>> The silicon internally ties the interrupts to L, so change the
>>> IRQ[4:6,11] to high level sensitive for PCIe.
>>
>> Some extra commentary on why this works would be nice.
> I do not know what kind of extra commentary you request. 

Just a note that there's magic to allow the PCIe block to output these
interrupts as either active-high or active-low, depending on how they're
configured at the mpic.

> IRQ 4,5,6, 11 are internally tie to low by silicon. To use these interrupts for PCIe, they need to set high level sensitive.
> It is clear enough for this patch.

It's odd enough that I felt the need to go reading through the docs to
see why such a thing would work at all.

>> The manual says:
>>
>>> If a PCI Express INTx interrupt is being used, then the PIC must be configured
>> so that external interrupts
>>> are level-sensitive (EIVPRn[S] = 1).
> That is true for all FSL powerpc silicon with PCIe controller beside P1023.

Sure, my point was more that it didn't say anything there about how to
configure EIVPRn[P].

-Scott
Zang Roy-R61911 - Nov. 9, 2011, 3:27 p.m.
> -----Original Message-----
> From: Wood Scott-B07421
> Sent: Wednesday, November 09, 2011 0:54 AM
> To: Zang Roy-R61911
> Cc: Wood Scott-B07421; linuxppc-dev@lists.ozlabs.org
> Subject: Re: [PATCH] powerpc/p1023: set IRQ[4:6, 11] to high level sensitive for
> PCIe
> 
> On 11/07/2011 11:51 PM, Zang Roy-R61911 wrote:
> >
> >
> >> -----Original Message-----
> >> From: Wood Scott-B07421
> >> Sent: Tuesday, November 08, 2011 2:44 AM
> >> To: Zang Roy-R61911
> >> Cc: linuxppc-dev@lists.ozlabs.org
> >> Subject: Re: [PATCH] powerpc/p1023: set IRQ[4:6, 11] to high level sensitive
> for
> >> PCIe
> >>
> >> On 11/07/2011 02:32 AM, Roy Zang wrote:
> >>> P1023 external IRQ[4:6, 11] do not pin out, but the interrupts are
> >>> shared with PCIe controller.
> >>> The silicon internally ties the interrupts to L, so change the
> >>> IRQ[4:6,11] to high level sensitive for PCIe.
> >>
> >> Some extra commentary on why this works would be nice.
> > I do not know what kind of extra commentary you request.
> 
> Just a note that there's magic to allow the PCIe block to output these
> interrupts as either active-high or active-low, depending on how they're
> configured at the mpic.
I do not think there is any magic.
On the contrary, it is the mpic/device tree needs to comply with the hardware setting for the interrupt polarity.

> 
> > IRQ 4,5,6, 11 are internally tie to low by silicon. To use these interrupts
> for PCIe, they need to set high level sensitive.
> > It is clear enough for this patch.
> 
> It's odd enough that I felt the need to go reading through the docs to
> see why such a thing would work at all.
If you consider the normal case, the shared irq pulls up, the PCIe interrupt set to low level sensitive. Anything odd?

> 
> >> The manual says:
> >>
> >>> If a PCI Express INTx interrupt is being used, then the PIC must be
> configured
> >> so that external interrupts
> >>> are level-sensitive (EIVPRn[S] = 1).
> > That is true for all FSL powerpc silicon with PCIe controller beside P1023.
> 
> Sure, my point was more that it didn't say anything there about how to
> configure EIVPRn[P].
It depends on the irq pulls up or down by hardware.
Roy
Scott Wood - Nov. 9, 2011, 3:38 p.m.
On Wed, Nov 09, 2011 at 09:27:02AM -0600, Zang Roy-R61911 wrote:
> > -----Original Message-----
> > From: Wood Scott-B07421
> > Sent: Wednesday, November 09, 2011 0:54 AM
> > To: Zang Roy-R61911
> > Cc: Wood Scott-B07421; linuxppc-dev@lists.ozlabs.org
> > Subject: Re: [PATCH] powerpc/p1023: set IRQ[4:6, 11] to high level sensitive for
> > PCIe
> > 
> > Just a note that there's magic to allow the PCIe block to output these
> > interrupts as either active-high or active-low, depending on how they're
> > configured at the mpic.
> I do not think there is any magic.
> On the contrary, it is the mpic/device tree needs to comply with the hardware setting for the interrupt polarity.

The magic is that the PCIe block can generate the interrupt in either
polarity depending on the MPIC setting (or perhaps it bases it on
sampling the pin status during/after reset, but that seems fragile).

> > > IRQ 4,5,6, 11 are internally tie to low by silicon. To use these interrupts
> > for PCIe, they need to set high level sensitive.
> > > It is clear enough for this patch.
> > 
> > It's odd enough that I felt the need to go reading through the docs to
> > see why such a thing would work at all.
> If you consider the normal case, the shared irq pulls up, the PCIe interrupt set to low level sensitive. Anything odd?

The oddity is that active-high works at all for a PCI interrupt, and that
not all the PCIe interrupts have the same polarity.

-Scott
Kumar Gala - Nov. 9, 2011, 3:49 p.m.
How did you come by this information?

- k

On Nov 7, 2011, at 2:32 AM, Roy Zang wrote:

> P1023 external IRQ[4:6, 11] do not pin out, but the interrupts are
> shared with PCIe controller.
> The silicon internally ties the interrupts to L, so change the
> IRQ[4:6,11] to high level sensitive for PCIe.
> 
> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
> ---
> arch/powerpc/boot/dts/p1023rds.dts |    8 ++++----
> 1 files changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/powerpc/boot/dts/p1023rds.dts b/arch/powerpc/boot/dts/p1023rds.dts
> index d9b7767..66bf804 100644
> --- a/arch/powerpc/boot/dts/p1023rds.dts
> +++ b/arch/powerpc/boot/dts/p1023rds.dts
> @@ -490,9 +490,9 @@
> 			interrupt-map-mask = <0xf800 0 0 7>;
> 			interrupt-map = <
> 				/* IDSEL 0x0 */
> -				0000 0 0 1 &mpic 4 1
> -				0000 0 0 2 &mpic 5 1
> -				0000 0 0 3 &mpic 6 1
> +				0000 0 0 1 &mpic 4 2
> +				0000 0 0 2 &mpic 5 2
> +				0000 0 0 3 &mpic 6 2
> 				0000 0 0 4 &mpic 7 1
> 				>;
> 			ranges = <0x2000000 0x0 0xa0000000
> @@ -532,7 +532,7 @@
> 				0000 0 0 1 &mpic 8 1
> 				0000 0 0 2 &mpic 9 1
> 				0000 0 0 3 &mpic 10 1
> -				0000 0 0 4 &mpic 11 1
> +				0000 0 0 4 &mpic 11 2
> 				>;
> 			ranges = <0x2000000 0x0 0x80000000
> 				  0x2000000 0x0 0x80000000
> -- 
> 1.6.0.6
>
Kumar Gala - Nov. 15, 2011, 9:51 p.m.
On Nov 7, 2011, at 2:32 AM, Roy Zang wrote:

> P1023 external IRQ[4:6, 11] do not pin out, but the interrupts are
> shared with PCIe controller.
> The silicon internally ties the interrupts to L, so change the
> IRQ[4:6,11] to high level sensitive for PCIe.
> 
> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
> ---
> arch/powerpc/boot/dts/p1023rds.dts |    8 ++++----
> 1 files changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/powerpc/boot/dts/p1023rds.dts b/arch/powerpc/boot/dts/p1023rds.dts
> index d9b7767..66bf804 100644
> --- a/arch/powerpc/boot/dts/p1023rds.dts
> +++ b/arch/powerpc/boot/dts/p1023rds.dts
> @@ -490,9 +490,9 @@
> 			interrupt-map-mask = <0xf800 0 0 7>;
> 			interrupt-map = <
> 				/* IDSEL 0x0 */
> -				0000 0 0 1 &mpic 4 1
> -				0000 0 0 2 &mpic 5 1
> -				0000 0 0 3 &mpic 6 1
> +				0000 0 0 1 &mpic 4 2
> +				0000 0 0 2 &mpic 5 2
> +				0000 0 0 3 &mpic 6 2
> 				0000 0 0 4 &mpic 7 1
> 				>;
> 			ranges = <0x2000000 0x0 0xa0000000
> @@ -532,7 +532,7 @@
> 				0000 0 0 1 &mpic 8 1
> 				0000 0 0 2 &mpic 9 1
> 				0000 0 0 3 &mpic 10 1
> -				0000 0 0 4 &mpic 11 1
> +				0000 0 0 4 &mpic 11 2
> 				>;
> 			ranges = <0x2000000 0x0 0x80000000
> 				  0x2000000 0x0 0x80000000
> -- 
> 1.6.0.6
> 

Should be setting ALL PCIe interrupts to '2'?  As I think in general we say these PCIe are 'active high'.  The only reason I would think we would NOT do this is if they are shared with some external device that is 'active low'.  If so we should comment that somewhere (maybe in the .dts, maybe just in the commit message).

- k
Scott Wood - Nov. 15, 2011, 10:14 p.m.
On 11/15/2011 03:51 PM, Kumar Gala wrote:
> 
> On Nov 7, 2011, at 2:32 AM, Roy Zang wrote:
> 
> Should be setting ALL PCIe interrupts to '2'?  As I think in general
> we say these PCIe are 'active high'.  The only reason I would think
> we would NOT do this is if they are shared with some external device
> that is 'active low'.  If so we should comment that somewhere (maybe
> in the .dts, maybe just in the commit message).

I'd assume the ones that are pinned out are pulled high on the board.
Active-low is normal, it's these non-pinned-out "external" interrupts
that are pulled low inside the SoC that are weird.

-Scott
Zang Roy-R61911 - Nov. 16, 2011, 4:27 a.m.
> -----Original Message-----
> From: Wood Scott-B07421
> Sent: Wednesday, November 16, 2011 6:14 AM
> To: Kumar Gala
> Cc: Zang Roy-R61911; linuxppc-dev@lists.ozlabs.org
> Subject: Re: [PATCH] powerpc/p1023: set IRQ[4:6, 11] to high level
> sensitive for PCIe
> 
> On 11/15/2011 03:51 PM, Kumar Gala wrote:
> >
> > On Nov 7, 2011, at 2:32 AM, Roy Zang wrote:
> >
> > Should be setting ALL PCIe interrupts to '2'?  As I think in general
> > we say these PCIe are 'active high'.  The only reason I would think
> > we would NOT do this is if they are shared with some external device
> > that is 'active low'.  If so we should comment that somewhere (maybe
> > in the .dts, maybe just in the commit message).
> 
> I'd assume the ones that are pinned out are pulled high on the board.
yes. The boards pulled up the shared IRQs. PCIe specification does not specify 'active low' or 'active high', but for PCI, the INTx is 'active low'.

> Active-low is normal, it's these non-pinned-out "external" interrupts
> that are pulled low inside the SoC that are weird.
I agree here. Do you want me to add something to point out the "weird" in the commit message?
Thanks.
Roy

Patch

diff --git a/arch/powerpc/boot/dts/p1023rds.dts b/arch/powerpc/boot/dts/p1023rds.dts
index d9b7767..66bf804 100644
--- a/arch/powerpc/boot/dts/p1023rds.dts
+++ b/arch/powerpc/boot/dts/p1023rds.dts
@@ -490,9 +490,9 @@ 
 			interrupt-map-mask = <0xf800 0 0 7>;
 			interrupt-map = <
 				/* IDSEL 0x0 */
-				0000 0 0 1 &mpic 4 1
-				0000 0 0 2 &mpic 5 1
-				0000 0 0 3 &mpic 6 1
+				0000 0 0 1 &mpic 4 2
+				0000 0 0 2 &mpic 5 2
+				0000 0 0 3 &mpic 6 2
 				0000 0 0 4 &mpic 7 1
 				>;
 			ranges = <0x2000000 0x0 0xa0000000
@@ -532,7 +532,7 @@ 
 				0000 0 0 1 &mpic 8 1
 				0000 0 0 2 &mpic 9 1
 				0000 0 0 3 &mpic 10 1
-				0000 0 0 4 &mpic 11 1
+				0000 0 0 4 &mpic 11 2
 				>;
 			ranges = <0x2000000 0x0 0x80000000
 				  0x2000000 0x0 0x80000000