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[73.93.86.59]) by smtp.gmail.com with ESMTPSA id a22sm11532304pfk.108.2020.02.15.07.26.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 15 Feb 2020 07:26:33 -0800 (PST) Received: from gnu-cfl-2.hsd1.ca.comcast.net (localhost [IPv6:::1]) by gnu-cfl-2.localdomain (Postfix) with ESMTP id 7FEF1C04D8; Sat, 15 Feb 2020 07:26:28 -0800 (PST) From: "H.J. Lu" To: gcc-patches@gcc.gnu.org Cc: Jakub Jelinek , Jeffrey Law , Jan Hubicka , Uros Bizjak Subject: [PATCH 10/10] i386: Use ix86_output_ssemov for MMX TYPE_SSEMOV Date: Sat, 15 Feb 2020 07:26:28 -0800 Message-Id: <20200215152628.32068-11-hjl.tools@gmail.com> In-Reply-To: <20200215152628.32068-1-hjl.tools@gmail.com> References: <20200215152628.32068-1-hjl.tools@gmail.com> MIME-Version: 1.0 X-IsSubscribed: yes There is no need to set mode attribute to XImode since ix86_output_ssemov can properly encode xmm16-xmm31 registers with and without AVX512VL. Remove ext_sse_reg_operand since it is no longer needed. PR target/89229 * config/i386/mmx.md (MMXMODE:*mov_internal): Call ix86_output_ssemov for TYPE_SSEMOV. Remove ext_sse_reg_operand check. * config/i386/predicates.md (ext_sse_reg_operand): Removed. --- gcc/config/i386/mmx.md | 29 ++--------------------------- gcc/config/i386/predicates.md | 5 ----- 2 files changed, 2 insertions(+), 32 deletions(-) diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index f695831b5b9..7d9db5d352c 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -118,29 +118,7 @@ (define_insn "*mov_internal" return standard_sse_constant_opcode (insn, operands); case TYPE_SSEMOV: - switch (get_attr_mode (insn)) - { - case MODE_DI: - /* Handle broken assemblers that require movd instead of movq. */ - if (!HAVE_AS_IX86_INTERUNIT_MOVQ - && (GENERAL_REG_P (operands[0]) || GENERAL_REG_P (operands[1]))) - return "%vmovd\t{%1, %0|%0, %1}"; - return "%vmovq\t{%1, %0|%0, %1}"; - case MODE_TI: - return "%vmovdqa\t{%1, %0|%0, %1}"; - case MODE_XI: - return "vmovdqa64\t{%g1, %g0|%g0, %g1}"; - - case MODE_V2SF: - if (TARGET_AVX && REG_P (operands[0])) - return "vmovlps\t{%1, %0, %0|%0, %0, %1}"; - return "%vmovlps\t{%1, %0|%0, %1}"; - case MODE_V4SF: - return "%vmovaps\t{%1, %0|%0, %1}"; - - default: - gcc_unreachable (); - } + return ix86_output_ssemov (insn, operands); default: gcc_unreachable (); @@ -189,10 +167,7 @@ (define_insn "*mov_internal" (cond [(eq_attr "alternative" "2") (const_string "SI") (eq_attr "alternative" "11,12") - (cond [(ior (match_operand 0 "ext_sse_reg_operand") - (match_operand 1 "ext_sse_reg_operand")) - (const_string "XI") - (match_test "mode == V2SFmode") + (cond [(match_test "mode == V2SFmode") (const_string "V4SF") (ior (not (match_test "TARGET_SSE2")) (match_test "optimize_function_for_size_p (cfun)")) diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md index 1119366d54e..71f4cb1193c 100644 --- a/gcc/config/i386/predicates.md +++ b/gcc/config/i386/predicates.md @@ -61,11 +61,6 @@ (define_predicate "sse_reg_operand" (and (match_code "reg") (match_test "SSE_REGNO_P (REGNO (op))"))) -;; True if the operand is an AVX-512 new register. -(define_predicate "ext_sse_reg_operand" - (and (match_code "reg") - (match_test "EXT_REX_SSE_REGNO_P (REGNO (op))"))) - ;; Return true if op is a QImode register. (define_predicate "any_QIreg_operand" (and (match_code "reg")