arm: dts: imx8mq-evk: add phy-reset-gpios for fec1
diff mbox series

Message ID 20200214171844.18810-1-alifer.wsdm@gmail.com
State Superseded
Delegated to: Stefano Babic
Headers show
Series
  • arm: dts: imx8mq-evk: add phy-reset-gpios for fec1
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Commit Message

Alifer Moraes Feb. 14, 2020, 5:18 p.m. UTC
Let the driver reset the phy via dts description instead of doing it
through functions in imx8mq_evk.c

Signed-off-by: Alifer Moraes <alifer.wsdm@gmail.com>
---
 arch/arm/dts/imx8mq-evk.dts             |  2 ++
 board/freescale/imx8mq_evk/imx8mq_evk.c | 18 ------------------
 2 files changed, 2 insertions(+), 18 deletions(-)

Comments

Michael Nazzareno Trimarchi Feb. 14, 2020, 5:21 p.m. UTC | #1
Hi

On Fri, Feb 14, 2020 at 6:18 PM Alifer Moraes <alifer.wsdm@gmail.com> wrote:
>
> Let the driver reset the phy via dts description instead of doing it
> through functions in imx8mq_evk.c
>
> Signed-off-by: Alifer Moraes <alifer.wsdm@gmail.com>
> ---
>  arch/arm/dts/imx8mq-evk.dts             |  2 ++
>  board/freescale/imx8mq_evk/imx8mq_evk.c | 18 ------------------
>  2 files changed, 2 insertions(+), 18 deletions(-)
>
> diff --git a/arch/arm/dts/imx8mq-evk.dts b/arch/arm/dts/imx8mq-evk.dts
> index 3693933451..55294ba9c8 100644
> --- a/arch/arm/dts/imx8mq-evk.dts
> +++ b/arch/arm/dts/imx8mq-evk.dts
> @@ -104,6 +104,8 @@
>         pinctrl-0 = <&pinctrl_fec1>;
>         phy-mode = "rgmii-id";
>         phy-handle = <&ethphy0>;
> +       phy-reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
> +       phy-reset-duration = <10>;

Where is the relative pinctrl change to mux the pin? why now is 10 the
reset duration

Michael

>         fsl,magic-packet;
>         status = "okay";
>
> diff --git a/board/freescale/imx8mq_evk/imx8mq_evk.c b/board/freescale/imx8mq_evk/imx8mq_evk.c
> index cb39d0f2d6..b2f464abb1 100644
> --- a/board/freescale/imx8mq_evk/imx8mq_evk.c
> +++ b/board/freescale/imx8mq_evk/imx8mq_evk.c
> @@ -64,29 +64,11 @@ int dram_init(void)
>  }
>
>  #ifdef CONFIG_FEC_MXC
> -#define FEC_RST_PAD IMX_GPIO_NR(1, 9)
> -static iomux_v3_cfg_t const fec1_rst_pads[] = {
> -       IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL),
> -};
> -
> -static void setup_iomux_fec(void)
> -{
> -       imx_iomux_v3_setup_multiple_pads(fec1_rst_pads,
> -                                        ARRAY_SIZE(fec1_rst_pads));
> -
> -       gpio_request(IMX_GPIO_NR(1, 9), "fec1_rst");
> -       gpio_direction_output(IMX_GPIO_NR(1, 9), 0);
> -       udelay(500);
> -       gpio_direction_output(IMX_GPIO_NR(1, 9), 1);
> -}
> -
>  static int setup_fec(void)
>  {
>         struct iomuxc_gpr_base_regs *gpr =
>                 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
>
> -       setup_iomux_fec();
> -
>         /* Use 125M anatop REF_CLK1 for ENET1, not from external */
>         clrsetbits_le32(&gpr->gpr[1], BIT(13) | BIT(17), 0);
>         return set_clk_enet(ENET_125MHZ);
> --
> 2.17.1
>
Michael Nazzareno Trimarchi Feb. 14, 2020, 5:36 p.m. UTC | #2
Hi

On Fri, Feb 14, 2020 at 6:33 PM Alifer Moraes <alifer.wsdm@gmail.com> wrote:
>
> Hello, Michael,
>
> > Where is the relative pinctrl change to mux the pin? why now is 10 the
> > reset duration
>
> The pinctrl change is described in arch/arm/dts/imx8mq-evk.dts in the
> subnode pinctrl_fec1.

Ok, so was already defined the pinmux there.

> The ethernet phy used by this board is an atheros 8031, its datasheet
> says that the reset duration should be 10ms.

Please upload the commit message with this information

Michael

PS: this way to reset is deprecated but uboot I think does not have
the reset at mdio bus level

>
> Regards,
>
> Alifer

Patch
diff mbox series

diff --git a/arch/arm/dts/imx8mq-evk.dts b/arch/arm/dts/imx8mq-evk.dts
index 3693933451..55294ba9c8 100644
--- a/arch/arm/dts/imx8mq-evk.dts
+++ b/arch/arm/dts/imx8mq-evk.dts
@@ -104,6 +104,8 @@ 
 	pinctrl-0 = <&pinctrl_fec1>;
 	phy-mode = "rgmii-id";
 	phy-handle = <&ethphy0>;
+	phy-reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
+	phy-reset-duration = <10>;
 	fsl,magic-packet;
 	status = "okay";
 
diff --git a/board/freescale/imx8mq_evk/imx8mq_evk.c b/board/freescale/imx8mq_evk/imx8mq_evk.c
index cb39d0f2d6..b2f464abb1 100644
--- a/board/freescale/imx8mq_evk/imx8mq_evk.c
+++ b/board/freescale/imx8mq_evk/imx8mq_evk.c
@@ -64,29 +64,11 @@  int dram_init(void)
 }
 
 #ifdef CONFIG_FEC_MXC
-#define FEC_RST_PAD IMX_GPIO_NR(1, 9)
-static iomux_v3_cfg_t const fec1_rst_pads[] = {
-	IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-static void setup_iomux_fec(void)
-{
-	imx_iomux_v3_setup_multiple_pads(fec1_rst_pads,
-					 ARRAY_SIZE(fec1_rst_pads));
-
-	gpio_request(IMX_GPIO_NR(1, 9), "fec1_rst");
-	gpio_direction_output(IMX_GPIO_NR(1, 9), 0);
-	udelay(500);
-	gpio_direction_output(IMX_GPIO_NR(1, 9), 1);
-}
-
 static int setup_fec(void)
 {
 	struct iomuxc_gpr_base_regs *gpr =
 		(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
 
-	setup_iomux_fec();
-
 	/* Use 125M anatop REF_CLK1 for ENET1, not from external */
 	clrsetbits_le32(&gpr->gpr[1], BIT(13) | BIT(17), 0);
 	return set_clk_enet(ENET_125MHZ);