Message ID | 1581658476-12611-4-git-send-email-wasim.khan@nxp.com |
---|---|
State | Accepted |
Commit | 8cf113f473fdb60b62f939a21bc7f51795b168d8 |
Delegated to: | Priyanka Jain |
Headers | show
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Fri, 14 Feb 2020 05:34:54 +0000 From: Wasim Khan <wasim.khan@nxp.com> To: priyanka.jain@nxp.com, udit.agarwal@nxp.com, pankaj.bansal@nxp.com Cc: u-boot@lists.denx.de, Wasim Khan <wasim.khan@nxp.com> Subject: [PATCH 3/3] board: fsl: lx2160a: Add GIC LPI memory reserve fixup Date: Fri, 14 Feb 2020 11:04:36 +0530 Message-Id: <1581658476-12611-4-git-send-email-wasim.khan@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1581658476-12611-1-git-send-email-wasim.khan@nxp.com> References: <1581658476-12611-1-git-send-email-wasim.khan@nxp.com> Content-Type: text/plain X-ClientProxiedBy: SGBP274CA0001.SGPP274.PROD.OUTLOOK.COM (2603:1096:4:b0::13) To VE1PR04MB6702.eurprd04.prod.outlook.com (2603:10a6:803:123::13) MIME-Version: 1.0 Received: from lsv03032.swis.in-blr01.nxp.com (14.142.151.118) by SGBP274CA0001.SGPP274.PROD.OUTLOOK.COM (2603:1096:4:b0::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.20.2729.22 via Frontend Transport; Fri, 14 Feb 2020 05:34:52 +0000 X-Mailer: git-send-email 2.7.4 X-Originating-IP: [14.142.151.118] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: acd02cf2-ddd8-44cd-69a5-08d7b10f9ed9 X-MS-TrafficTypeDiagnostic: VE1PR04MB6559:|VE1PR04MB6559: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: <VE1PR04MB6559B04F2767C83A2049B2E790150@VE1PR04MB6559.eurprd04.prod.outlook.com> X-MS-Oob-TLC-OOBClassifiers: OLM:747; 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Program GIC LPI configuration table
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expand
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diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c index d8753b1..34f866b 100644 --- a/board/freescale/lx2160a/lx2160a.c +++ b/board/freescale/lx2160a/lx2160a.c @@ -630,6 +630,21 @@ void board_quiesce_devices(void) } #endif +#ifdef CONFIG_GIC_V3_ITS +void fdt_fixup_gic_lpi_memory(void *blob, u64 gic_lpi_base) +{ + u32 phandle; + int err; + struct fdt_memory gic_lpi; + + gic_lpi.start = gic_lpi_base; + gic_lpi.end = gic_lpi_base + GIC_LPI_SIZE - 1; + err = fdtdec_add_reserved_memory(blob, "gic-lpi", &gic_lpi, &phandle); + if (err < 0) + debug("failed to add reserved memory: %d\n", err); +} +#endif + #ifdef CONFIG_OF_BOARD_SETUP int ft_board_setup(void *blob, bd_t *bd) { @@ -664,6 +679,7 @@ int ft_board_setup(void *blob, bd_t *bd) #ifdef CONFIG_GIC_V3_ITS gic_lpi_base = gd->arch.resv_ram - GIC_LPI_SIZE; gic_lpi_tables_init(gic_lpi_base, cpu_numcores()); + fdt_fixup_gic_lpi_memory(blob, gic_lpi_base); #endif #ifdef CONFIG_RESV_RAM
Reserve DDR memory region used for GIC LPI configuration table. Signed-off-by: Wasim Khan <wasim.khan@nxp.com> --- board/freescale/lx2160a/lx2160a.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)