From patchwork Fri Nov 4 16:52:31 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jose Plans X-Patchwork-Id: 123668 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from chlorine.canonical.com (chlorine.canonical.com [91.189.94.204]) by ozlabs.org (Postfix) with ESMTP id E9176B70DD for ; Sat, 5 Nov 2011 03:52:44 +1100 (EST) Received: from localhost ([127.0.0.1] helo=chlorine.canonical.com) by chlorine.canonical.com with esmtp (Exim 4.71) (envelope-from ) id 1RMN0P-0004nC-0G; Fri, 04 Nov 2011 16:52:37 +0000 Received: from youngberry.canonical.com ([91.189.89.112]) by chlorine.canonical.com with esmtp (Exim 4.71) (envelope-from ) id 1RMN0M-0004n2-GQ for kernel-team@lists.ubuntu.com; Fri, 04 Nov 2011 16:52:34 +0000 Received: from [71.46.235.243] (helo=[10.155.38.240]) by youngberry.canonical.com with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1RMN0M-0005II-59 for kernel-team@lists.ubuntu.com; Fri, 04 Nov 2011 16:52:34 +0000 Message-ID: <1320425551.24274.15.camel@jmp> Subject: [natty] UBUNTU: SAUCE: (no-up) [PATCH 1/2] drm/i915: don't enable plane, pipe and PLL prematurely From: Jose Plans To: kernel-team@lists.ubuntu.com Date: Fri, 04 Nov 2011 12:52:31 -0400 In-Reply-To: <1320425348.24274.12.camel@jmp> References: <1320425348.24274.12.camel@jmp> Organization: Canonical Ltd X-Mailer: Evolution 3.2.0- Mime-Version: 1.0 X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.13 Precedence: list Reply-To: jose.plans@canonical.com List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: kernel-team-bounces@lists.ubuntu.com Errors-To: kernel-team-bounces@lists.ubuntu.com Acked-by: Seth Forshee Signed-off-by: From 6f429dca81e9be173655302ea7252906d1291321 Mon Sep 17 00:00:00 2001 From: Jose Plans Date: Thu, 20 Oct 2011 19:05:53 +0000 Subject: [natty] UBUNTU: SAUCE: (no-up) [PATCH 1/2] drm/i915: don't enable plane, pipe and PLL prematurely BugLink: http://bugs.launchpad.net/bugs/812638 On Ironlake+ we need to enable these in a specific order. Signed-off-by: Jesse Barnes Signed-off-by: Chris Wilson (cherry picked from commit 65993d64a31844ad444694efb2d159eb9c883e49) Signed-off by: Jose Plans --- drivers/gpu/drm/i915/intel_display.c | 8 +++++--- 1 files changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 841558b..49644cc 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -4322,9 +4322,11 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc, pipeconf &= ~PIPECONF_DOUBLE_WIDE; } - dspcntr |= DISPLAY_PLANE_ENABLE; - pipeconf |= PIPECONF_ENABLE; - dpll |= DPLL_VCO_ENABLE; + if (!HAS_PCH_SPLIT(dev)) { + dspcntr |= DISPLAY_PLANE_ENABLE; + pipeconf |= PIPECONF_ENABLE; + dpll |= DPLL_VCO_ENABLE; + } DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B'); drm_mode_debug_printmodeline(mode); -- 1.7.4.1