[cris-decc0,12/14] cris: Enable 32-bit shifts, clz, bswap, umin to set condition codes.
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Message ID 202002120703.01C73Eiq027061@ignucius.se.axis.com
State New
Headers show
Series
  • Untitled series #158021
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Commit Message

Hans-Peter Nilsson Feb. 12, 2020, 7:03 a.m. UTC
* config/cris/cris.md
("<acc><anz><anzvc><shlr>si3<setcc><setnz><setnzvc>"):
Rename from "<shlr>si3".
("<acc><anz><anzvc>clzsi2<setcc><setnz><setnzvc>"):
Rename from "clzsi2".
("<acc><anz><anzvc>bswapsi2<setcc><setnz><setnzvc>"):
Rename from "bswapsi2".
("*uminsi3<setcc><setnz><setnzvc>"): Rename from "*uminsi3".

Enables dropping of compares with zero of the result, through
any CCmode substitution.
---
 gcc/config/cris/cris.md | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

Patch
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diff --git a/gcc/config/cris/cris.md b/gcc/config/cris/cris.md
index 6faef6cda..c085e2660 100644
--- a/gcc/config/cris/cris.md
+++ b/gcc/config/cris/cris.md
@@ -1758,7 +1758,7 @@  (define_insn "one_cmpl<mode>2"
 
 ;; Arithmetic/Logical shift right (and SI left).
 
-(define_insn "<shlr>si3"
+(define_insn "<acc><anz><anzvc><shlr>si3<setcc><setnz><setnzvc>"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(shift:SI (match_operand:SI 1 "register_operand" "0")
 		  (match_operand:SI 2 "nonmemory_operand" "Kcr")))
@@ -1918,7 +1918,7 @@  (define_expand "abs<mode>2"
   ""
   "operands[2] = gen_reg_rtx (SImode); operands[3] = gen_reg_rtx (SImode);")
 
-(define_insn "clzsi2"
+(define_insn "<acc><anz><anzvc>clzsi2<setcc><setnz><setnzvc>"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(clz:SI (match_operand:SI 1 "register_operand" "r")))
    (clobber (reg:CC CRIS_CC0_REGNUM))]
@@ -1926,7 +1926,7 @@  (define_insn "clzsi2"
   "lz %1,%0"
   [(set_attr "slottable" "yes")])
 
-(define_insn "bswapsi2"
+(define_insn "<acc><anz><anzvc>bswapsi2<setcc><setnz><setnzvc>"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(bswap:SI (match_operand:SI 1 "register_operand" "0")))
    (clobber (reg:CC CRIS_CC0_REGNUM))]
@@ -1979,7 +1979,7 @@  (define_expand "uminsi3"
   ""
   "")
 
-(define_insn "*uminsi3"
+(define_insn "*uminsi3<setcc><setnz><setnzvc>"
   [(set (match_operand:SI 0 "register_operand"		 "=r,r, r,r")
 	(umin:SI  (match_operand:SI 1 "register_operand" "%0,0, 0,r")
 		  (match_operand:SI 2 "general_operand"   "r,Q>,g,!To")))