[2/2] pinctrl: stm32: Add level interrupt support to gpio irq chip
diff mbox series

Message ID 20200210134901.1939-3-alexandre.torgue@st.com
State New
Headers show
Series
  • [1/2] irqchip/stm32: Add irq retrigger support
Related show

Commit Message

Alexandre Torgue Feb. 10, 2020, 1:49 p.m. UTC
This patch adds level interrupt support to gpio irq chip.

GPIO hardware block is directly linked to EXTI block but EXTI handles
external interrupts only on edge. To be able to handle GPIO interrupt on
level a "hack" is done in gpio irq chip: parent interrupt (exti irq chip)
is retriggered following interrupt type and gpio line value.

Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>

Comments

Marek Vasut Feb. 10, 2020, 6:39 p.m. UTC | #1
On 2/10/20 2:49 PM, Alexandre Torgue wrote:
> This patch adds level interrupt support to gpio irq chip.
> 
> GPIO hardware block is directly linked to EXTI block but EXTI handles
> external interrupts only on edge. To be able to handle GPIO interrupt on
> level a "hack" is done in gpio irq chip: parent interrupt (exti irq chip)
> is retriggered following interrupt type and gpio line value.
> 
> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
> 
> diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c b/drivers/pinctrl/stm32/pinctrl-stm32.c
> index 2d5e0435af0a..04e1b062c20e 100644
> --- a/drivers/pinctrl/stm32/pinctrl-stm32.c
> +++ b/drivers/pinctrl/stm32/pinctrl-stm32.c
> @@ -89,6 +89,7 @@ struct stm32_gpio_bank {
>  	struct pinctrl_gpio_range range;
>  	struct fwnode_handle *fwnode;
>  	struct irq_domain *domain;
> +	u32 irq_type[STM32_GPIO_PINS_PER_BANK];

You might want reverse xmas tree order here.

>  	u32 bank_nr;
>  	u32 bank_ioport_nr;
>  	u32 pin_backup[STM32_GPIO_PINS_PER_BANK];
> @@ -303,6 +304,48 @@ static const struct gpio_chip stm32_gpio_template = {
>  	.get_direction		= stm32_gpio_get_direction,
>  };
>  
> +void stm32_gpio_irq_eoi(struct irq_data *d)
> +{
> +	struct stm32_gpio_bank *bank = d->domain->host_data;
> +	int line;
> +
> +	irq_chip_eoi_parent(d);
> +
> +	/* If level interrupt type then retrig */
> +	line = stm32_gpio_get(&bank->gpio_chip, d->hwirq);
> +	if ((line == 0 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_LOW) ||
> +	    (line == 1 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_HIGH))
> +		irq_chip_retrigger_hierarchy(d);
> +};
> +
> +static int stm32_gpio_set_type(struct irq_data *d, unsigned int type)
> +{
> +	struct stm32_gpio_bank *bank = d->domain->host_data;
> +	u32 parent_type;
> +
> +	bank->irq_type[d->hwirq] = type;
> +
> +	switch (type) {
> +	case IRQ_TYPE_EDGE_RISING:
> +	case IRQ_TYPE_EDGE_FALLING:
> +	case IRQ_TYPE_EDGE_BOTH:
> +		parent_type = type;
> +		break;
> +	case IRQ_TYPE_LEVEL_HIGH:
> +		parent_type = IRQ_TYPE_EDGE_RISING;
> +		break;
> +	case IRQ_TYPE_LEVEL_LOW:
> +		parent_type = IRQ_TYPE_EDGE_FALLING;
> +		break;
> +	default:
> +		return -EINVAL;
> +	}
> +
> +	irq_chip_set_type_parent(d, parent_type);

irq_chip_set_type_parent() returns error code, shouldn't that be handled?

Otherwise, tested on STM32MP1 with KSZ8851-16MLL NIC.
Alexandre Torgue Feb. 11, 2020, 10:08 a.m. UTC | #2
Hi Marek

On 2/10/20 7:39 PM, Marek Vasut wrote:
> On 2/10/20 2:49 PM, Alexandre Torgue wrote:
>> This patch adds level interrupt support to gpio irq chip.
>>
>> GPIO hardware block is directly linked to EXTI block but EXTI handles
>> external interrupts only on edge. To be able to handle GPIO interrupt on
>> level a "hack" is done in gpio irq chip: parent interrupt (exti irq chip)
>> is retriggered following interrupt type and gpio line value.
>>
>> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
>>
>> diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c b/drivers/pinctrl/stm32/pinctrl-stm32.c
>> index 2d5e0435af0a..04e1b062c20e 100644
>> --- a/drivers/pinctrl/stm32/pinctrl-stm32.c
>> +++ b/drivers/pinctrl/stm32/pinctrl-stm32.c
>> @@ -89,6 +89,7 @@ struct stm32_gpio_bank {
>>   	struct pinctrl_gpio_range range;
>>   	struct fwnode_handle *fwnode;
>>   	struct irq_domain *domain;
>> +	u32 irq_type[STM32_GPIO_PINS_PER_BANK];
> 
> You might want reverse xmas tree order here.

I agree

> 
>>   	u32 bank_nr;
>>   	u32 bank_ioport_nr;
>>   	u32 pin_backup[STM32_GPIO_PINS_PER_BANK];
>> @@ -303,6 +304,48 @@ static const struct gpio_chip stm32_gpio_template = {
>>   	.get_direction		= stm32_gpio_get_direction,
>>   };
>>   
>> +void stm32_gpio_irq_eoi(struct irq_data *d)
>> +{
>> +	struct stm32_gpio_bank *bank = d->domain->host_data;
>> +	int line;
>> +
>> +	irq_chip_eoi_parent(d);
>> +
>> +	/* If level interrupt type then retrig */
>> +	line = stm32_gpio_get(&bank->gpio_chip, d->hwirq);
>> +	if ((line == 0 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_LOW) ||
>> +	    (line == 1 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_HIGH))
>> +		irq_chip_retrigger_hierarchy(d);
>> +};
>> +
>> +static int stm32_gpio_set_type(struct irq_data *d, unsigned int type)
>> +{
>> +	struct stm32_gpio_bank *bank = d->domain->host_data;
>> +	u32 parent_type;
>> +
>> +	bank->irq_type[d->hwirq] = type;
>> +
>> +	switch (type) {
>> +	case IRQ_TYPE_EDGE_RISING:
>> +	case IRQ_TYPE_EDGE_FALLING:
>> +	case IRQ_TYPE_EDGE_BOTH:
>> +		parent_type = type;
>> +		break;
>> +	case IRQ_TYPE_LEVEL_HIGH:
>> +		parent_type = IRQ_TYPE_EDGE_RISING;
>> +		break;
>> +	case IRQ_TYPE_LEVEL_LOW:
>> +		parent_type = IRQ_TYPE_EDGE_FALLING;
>> +		break;
>> +	default:
>> +		return -EINVAL;
>> +	}
>> +
>> +	irq_chip_set_type_parent(d, parent_type);
> 
> irq_chip_set_type_parent() returns error code, shouldn't that be handled?

Yes. It'll be fixed in v2.

> 
> Otherwise, tested on STM32MP1 with KSZ8851-16MLL NIC.

Thanks
Marc Zyngier Feb. 19, 2020, 11:19 a.m. UTC | #3
On 2020-02-11 10:08, Alexandre Torgue wrote:

[...]

> Yes. It'll be fixed in v2.

And when you do that, please use my official email address (my @arm.com
address goes to my ex manager, and I don't think he cares much about 
this).

         M.
Alexandre Torgue Feb. 19, 2020, 11:30 a.m. UTC | #4
On 2/19/20 12:19 PM, Marc Zyngier wrote:
> On 2020-02-11 10:08, Alexandre Torgue wrote:
> 
> [...]
> 
>> Yes. It'll be fixed in v2.
> 
> And when you do that, please use my official email address (my @arm.com
> address goes to my ex manager, and I don't think he cares much about this).

Ok I update my script.

Alex

> 
>          M.
Marc Zyngier Feb. 19, 2020, 11:39 a.m. UTC | #5
On 2020-02-19 11:30, Alexandre Torgue wrote:
> On 2/19/20 12:19 PM, Marc Zyngier wrote:
>> On 2020-02-11 10:08, Alexandre Torgue wrote:
>> 
>> [...]
>> 
>>> Yes. It'll be fixed in v2.
>> 
>> And when you do that, please use my official email address (my 
>> @arm.com
>> address goes to my ex manager, and I don't think he cares much about 
>> this).
> 
> Ok I update my script.

Surely your script is a wrapper around scripts/get_maintainer.pl, right?

         M.
Alexandre Torgue Feb. 19, 2020, 11:48 a.m. UTC | #6
On 2/19/20 12:39 PM, Marc Zyngier wrote:
> On 2020-02-19 11:30, Alexandre Torgue wrote:
>> On 2/19/20 12:19 PM, Marc Zyngier wrote:
>>> On 2020-02-11 10:08, Alexandre Torgue wrote:
>>>
>>> [...]
>>>
>>>> Yes. It'll be fixed in v2.
>>>
>>> And when you do that, please use my official email address (my @arm.com
>>> address goes to my ex manager, and I don't think he cares much about 
>>> this).
>>
>> Ok I update my script.
> 
> Surely your script is a wrapper around scripts/get_maintainer.pl, right?

No. it's an old script which create groups (hard coded) to be used for 
git send-mail. But yes, a good improvement would be to use 
get_maintainer.pl.

> 
>          M.

Patch
diff mbox series

diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c b/drivers/pinctrl/stm32/pinctrl-stm32.c
index 2d5e0435af0a..04e1b062c20e 100644
--- a/drivers/pinctrl/stm32/pinctrl-stm32.c
+++ b/drivers/pinctrl/stm32/pinctrl-stm32.c
@@ -89,6 +89,7 @@  struct stm32_gpio_bank {
 	struct pinctrl_gpio_range range;
 	struct fwnode_handle *fwnode;
 	struct irq_domain *domain;
+	u32 irq_type[STM32_GPIO_PINS_PER_BANK];
 	u32 bank_nr;
 	u32 bank_ioport_nr;
 	u32 pin_backup[STM32_GPIO_PINS_PER_BANK];
@@ -303,6 +304,48 @@  static const struct gpio_chip stm32_gpio_template = {
 	.get_direction		= stm32_gpio_get_direction,
 };
 
+void stm32_gpio_irq_eoi(struct irq_data *d)
+{
+	struct stm32_gpio_bank *bank = d->domain->host_data;
+	int line;
+
+	irq_chip_eoi_parent(d);
+
+	/* If level interrupt type then retrig */
+	line = stm32_gpio_get(&bank->gpio_chip, d->hwirq);
+	if ((line == 0 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_LOW) ||
+	    (line == 1 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_HIGH))
+		irq_chip_retrigger_hierarchy(d);
+};
+
+static int stm32_gpio_set_type(struct irq_data *d, unsigned int type)
+{
+	struct stm32_gpio_bank *bank = d->domain->host_data;
+	u32 parent_type;
+
+	bank->irq_type[d->hwirq] = type;
+
+	switch (type) {
+	case IRQ_TYPE_EDGE_RISING:
+	case IRQ_TYPE_EDGE_FALLING:
+	case IRQ_TYPE_EDGE_BOTH:
+		parent_type = type;
+		break;
+	case IRQ_TYPE_LEVEL_HIGH:
+		parent_type = IRQ_TYPE_EDGE_RISING;
+		break;
+	case IRQ_TYPE_LEVEL_LOW:
+		parent_type = IRQ_TYPE_EDGE_FALLING;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	irq_chip_set_type_parent(d, parent_type);
+
+	return 0;
+};
+
 static int stm32_gpio_irq_request_resources(struct irq_data *irq_data)
 {
 	struct stm32_gpio_bank *bank = irq_data->domain->host_data;
@@ -332,11 +375,11 @@  static void stm32_gpio_irq_release_resources(struct irq_data *irq_data)
 
 static struct irq_chip stm32_gpio_irq_chip = {
 	.name		= "stm32gpio",
-	.irq_eoi	= irq_chip_eoi_parent,
+	.irq_eoi	= stm32_gpio_irq_eoi,
 	.irq_ack	= irq_chip_ack_parent,
 	.irq_mask	= irq_chip_mask_parent,
 	.irq_unmask	= irq_chip_unmask_parent,
-	.irq_set_type	= irq_chip_set_type_parent,
+	.irq_set_type	= stm32_gpio_set_type,
 	.irq_set_wake	= irq_chip_set_wake_parent,
 	.irq_request_resources = stm32_gpio_irq_request_resources,
 	.irq_release_resources = stm32_gpio_irq_release_resources,