diff mbox

[i386] : Use {} for multi-line preparation statements.

Message ID CAFULd4YW_NCrTQ6nFAzEQU1F9JJzE+ztmebjyw8mmCJ0SqZ_Fg@mail.gmail.com
State New
Headers show

Commit Message

Uros Bizjak Nov. 3, 2011, 5:01 p.m. UTC 
Hello!

No functional change.

2011-11-03  Uros Bizjak  <ubizjak@gmail.com>

	* config/i386/i386.md: Use {} for multi-line preparation statements.

Bootstrapped and regression tested on x86_64-pc-linux-gnu, committed
to mainline SVN.

Uros.
diff mbox

Patch

Index: i386.md
===================================================================
--- i386.md	(revision 180818)
+++ i386.md	(working copy)
@@ -7702,8 +7702,10 @@ 
 	  [(and:SI (zero_extract:SI (match_dup 2) (const_int 8) (const_int 8))
 		   (match_dup 3))
 	   (const_int 0)]))]
-  "operands[2] = gen_lowpart (SImode, operands[2]);
-   operands[3] = gen_int_mode (INTVAL (operands[3]) >> 8, SImode);")
+{
+  operands[2] = gen_lowpart (SImode, operands[2]);
+  operands[3] = gen_int_mode (INTVAL (operands[3]) >> 8, SImode);
+})
 
 (define_split
   [(set (match_operand 0 "flags_reg_operand" "")
@@ -7721,8 +7723,10 @@ 
   [(set (match_dup 0)
 	(match_op_dup 1 [(and:QI (match_dup 2) (match_dup 3))
 			 (const_int 0)]))]
-  "operands[2] = gen_lowpart (QImode, operands[2]);
-   operands[3] = gen_lowpart (QImode, operands[3]);")
+{
+  operands[2] = gen_lowpart (QImode, operands[2]);
+  operands[3] = gen_lowpart (QImode, operands[3]);
+})
 
 ;; %%% This used to optimize known byte-wide and operations to memory,
 ;; and sometimes to QImode registers.  If this is considered useful,
@@ -8147,9 +8151,11 @@ 
 					    (const_int 8) (const_int 8))
 			   (match_dup 2)))
 	      (clobber (reg:CC FLAGS_REG))])]
-  "operands[0] = gen_lowpart (SImode, operands[0]);
-   operands[1] = gen_lowpart (SImode, operands[1]);
-   operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);")
+{
+  operands[0] = gen_lowpart (SImode, operands[0]);
+  operands[1] = gen_lowpart (SImode, operands[1]);
+  operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);
+})
 
 ;; Since AND can be encoded with sign extended immediate, this is only
 ;; profitable when 7th bit is not set.
@@ -8168,9 +8174,11 @@ 
 		   (and:QI (match_dup 1)
 			   (match_dup 2)))
 	      (clobber (reg:CC FLAGS_REG))])]
-  "operands[0] = gen_lowpart (QImode, operands[0]);
-   operands[1] = gen_lowpart (QImode, operands[1]);
-   operands[2] = gen_lowpart (QImode, operands[2]);")
+{
+  operands[0] = gen_lowpart (QImode, operands[0]);
+  operands[1] = gen_lowpart (QImode, operands[1]);
+  operands[2] = gen_lowpart (QImode, operands[2]);
+})
 
 ;; Logical inclusive and exclusive OR instructions
 
@@ -8402,9 +8410,11 @@ 
 					       (const_int 8) (const_int 8))
 			      (match_dup 2)))
 	      (clobber (reg:CC FLAGS_REG))])]
-  "operands[0] = gen_lowpart (SImode, operands[0]);
-   operands[1] = gen_lowpart (SImode, operands[1]);
-   operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);")
+{
+  operands[0] = gen_lowpart (SImode, operands[0]);
+  operands[1] = gen_lowpart (SImode, operands[1]);
+  operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);
+})
 
 ;; Since OR can be encoded with sign extended immediate, this is only
 ;; profitable when 7th bit is set.
@@ -8423,9 +8433,11 @@ 
 		   (any_or:QI (match_dup 1)
 			      (match_dup 2)))
 	      (clobber (reg:CC FLAGS_REG))])]
-  "operands[0] = gen_lowpart (QImode, operands[0]);
-   operands[1] = gen_lowpart (QImode, operands[1]);
-   operands[2] = gen_lowpart (QImode, operands[2]);")
+{
+  operands[0] = gen_lowpart (QImode, operands[0]);
+  operands[1] = gen_lowpart (QImode, operands[1]);
+  operands[2] = gen_lowpart (QImode, operands[2]);
+})
 
 (define_expand "xorqi_cc_ext_1"
   [(parallel [
@@ -16631,15 +16643,19 @@ 
 
   ;; The % modifier is not operational anymore in peephole2's, so we have to
   ;; swap the operands manually in the case of addition and multiplication.
-  "if (COMMUTATIVE_ARITH_P (operands[2]))
-     operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[2]),
-				   GET_MODE (operands[2]),
-				   operands[0], operands[1]);
-   else
-     operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[2]),
-				   GET_MODE (operands[2]),
-				   operands[1], operands[0]);")
+{
+  rtx op0, op1;
 
+  if (COMMUTATIVE_ARITH_P (operands[2]))
+    op0 = operands[0], op1 = operands[1];
+  else
+    op0 = operands[1], op1 = operands[0];
+
+  operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[2]),
+				GET_MODE (operands[2]),
+				op0, op1);
+})
+
 ;; Conditional addition patterns
 (define_expand "add<mode>cc"
   [(match_operand:SWI 0 "register_operand" "")
@@ -16837,11 +16853,13 @@ 
   [(parallel [(set (match_dup 0)
 		   (match_op_dup 3 [(match_dup 1) (match_dup 2)]))
 	      (clobber (reg:CC FLAGS_REG))])]
-  "operands[0] = gen_lowpart (SImode, operands[0]);
-   operands[1] = gen_lowpart (SImode, operands[1]);
-   if (GET_CODE (operands[3]) != ASHIFT)
-     operands[2] = gen_lowpart (SImode, operands[2]);
-   PUT_MODE (operands[3], SImode);")
+{
+  operands[0] = gen_lowpart (SImode, operands[0]);
+  operands[1] = gen_lowpart (SImode, operands[1]);
+  if (GET_CODE (operands[3]) != ASHIFT)
+    operands[2] = gen_lowpart (SImode, operands[2]);
+  PUT_MODE (operands[3], SImode);
+})
 
 ; Promote the QImode tests, as i386 has encoding of the AND
 ; instruction with 32-bit sign-extended immediate and thus the
@@ -16911,8 +16929,10 @@ 
   [(parallel [(set (match_dup 0)
 		   (neg:SI (match_dup 1)))
 	      (clobber (reg:CC FLAGS_REG))])]
-  "operands[0] = gen_lowpart (SImode, operands[0]);
-   operands[1] = gen_lowpart (SImode, operands[1]);")
+{
+  operands[0] = gen_lowpart (SImode, operands[0]);
+  operands[1] = gen_lowpart (SImode, operands[1]);
+})
 
 (define_split
   [(set (match_operand 0 "register_operand" "")
@@ -16924,8 +16944,10 @@ 
 	       || optimize_insn_for_size_p ())))"
   [(set (match_dup 0)
 	(not:SI (match_dup 1)))]
-  "operands[0] = gen_lowpart (SImode, operands[0]);
-   operands[1] = gen_lowpart (SImode, operands[1]);")
+{
+  operands[0] = gen_lowpart (SImode, operands[0]);
+  operands[1] = gen_lowpart (SImode, operands[1]);
+})
 
 (define_split
   [(set (match_operand 0 "register_operand" "")
@@ -16940,9 +16962,11 @@ 
 	       || optimize_insn_for_size_p ())))"
   [(set (match_dup 0)
 	(if_then_else:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
-  "operands[0] = gen_lowpart (SImode, operands[0]);
-   operands[2] = gen_lowpart (SImode, operands[2]);
-   operands[3] = gen_lowpart (SImode, operands[3]);")
+{
+  operands[0] = gen_lowpart (SImode, operands[0]);
+  operands[2] = gen_lowpart (SImode, operands[2]);
+  operands[3] = gen_lowpart (SImode, operands[3]);
+})
 
 ;; RTL Peephole optimizations, run before sched2.  These primarily look to
 ;; transform a complex memory operation into two memory to register operations.
@@ -17228,12 +17252,14 @@ 
   [(parallel [(set (match_dup 4) (match_dup 5))
 	      (set (match_dup 1) (match_op_dup 3 [(match_dup 1)
 						  (match_dup 2)]))])]
-  "operands[4] = SET_DEST (PATTERN (peep2_next_insn (3)));
-   operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), <MODE>mode,
-				 copy_rtx (operands[1]),
-				 copy_rtx (operands[2]));
-   operands[5] = gen_rtx_COMPARE (GET_MODE (operands[4]),
-				  operands[5], const0_rtx);")
+{
+  operands[4] = SET_DEST (PATTERN (peep2_next_insn (3)));
+  operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), <MODE>mode,
+				copy_rtx (operands[1]),
+				copy_rtx (operands[2]));
+  operands[5] = gen_rtx_COMPARE (GET_MODE (operands[4]),
+				 operands[5], const0_rtx);
+})
 
 (define_peephole2
   [(parallel [(set (match_operand:SWI 0 "register_operand" "")
@@ -17253,12 +17279,14 @@ 
   [(parallel [(set (match_dup 3) (match_dup 4))
 	      (set (match_dup 1) (match_op_dup 2 [(match_dup 1)
 						  (match_dup 0)]))])]
-  "operands[3] = SET_DEST (PATTERN (peep2_next_insn (2)));
-   operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[2]), <MODE>mode,
-				 copy_rtx (operands[1]),
-				 copy_rtx (operands[0]));
-   operands[4] = gen_rtx_COMPARE (GET_MODE (operands[3]),
-				  operands[4], const0_rtx);")
+{
+  operands[3] = SET_DEST (PATTERN (peep2_next_insn (2)));
+  operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[2]), <MODE>mode,
+				copy_rtx (operands[1]),
+				copy_rtx (operands[0]));
+  operands[4] = gen_rtx_COMPARE (GET_MODE (operands[3]),
+				 operands[4], const0_rtx);
+})
 
 (define_peephole2
   [(set (match_operand:SWI12 0 "register_operand" "")
@@ -17281,15 +17309,17 @@ 
 			 ? CCGOCmode : CCNOmode)"
   [(parallel [(set (match_dup 4) (match_dup 5))
 	      (set (match_dup 1) (match_dup 6))])]
-  "operands[2] = gen_lowpart (<MODE>mode, operands[2]);
-   operands[4] = SET_DEST (PATTERN (peep2_next_insn (3)));
-   operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), <MODE>mode,
-				 copy_rtx (operands[1]), operands[2]);
-   operands[5] = gen_rtx_COMPARE (GET_MODE (operands[4]),
-				  operands[5], const0_rtx);
-   operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[3]), <MODE>mode,
-				 copy_rtx (operands[1]),
-				 copy_rtx (operands[2]));")
+{
+  operands[2] = gen_lowpart (<MODE>mode, operands[2]);
+  operands[4] = SET_DEST (PATTERN (peep2_next_insn (3)));
+  operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), <MODE>mode,
+				copy_rtx (operands[1]), operands[2]);
+  operands[5] = gen_rtx_COMPARE (GET_MODE (operands[4]),
+				 operands[5], const0_rtx);
+  operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[3]), <MODE>mode,
+				copy_rtx (operands[1]),
+				copy_rtx (operands[2]));
+})
 
 ;; Attempt to always use XOR for zeroing registers.
 (define_peephole2
@@ -18075,8 +18105,8 @@ 
 		     (match_operand:SI 3 "const_int_operand" "i")]
 		    UNSPECV_LWPVAL_INTRINSIC)]
   "TARGET_LWP"
-  "/* Avoid unused variable warning.  */
-   (void) operand0;")
+  ;; Avoid unused variable warning.
+  "(void) operand0;")
 
 (define_insn "*lwp_lwpval<mode>3_1"
   [(unspec_volatile [(match_operand:SWI48 0 "register_operand" "r")