Patchwork [SPARC] Consolidate movtf patterns

login
register
mail settings
Submitter Eric Botcazou
Date Nov. 3, 2011, 4:26 p.m.
Message ID <201111031726.28803.ebotcazou@adacore.com>
Download mbox | patch
Permalink /patch/123467/
State New
Headers show

Comments

Eric Botcazou - Nov. 3, 2011, 4:26 p.m.
Tested on SPARC/Solaris, applied on the mainline.


2011-11-03  Eric Botcazou  <ebotcazou@adacore.com>

	* config/sparc/sparc.md (movtf_insn_sp32_no_fpu): Consolidate into...
	(movtf_insn_sp32): ...this.
	(movtf_insn_sp64_no_fpu): Consolidate into...
	(movtf_insn_sp64): ...this.
	(movtf_insn_sp64_hq): Do not test TARGET_FPU.
	* config/sparc/sparc.c (sparc_legitimate_address_p): Likewise.
David Miller - Nov. 4, 2011, 6:22 a.m.
From: Eric Botcazou <ebotcazou@adacore.com>
Date: Thu, 3 Nov 2011 17:26:28 +0100

> Tested on SPARC/Solaris, applied on the mainline.

Thanks for doing this work Eric.

Patch

Index: config/sparc/sparc.md
===================================================================
--- config/sparc/sparc.md	(revision 180818)
+++ config/sparc/sparc.md	(working copy)
@@ -2377,45 +2377,30 @@  (define_expand "movtf"
 })
 
 (define_insn "*movtf_insn_sp32"
-  [(set (match_operand:TF 0 "nonimmediate_operand" "=b, e,   o,U,  r")
-	(match_operand:TF 1 "input_operand"        " G,oe,GeUr,o,roG"))]
-  "TARGET_FPU
-   && ! TARGET_ARCH64
+  [(set (match_operand:TF 0 "nonimmediate_operand" "=b, e,o,  o,U,  r")
+	(match_operand:TF 1 "input_operand"        " G,oe,e,rGU,o,roG"))]
+  "! TARGET_ARCH64
    && (register_operand (operands[0], TFmode)
        || register_or_zero_operand (operands[1], TFmode))"
   "#"
-  [(set_attr "length" "4")])
-
-;; Exactly the same as above, except that all `e' cases are deleted.
-;; This is necessary to prevent reload from ever trying to use a `e' reg
-;; when -mno-fpu.
-
-(define_insn "*movtf_insn_sp32_no_fpu"
-  [(set (match_operand:TF 0 "nonimmediate_operand" "=o,U,o,  r,o")
-	(match_operand:TF 1 "input_operand"        " G,o,U,roG,r"))]
-  "! TARGET_FPU
-   && ! TARGET_ARCH64
-   && (register_operand (operands[0], TFmode)
-       || register_or_zero_operand (operands[1], TFmode))"
-  "#"
-  [(set_attr "length" "4")])
+  [(set_attr "length" "4,4,4,4,4,4")
+   (set_attr "cpu_feature" "fpu,fpu,fpu,*,*,*")])
 
 (define_insn "*movtf_insn_sp64"
-  [(set (match_operand:TF 0 "nonimmediate_operand" "=b, e,  o,  r")
-	(match_operand:TF 1 "input_operand"         "G,oe,Ger,roG"))]
-  "TARGET_FPU
-   && TARGET_ARCH64
+  [(set (match_operand:TF 0 "nonimmediate_operand" "=b, e,o, o,  r")
+	(match_operand:TF 1 "input_operand"         "G,oe,e,rG,roG"))]
+  "TARGET_ARCH64
    && ! TARGET_HARD_QUAD
    && (register_operand (operands[0], TFmode)
        || register_or_zero_operand (operands[1], TFmode))"
   "#"
-  [(set_attr "length" "2")])
+  [(set_attr "length" "2,2,2,2,2")
+   (set_attr "cpu_feature" "fpu,fpu,fpu,*,*")])
 
 (define_insn "*movtf_insn_sp64_hq"
   [(set (match_operand:TF 0 "nonimmediate_operand" "=b,e,e,m, o,  r")
 	(match_operand:TF 1 "input_operand"         "G,e,m,e,rG,roG"))]
-  "TARGET_FPU
-   && TARGET_ARCH64
+  "TARGET_ARCH64
    && TARGET_HARD_QUAD
    && (register_operand (operands[0], TFmode)
        || register_or_zero_operand (operands[1], TFmode))"
@@ -2429,16 +2414,6 @@  (define_insn "*movtf_insn_sp64_hq"
   [(set_attr "type" "*,fpmove,fpload,fpstore,*,*")
    (set_attr "length" "2,*,*,*,2,2")])
 
-(define_insn "*movtf_insn_sp64_no_fpu"
-  [(set (match_operand:TF 0 "nonimmediate_operand" "=  r, o")
-	(match_operand:TF 1 "input_operand"         "orG,rG"))]
-  "! TARGET_FPU
-   && TARGET_ARCH64
-   && (register_operand (operands[0], TFmode)
-       || register_or_zero_operand (operands[1], TFmode))"
-  "#"
-  [(set_attr "length" "2")])
-
 ;; Now all the splits to handle multi-insn TF mode moves.
 (define_split
   [(set (match_operand:TF 0 "register_operand" "")
Index: config/sparc/sparc.c
===================================================================
--- config/sparc/sparc.c	(revision 180818)
+++ config/sparc/sparc.c	(working copy)
@@ -3440,7 +3440,7 @@  sparc_legitimate_address_p (enum machine
 	     REG+REG address, then only one of them gets converted to an
 	     offsettable address.  */
 	  if (mode == TFmode
-	      && ! (TARGET_FPU && TARGET_ARCH64 && TARGET_HARD_QUAD))
+	      && ! (TARGET_ARCH64 && TARGET_HARD_QUAD))
 	    return 0;
 
 	  /* We prohibit REG + REG on ARCH32 if not optimizing for