| Message ID | 20200206202206.14770-4-sshivamurthy@micron.com |
|---|---|
| State | Changes Requested |
| Delegated to: | Miquel Raynal |
| Headers | show |
| Series | Add new series Micron SPI NAND devices | expand |
On Thu, 6 Feb 2020 21:22:04 +0100 shiva.linuxworks@gmail.com wrote: > From: Shivamurthy Shastri <sshivamurthy@micron.com> > > Add SPINAND_HAS_CR_FEAT_BIT flag to identify the SPI NAND device with > the Continuous Read mode. > > Some of the Micron SPI NAND devices have the "Continuous Read" feature > enabled by default, which does not fit the subsystem needs. > > In this mode, the READ CACHE command doesn't require the starting column > address. The device always output the data starting from the first > column of the cache register, and once the end of the cache register > reached, the data output continues through the next page. With the > continuous read mode, it is possible to read out the entire block using > a single READ command, and once the end of the block reached, the output > pins become High-Z state. However, during this mode the read command > doesn't output the OOB area. > > Hence, we disable the feature at probe time. > > Signed-off-by: Shivamurthy Shastri <sshivamurthy@micron.com> > --- > drivers/mtd/nand/spi/micron.c | 16 ++++++++++++++++ > include/linux/mtd/spinand.h | 1 + > 2 files changed, 17 insertions(+) > > diff --git a/drivers/mtd/nand/spi/micron.c b/drivers/mtd/nand/spi/micron.c > index 5fd1f921ef12..a8e947609cd9 100644 > --- a/drivers/mtd/nand/spi/micron.c > +++ b/drivers/mtd/nand/spi/micron.c > @@ -18,6 +18,8 @@ > #define MICRON_STATUS_ECC_4TO6_BITFLIPS (3 << 4) > #define MICRON_STATUS_ECC_7TO8_BITFLIPS (5 << 4) > > +#define MICRON_CFG_CONTI_READ BIT(0) Let's try to use consistent names. The feature bit is SPINAND_HAS_CR_FEAT_BIT, so maybe MICRON_CFG_CR. BTW, is this really a micron-specific bit? > + > static SPINAND_OP_VARIANTS(read_cache_variants, > SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0), > SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), > @@ -153,8 +155,22 @@ static int micron_spinand_detect(struct spinand_device *spinand) > return 1; > } > > +static int micron_spinand_init(struct spinand_device *spinand) > +{ > + /* > + * M70A device series enable Continuous Read feature at Power-up, > + * which is not supported. Disable this bit to avoid any possible > + * failure. > + */ > + if (spinand->flags == SPINAND_HAS_CR_FEAT_BIT) if (spinand->flags & SPINAND_HAS_CR_FEAT_BIT) > + return spinand_upd_cfg(spinand, MICRON_CFG_CONTI_READ, 0); > + > + return 0; > +} > + > static const struct spinand_manufacturer_ops micron_spinand_manuf_ops = { > .detect = micron_spinand_detect, > + .init = micron_spinand_init, > }; > > const struct spinand_manufacturer micron_spinand_manufacturer = { > diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h > index 4ea558bd3c46..333149b2855f 100644 > --- a/include/linux/mtd/spinand.h > +++ b/include/linux/mtd/spinand.h > @@ -270,6 +270,7 @@ struct spinand_ecc_info { > }; > > #define SPINAND_HAS_QE_BIT BIT(0) > +#define SPINAND_HAS_CR_FEAT_BIT BIT(1) > > /** > * struct spinand_info - Structure used to describe SPI NAND chips
Hi Boris, Thanks for the review. > > On Thu, 6 Feb 2020 21:22:04 +0100 > shiva.linuxworks@gmail.com wrote: > > > From: Shivamurthy Shastri <sshivamurthy@micron.com> > > > > Add SPINAND_HAS_CR_FEAT_BIT flag to identify the SPI NAND device with > > the Continuous Read mode. > > > > Some of the Micron SPI NAND devices have the "Continuous Read" feature > > enabled by default, which does not fit the subsystem needs. > > > > In this mode, the READ CACHE command doesn't require the starting > column > > address. The device always output the data starting from the first > > column of the cache register, and once the end of the cache register > > reached, the data output continues through the next page. With the > > continuous read mode, it is possible to read out the entire block using > > a single READ command, and once the end of the block reached, the > output > > pins become High-Z state. However, during this mode the read command > > doesn't output the OOB area. > > > > Hence, we disable the feature at probe time. > > > > Signed-off-by: Shivamurthy Shastri <sshivamurthy@micron.com> > > --- > > drivers/mtd/nand/spi/micron.c | 16 ++++++++++++++++ > > include/linux/mtd/spinand.h | 1 + > > 2 files changed, 17 insertions(+) > > > > diff --git a/drivers/mtd/nand/spi/micron.c > b/drivers/mtd/nand/spi/micron.c > > index 5fd1f921ef12..a8e947609cd9 100644 > > --- a/drivers/mtd/nand/spi/micron.c > > +++ b/drivers/mtd/nand/spi/micron.c > > @@ -18,6 +18,8 @@ > > #define MICRON_STATUS_ECC_4TO6_BITFLIPS (3 << 4) > > #define MICRON_STATUS_ECC_7TO8_BITFLIPS (5 << 4) > > > > +#define MICRON_CFG_CONTI_READ BIT(0) > > Let's try to use consistent names. The feature bit is > SPINAND_HAS_CR_FEAT_BIT, so maybe MICRON_CFG_CR. BTW, is this really > a > micron-specific bit? I will change the name. Yes, only Micron uses this BIT for Continuous Read feature. > > > + > > static SPINAND_OP_VARIANTS(read_cache_variants, > > SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, > NULL, 0), > > SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), > > @@ -153,8 +155,22 @@ static int micron_spinand_detect(struct > spinand_device *spinand) > > return 1; > > } > > > > +static int micron_spinand_init(struct spinand_device *spinand) > > +{ > > + /* > > + * M70A device series enable Continuous Read feature at Power-up, > > + * which is not supported. Disable this bit to avoid any possible > > + * failure. > > + */ > > + if (spinand->flags == SPINAND_HAS_CR_FEAT_BIT) > > if (spinand->flags & SPINAND_HAS_CR_FEAT_BIT) Okay. > > > + return spinand_upd_cfg(spinand, > MICRON_CFG_CONTI_READ, 0); > > + > > + return 0; > > +} > > + > > static const struct spinand_manufacturer_ops > micron_spinand_manuf_ops = { > > .detect = micron_spinand_detect, > > + .init = micron_spinand_init, > > }; > > > > const struct spinand_manufacturer micron_spinand_manufacturer = { > > diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h > > index 4ea558bd3c46..333149b2855f 100644 > > --- a/include/linux/mtd/spinand.h > > +++ b/include/linux/mtd/spinand.h > > @@ -270,6 +270,7 @@ struct spinand_ecc_info { > > }; > > > > #define SPINAND_HAS_QE_BIT BIT(0) > > +#define SPINAND_HAS_CR_FEAT_BIT BIT(1) > > > > /** > > * struct spinand_info - Structure used to describe SPI NAND chips
diff --git a/drivers/mtd/nand/spi/micron.c b/drivers/mtd/nand/spi/micron.c index 5fd1f921ef12..a8e947609cd9 100644 --- a/drivers/mtd/nand/spi/micron.c +++ b/drivers/mtd/nand/spi/micron.c @@ -18,6 +18,8 @@ #define MICRON_STATUS_ECC_4TO6_BITFLIPS (3 << 4) #define MICRON_STATUS_ECC_7TO8_BITFLIPS (5 << 4) +#define MICRON_CFG_CONTI_READ BIT(0) + static SPINAND_OP_VARIANTS(read_cache_variants, SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0), SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), @@ -153,8 +155,22 @@ static int micron_spinand_detect(struct spinand_device *spinand) return 1; } +static int micron_spinand_init(struct spinand_device *spinand) +{ + /* + * M70A device series enable Continuous Read feature at Power-up, + * which is not supported. Disable this bit to avoid any possible + * failure. + */ + if (spinand->flags == SPINAND_HAS_CR_FEAT_BIT) + return spinand_upd_cfg(spinand, MICRON_CFG_CONTI_READ, 0); + + return 0; +} + static const struct spinand_manufacturer_ops micron_spinand_manuf_ops = { .detect = micron_spinand_detect, + .init = micron_spinand_init, }; const struct spinand_manufacturer micron_spinand_manufacturer = { diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h index 4ea558bd3c46..333149b2855f 100644 --- a/include/linux/mtd/spinand.h +++ b/include/linux/mtd/spinand.h @@ -270,6 +270,7 @@ struct spinand_ecc_info { }; #define SPINAND_HAS_QE_BIT BIT(0) +#define SPINAND_HAS_CR_FEAT_BIT BIT(1) /** * struct spinand_info - Structure used to describe SPI NAND chips