Patchwork powerpc/4xx: Add L2 cache node to AMCC Canyonlands dts file

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Submitter Stefan Roese
Date Dec. 5, 2008, 6:08 a.m.
Message ID <1228457332-523-1-git-send-email-sr@denx.de>
Download mbox | patch
Permalink /patch/12345/
State Superseded, archived
Headers show

Comments

Stefan Roese - Dec. 5, 2008, 6:08 a.m.
With this patch the L2 cache is enabled on Canyonlands to increase the
overall performance. There is a known cache coherency issue with the L2
cache, but this is related to the high bandwidth (HB) PLB segment where
the memory address is 0x8.xxxx.xxxx (low bandwidth PLB segment is mapped
to 0x0.xxxx.xxxx). Since this HB address is currently unused it is safe
to enable the L2 cache.

Signed-off-by: Stefan Roese <sr@denx.de>
---
 arch/powerpc/boot/dts/canyonlands.dts |   10 ++++++++++
 1 files changed, 10 insertions(+), 0 deletions(-)
Josh Boyer - Dec. 5, 2008, 11:08 a.m.
On Fri,  5 Dec 2008 07:08:52 +0100
Stefan Roese <sr@denx.de> wrote:

> With this patch the L2 cache is enabled on Canyonlands to increase the
> overall performance. There is a known cache coherency issue with the L2
> cache, but this is related to the high bandwidth (HB) PLB segment where
> the memory address is 0x8.xxxx.xxxx (low bandwidth PLB segment is mapped
> to 0x0.xxxx.xxxx). Since this HB address is currently unused it is safe
> to enable the L2 cache.
> 
> Signed-off-by: Stefan Roese <sr@denx.de>
> ---
>  arch/powerpc/boot/dts/canyonlands.dts |   10 ++++++++++
>  1 files changed, 10 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/powerpc/boot/dts/canyonlands.dts b/arch/powerpc/boot/dts/canyonlands.dts
> index 79fe412..0d77482 100644
> --- a/arch/powerpc/boot/dts/canyonlands.dts
> +++ b/arch/powerpc/boot/dts/canyonlands.dts
> @@ -104,6 +104,16 @@
>  		dcr-reg = <0x00c 0x002>;
>  	};
> 
> +	L2C0: l2c {
> +		compatible = "ibm,l2-cache-460ex", "ibm,l2-cache";
> +		dcr-reg = <0x020 0x008		/* Internal SRAM DCR's */
> +			   0x030 0x008>;	/* L2 cache DCR's */
> +		cache-line-size = <32>;		/* 32 bytes */
> +		cache-size = <262144>;		/* L2, 256K */
> +		interrupt-parent = <&UIC1>;
> +		interrupts = <11 1>;
> +	};

Shouldn't there also be a next-level-cache property added to the cpu
node that references this?

josh
Benjamin Herrenschmidt - Dec. 5, 2008, 11:11 a.m.
On Fri, 2008-12-05 at 06:08 -0500, Josh Boyer wrote:
> Shouldn't there also be a next-level-cache property added to the cpu
> node that references this?
> 
It would be nice indeed, it would allow the kernel to expose the cache
info in sysfs

Cheers,
Ben.
Stefan Roese - Dec. 5, 2008, 11:17 a.m.
On Friday 05 December 2008, Benjamin Herrenschmidt wrote:
> On Fri, 2008-12-05 at 06:08 -0500, Josh Boyer wrote:
> > Shouldn't there also be a next-level-cache property added to the cpu
> > node that references this?
>
> It would be nice indeed, it would allow the kernel to expose the cache
> info in sysfs

OK, I'll send an updated version in a short while (lunch time first :)).

Best regards,
Stefan
Nathan Lynch - Dec. 5, 2008, 9:04 p.m.
Benjamin Herrenschmidt wrote:
> On Fri, 2008-12-05 at 06:08 -0500, Josh Boyer wrote:
> > Shouldn't there also be a next-level-cache property added to the cpu
> > node that references this?
> > 
> It would be nice indeed, it would allow the kernel to expose the cache
> info in sysfs

Currently the kernel only knows about the 'l2-cache' property and not
'next-level-cache'.  I've got patches to fix that, will post them
soon.

Patch

diff --git a/arch/powerpc/boot/dts/canyonlands.dts b/arch/powerpc/boot/dts/canyonlands.dts
index 79fe412..0d77482 100644
--- a/arch/powerpc/boot/dts/canyonlands.dts
+++ b/arch/powerpc/boot/dts/canyonlands.dts
@@ -104,6 +104,16 @@ 
 		dcr-reg = <0x00c 0x002>;
 	};
 
+	L2C0: l2c {
+		compatible = "ibm,l2-cache-460ex", "ibm,l2-cache";
+		dcr-reg = <0x020 0x008		/* Internal SRAM DCR's */
+			   0x030 0x008>;	/* L2 cache DCR's */
+		cache-line-size = <32>;		/* 32 bytes */
+		cache-size = <262144>;		/* L2, 256K */
+		interrupt-parent = <&UIC1>;
+		interrupts = <11 1>;
+	};
+
 	plb {
 		compatible = "ibm,plb-460ex", "ibm,plb4";
 		#address-cells = <2>;