Patchwork Handle V4HI vector initialization more efficiently on VIS1.

login
register
mail settings
Submitter David Miller
Date Nov. 1, 2011, 11:45 p.m.
Message ID <20111101.194514.905931458608194041.davem@davemloft.net>
Download mbox | patch
Permalink /patch/123192/
State New
Headers show

Comments

David Miller - Nov. 1, 2011, 11:45 p.m.
Committed to trunk.

gcc/

	* config/sparc/sparc.c (vector_init_faligndata): New function.
	(sparc_expand_vector_init): Use it for V4HImode on VIS1.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@180752 138bc75d-0d04-0410-961f-82ee72b054a4
---
 gcc/ChangeLog            |    3 +++
 gcc/config/sparc/sparc.c |   24 ++++++++++++++++++++++++
 2 files changed, 27 insertions(+), 0 deletions(-)

Patch

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 9c75318..a7b1c09 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -76,6 +76,9 @@ 
 
 2011-11-01  David S. Miller  <davem@davemloft.net>
 
+	* config/sparc/sparc.c (vector_init_faligndata): New function.
+	(sparc_expand_vector_init): Use it for V4HImode on VIS1.
+
 	* config/sparc/sparc.c (sparc_expand_vcond): New function.
 	* config/sparc/sparc-protos.h (sparc_expand_vcond): Declare it.
 	* config/sparc/sparc.md (vcond<mode><mode>): New VIS3 expander.
diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c
index 6431405..649612e 100644
--- a/gcc/config/sparc/sparc.c
+++ b/gcc/config/sparc/sparc.c
@@ -11340,6 +11340,25 @@  vector_init_fpmerge (rtx target, rtx elt, enum machine_mode inner_mode)
   emit_insn (gen_fpmerge_vis (gen_lowpart (V8QImode, target), t1, t2));
 }
 
+static void
+vector_init_faligndata (rtx target, rtx elt, enum machine_mode inner_mode)
+{
+  rtx t1 = gen_reg_rtx (V4HImode);
+
+  elt = convert_modes (SImode, inner_mode, elt, true);
+
+  emit_move_insn (gen_lowpart (SImode, t1), elt);
+
+  emit_insn (gen_alignaddrsi_vis (gen_reg_rtx (SImode),
+				  force_reg (SImode, GEN_INT (6)),
+				  CONST0_RTX (SImode)));
+
+  emit_insn (gen_faligndatav4hi_vis (target, t1, target));
+  emit_insn (gen_faligndatav4hi_vis (target, t1, target));
+  emit_insn (gen_faligndatav4hi_vis (target, t1, target));
+  emit_insn (gen_faligndatav4hi_vis (target, t1, target));
+}
+
 void
 sparc_expand_vector_init (rtx target, rtx vals)
 {
@@ -11404,6 +11423,11 @@  sparc_expand_vector_init (rtx target, rtx vals)
 	  vector_init_fpmerge (target, XVECEXP (vals, 0, 0), inner_mode);
 	  return;
 	}
+      if (mode == V4HImode)
+	{
+	  vector_init_faligndata (target, XVECEXP (vals, 0, 0), inner_mode);
+	  return;
+	}
     }
 
   mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);