[v2] monitor: add ability to dump SLB entries

Submitted by Nishanth Aravamudan on Nov. 1, 2011, 7:57 p.m.

Details

Message ID 20111101195752.GA17615@us.ibm.com
State New
Headers show

Commit Message

Nishanth Aravamudan Nov. 1, 2011, 7:57 p.m.
On 31.10.2011 [15:14:12 +1100], David Gibson wrote:
> Good points below.  I forgot to CC Nish, the original patch author on
> my post, so I've added him to the list now.
> 
> Nish, can you correct these problems and resend the patch please?

When run with a PPC Book3S (server) CPU Currently 'info tlb' in the
qemu monitor reports "dump_mmu: unimplemented".  However, during
bringup work, it can be quite handy to have the SLB entries, which are
available in the CPUPPCState.  This patch adds an implementation of
info tlb for book3s, which dumps the SLB.
    
Signed-off-by: Nishanth Aravamudan <nacc@us.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>

---
v2: Update to build on PPC and PPC64 via suggestion from AGraf.

Comments

Alexander Graf Nov. 10, 2011, 5:11 p.m.
On 11/01/2011 08:57 PM, Nishanth Aravamudan wrote:
> On 31.10.2011 [15:14:12 +1100], David Gibson wrote:
>> Good points below.  I forgot to CC Nish, the original patch author on
>> my post, so I've added him to the list now.
>>
>> Nish, can you correct these problems and resend the patch please?
> When run with a PPC Book3S (server) CPU Currently 'info tlb' in the
> qemu monitor reports "dump_mmu: unimplemented".  However, during
> bringup work, it can be quite handy to have the SLB entries, which are
> available in the CPUPPCState.  This patch adds an implementation of
> info tlb for book3s, which dumps the SLB.
>
> Signed-off-by: Nishanth Aravamudan<nacc@us.ibm.com>
> Signed-off-by: David Gibson<david@gibson.dropbear.id.au>

Thanks, applied to ppc-next.


Alex
David Gibson Nov. 14, 2011, 12:40 a.m.
On Thu, Nov 10, 2011 at 06:11:41PM +0100, Alexander Graf wrote:
> On 11/01/2011 08:57 PM, Nishanth Aravamudan wrote:
> >On 31.10.2011 [15:14:12 +1100], David Gibson wrote:
> >>Good points below.  I forgot to CC Nish, the original patch author on
> >>my post, so I've added him to the list now.
> >>
> >>Nish, can you correct these problems and resend the patch please?
> >When run with a PPC Book3S (server) CPU Currently 'info tlb' in the
> >qemu monitor reports "dump_mmu: unimplemented".  However, during
> >bringup work, it can be quite handy to have the SLB entries, which are
> >available in the CPUPPCState.  This patch adds an implementation of
> >info tlb for book3s, which dumps the SLB.
> >
> >Signed-off-by: Nishanth Aravamudan<nacc@us.ibm.com>
> >Signed-off-by: David Gibson<david@gibson.dropbear.id.au>
> 
> Thanks, applied to ppc-next.

I'm guessing that ppc-next is now the branch destined for post 1.0.
Is that right?
Alexander Graf Nov. 14, 2011, 6:25 a.m.
On 14.11.2011, at 01:40, David Gibson <dwg@au1.ibm.com> wrote:

> On Thu, Nov 10, 2011 at 06:11:41PM +0100, Alexander Graf wrote:
>> On 11/01/2011 08:57 PM, Nishanth Aravamudan wrote:
>>> On 31.10.2011 [15:14:12 +1100], David Gibson wrote:
>>>> Good points below.  I forgot to CC Nish, the original patch author on
>>>> my post, so I've added him to the list now.
>>>> 
>>>> Nish, can you correct these problems and resend the patch please?
>>> When run with a PPC Book3S (server) CPU Currently 'info tlb' in the
>>> qemu monitor reports "dump_mmu: unimplemented".  However, during
>>> bringup work, it can be quite handy to have the SLB entries, which are
>>> available in the CPUPPCState.  This patch adds an implementation of
>>> info tlb for book3s, which dumps the SLB.
>>> 
>>> Signed-off-by: Nishanth Aravamudan<nacc@us.ibm.com>
>>> Signed-off-by: David Gibson<david@gibson.dropbear.id.au>
>> 
>> Thanks, applied to ppc-next.
> 
> I'm guessing that ppc-next is now the branch destined for post 1.0.
> Is that right?

Yes :). Please mark 1.0 patches as such so I can cherry-pick them there.

Alex

> 
> -- 
> David Gibson            | I'll have my music baroque, and my code
> david AT gibson.dropbear.id.au    | minimalist, thank you.  NOT _the_ _other_
>                | _way_ _around_!
> http://www.ozlabs.org/~dgibson
>

Patch hide | download patch | download mbox

diff --git a/target-ppc/helper.c b/target-ppc/helper.c
index 137a494..5847453 100644
--- a/target-ppc/helper.c
+++ b/target-ppc/helper.c
@@ -1545,12 +1545,40 @@  static void mmubooke206_dump_mmu(FILE *f, fprintf_function cpu_fprintf,
     }
 }
 
+#if defined(TARGET_PPC64)
+static void mmubooks_dump_mmu(FILE *f, fprintf_function cpu_fprintf,
+                              CPUState *env)
+{
+    int i;
+    uint64_t slbe, slbv;
+
+    cpu_synchronize_state(env);
+
+    cpu_fprintf(f, "SLB\tESID\t\t\tVSID\n");
+    for (i = 0; i < env->slb_nr; i++) {
+        slbe = env->slb[i].esid;
+        slbv = env->slb[i].vsid;
+        if (slbe == 0 && slbv == 0) {
+            continue;
+        }
+        cpu_fprintf(f, "%d\t0x%016" PRIx64 "\t0x%016" PRIx64 "\n",
+                    i, slbe, slbv);
+    }
+}
+#endif
+
 void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUState *env)
 {
     switch (env->mmu_model) {
     case POWERPC_MMU_BOOKE206:
         mmubooke206_dump_mmu(f, cpu_fprintf, env);
         break;
+#if defined(TARGET_PPC64)
+    case POWERPC_MMU_64B:
+    case POWERPC_MMU_2_06:
+        mmubooks_dump_mmu(f, cpu_fprintf, env);
+        break;
+#endif
     default:
         cpu_fprintf(f, "%s: unimplemented\n", __func__);
     }