[U-Boot,v2,3/4] dts: u-boot.dtsi: override flash tx-rx width
diff mbox series

Message ID 1580234527-29280-4-git-send-email-sagar.kadam@sifive.com
State New
Delegated to: Andes
Headers show
Series
  • Fix currently available support for flash on HiFive Unleashed
Related show

Commit Message

Sagar Kadam Jan. 28, 2020, 6:02 p.m. UTC
The hifive-unleashed-a00.dts has flash spi-tx/rx width set
to 4-bit mode. During sf probe, spi_nor_scan fails to read the
JEDEC ID with reg_proto set to SNOR_PROTO_1_1_1. Setting it to
1-bit mode as of now will help read the JEDEC-ID and perform other
flash operations.

Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
---
 arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

Comments

Bin Meng Feb. 4, 2020, 12:13 p.m. UTC | #1
Hi Sagar,

On Wed, Jan 29, 2020 at 2:02 AM Sagar Shrikant Kadam
<sagar.kadam@sifive.com> wrote:
>
> The hifive-unleashed-a00.dts has flash spi-tx/rx width set
> to 4-bit mode. During sf probe, spi_nor_scan fails to read the
> JEDEC ID with reg_proto set to SNOR_PROTO_1_1_1. Setting it to
> 1-bit mode as of now will help read the JEDEC-ID and perform other
> flash operations.

So previously with Jagan's series that did not have these changes in
this commit, the flash driver worked well. I wonder what real issue
was fixed in this commit?

>
> Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
> ---
>  arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi | 8 ++++++++
>  1 file changed, 8 insertions(+)
>
> diff --git a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
> index d7a6413..dae9f87 100644
> --- a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
> +++ b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
> @@ -9,3 +9,11 @@
>                 spi2 = &qspi2;
>         };
>  };
> +
> +&qspi0 {
> +       flash@0 {
> +               spi-tx-bus-width = <1>;
> +               spi-rx-bus-width = <1>;
> +       };
> +};
> +

Regards,
Bin
Sagar Kadam Feb. 6, 2020, 6:43 p.m. UTC | #2
Hello Bin,

> -----Original Message-----
> From: Bin Meng <bmeng.cn@gmail.com>
> Sent: Tuesday, February 4, 2020 5:43 PM
> To: Sagar Kadam <sagar.kadam@sifive.com>
> Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Rick Chen
> <rick@andestech.com>; Paul Walmsley ( Sifive) <paul.walmsley@sifive.com>;
> Jagan Teki <jagan@amarulasolutions.com>; Anup Patel
> <anup.patel@wdc.com>
> Subject: Re: [U-Boot Patch v2 3/4] dts: u-boot.dtsi: override flash tx-rx width
> 
> Hi Sagar,
> 
> On Wed, Jan 29, 2020 at 2:02 AM Sagar Shrikant Kadam
> <sagar.kadam@sifive.com> wrote:
> >
> > The hifive-unleashed-a00.dts has flash spi-tx/rx width set to 4-bit
> > mode. During sf probe, spi_nor_scan fails to read the JEDEC ID with
> > reg_proto set to SNOR_PROTO_1_1_1. Setting it to 1-bit mode as of now
> > will help read the JEDEC-ID and perform other flash operations.
> 
> So previously with Jagan's series that did not have these changes in this
> commit, the flash driver worked well. I wonder what real issue was fixed in
> this commit?
> 
Yes true, I had observed that flash device was working with Jagan's series 
you are indicating here. The flash device was getting probed at cs 2/4/6/8 etc..
but it couldn't get detected on CS0 which is actually connected on the board 
to the flash device. 
With the check of spi->num_cs done in patch 2 of this series or the one handled
in commit 7bacce524d48 ("dm: spi: Check cs number before accessing slaves") 
invalid chip select is taken care of and flash is not detected on wrong chip selects,
but spi transfer still fails as the sifive-spi driver set's the SIFIVE_SPI_FMT_PROTO_QUAD
mode based on device tree information. While reading Device ID in spi_nor_scan the
reg proto is set to 1_1_1 bit mode and this contradicts here in the driver due to which
spi_nor_scan fails, due to which one cannot use the flash. 
So for now I have added this override here to 1 bit mode so that users can use it. 
Maybe I will update the commit message to indicate that this is workaround for a bug
in SPI driver for FU540 which currently is not able to handle QUAD mode operation.
Please let me know your views here.

Thanks & BR,
Sagar 
> >
> > Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
> > ---
> >  arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi | 8 ++++++++
> >  1 file changed, 8 insertions(+)
> >
> > diff --git a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
> > b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
> > index d7a6413..dae9f87 100644
> > --- a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
> > +++ b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
> > @@ -9,3 +9,11 @@
> >                 spi2 = &qspi2;
> >         };
> >  };
> > +
> > +&qspi0 {
> > +       flash@0 {
> > +               spi-tx-bus-width = <1>;
> > +               spi-rx-bus-width = <1>;
> > +       };
> > +};
> > +
> 
> Regards,
> Bin
Bin Meng Feb. 19, 2020, 4:28 p.m. UTC | #3
Hi Sagar,

On Fri, Feb 7, 2020 at 2:43 AM Sagar Kadam <sagar.kadam@sifive.com> wrote:
>
> Hello Bin,
>
> > -----Original Message-----
> > From: Bin Meng <bmeng.cn@gmail.com>
> > Sent: Tuesday, February 4, 2020 5:43 PM
> > To: Sagar Kadam <sagar.kadam@sifive.com>
> > Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Rick Chen
> > <rick@andestech.com>; Paul Walmsley ( Sifive) <paul.walmsley@sifive.com>;
> > Jagan Teki <jagan@amarulasolutions.com>; Anup Patel
> > <anup.patel@wdc.com>
> > Subject: Re: [U-Boot Patch v2 3/4] dts: u-boot.dtsi: override flash tx-rx width
> >
> > Hi Sagar,
> >
> > On Wed, Jan 29, 2020 at 2:02 AM Sagar Shrikant Kadam
> > <sagar.kadam@sifive.com> wrote:
> > >
> > > The hifive-unleashed-a00.dts has flash spi-tx/rx width set to 4-bit
> > > mode. During sf probe, spi_nor_scan fails to read the JEDEC ID with
> > > reg_proto set to SNOR_PROTO_1_1_1. Setting it to 1-bit mode as of now
> > > will help read the JEDEC-ID and perform other flash operations.
> >
> > So previously with Jagan's series that did not have these changes in this
> > commit, the flash driver worked well. I wonder what real issue was fixed in
> > this commit?
> >
> Yes true, I had observed that flash device was working with Jagan's series
> you are indicating here. The flash device was getting probed at cs 2/4/6/8 etc..
> but it couldn't get detected on CS0 which is actually connected on the board
> to the flash device.
> With the check of spi->num_cs done in patch 2 of this series or the one handled
> in commit 7bacce524d48 ("dm: spi: Check cs number before accessing slaves")
> invalid chip select is taken care of and flash is not detected on wrong chip selects,
> but spi transfer still fails as the sifive-spi driver set's the SIFIVE_SPI_FMT_PROTO_QUAD
> mode based on device tree information. While reading Device ID in spi_nor_scan the
> reg proto is set to 1_1_1 bit mode and this contradicts here in the driver due to which
> spi_nor_scan fails, due to which one cannot use the flash.
> So for now I have added this override here to 1 bit mode so that users can use it.
> Maybe I will update the commit message to indicate that this is workaround for a bug
> in SPI driver for FU540 which currently is not able to handle QUAD mode operation.
> Please let me know your views here.
>

Thanks for the details. Based on your description, I think there is
something wrong with the SPI-NOR driver. Your change to 1 line only
seems to be a workaround.

Jagan, would you please comment?

Regards,
Bin

Patch
diff mbox series

diff --git a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
index d7a6413..dae9f87 100644
--- a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
+++ b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
@@ -9,3 +9,11 @@ 
 		spi2 = &qspi2;
 	};
 };
+
+&qspi0 {
+	flash@0 {
+		spi-tx-bus-width = <1>;
+		spi-rx-bus-width = <1>;
+	};
+};
+