From patchwork Tue Jan 28 00:46:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 1230103 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=arm.com Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4867JH4KGnz9sP3 for ; Tue, 28 Jan 2020 11:47:59 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 41237819E6; Tue, 28 Jan 2020 01:47:30 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id D56AA819E6; Tue, 28 Jan 2020 01:47:20 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=SPF_HELO_NONE, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.2 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by phobos.denx.de (Postfix) with ESMTP id 1E07A81943 for ; Tue, 28 Jan 2020 01:47:17 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=andre.przywara@arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2E66E30E; Mon, 27 Jan 2020 16:47:16 -0800 (PST) Received: from localhost.localdomain (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 196E13F67D; Mon, 27 Jan 2020 16:47:13 -0800 (PST) From: Andre Przywara To: Maxime Ripard , Jagan Teki Subject: [PATCH v2 3/5] sunxi: SPL SPI: Add SPI boot support for the Allwinner R40 SoC Date: Tue, 28 Jan 2020 00:46:42 +0000 Message-Id: <20200128004644.21341-4-andre.przywara@arm.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20200128004644.21341-1-andre.przywara@arm.com> References: <20200128004644.21341-1-andre.przywara@arm.com> X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.26 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Olliver Schinagl , Hauke Mehrtens , u-boot@lists.denx.de, linux-sunxi@googlegroups.com, Icenowy Zheng Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.101.4 at phobos.denx.de X-Virus-Status: Clean Now that we can easily select an SoC specific SPI0 base address, adding support for the Allwinner R40 is fairly trivial: We set the base address, add this SoC to the ones that use PC23 and enable it in Kconfig. This allows booting from SPI flash on R40 boards. Tested on a Bananapi M2 Berry with SPI flash connected to the header pins. Signed-off-by: Andre Przywara --- arch/arm/mach-sunxi/Kconfig | 2 +- arch/arm/mach-sunxi/spl_spi_sunxi.c | 6 +++++- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 3a3b673430..eb046160e6 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -994,7 +994,7 @@ config SPL_STACK_R_ADDR config SPL_SPI_SUNXI bool "Support for SPI Flash on Allwinner SoCs in SPL" - depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I + depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 help Enable support for SPI Flash. This option allows SPL to read from sunxi SPI Flash. It uses the same method as the boot ROM, so does diff --git a/arch/arm/mach-sunxi/spl_spi_sunxi.c b/arch/arm/mach-sunxi/spl_spi_sunxi.c index cab6affe8d..357953cfce 100644 --- a/arch/arm/mach-sunxi/spl_spi_sunxi.c +++ b/arch/arm/mach-sunxi/spl_spi_sunxi.c @@ -94,7 +94,8 @@ static void spi0_pinmux_setup(unsigned int pin_function) for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(2); pin++) sunxi_gpio_set_cfgpin(pin, pin_function); - if (IS_ENABLED(CONFIG_MACH_SUN4I) || IS_ENABLED(CONFIG_MACH_SUN7I)) + if (IS_ENABLED(CONFIG_MACH_SUN4I) || IS_ENABLED(CONFIG_MACH_SUN7I) || + IS_ENABLED(CONFIG_MACH_SUN8I_R40)) sunxi_gpio_set_cfgpin(SUNXI_GPC(23), pin_function); else sunxi_gpio_set_cfgpin(SUNXI_GPC(3), pin_function); @@ -107,6 +108,9 @@ static bool is_sun6i_gen_spi(void) static uintptr_t spi0_base_address(void) { + if (IS_ENABLED(CONFIG_MACH_SUN8I_R40)) + return 0x01C05000; + if (!is_sun6i_gen_spi()) return 0x01C05000;