diff mbox

Allow zero operand in sparc VIS3 cmask patterns.

Message ID 20111031.181017.349760937366198500.davem@davemloft.net
State New
Headers show

Commit Message

David Miller Oct. 31, 2011, 10:10 p.m. UTC 
I noticed this while working on vcond patterns for sparc.

Committed to trunk.

gcc/

	* config/sparc/sparc.md (cmask patterns): Allow zero operand.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@180715 138bc75d-0d04-0410-961f-82ee72b054a4
---
 gcc/ChangeLog             |    2 ++
 gcc/config/sparc/sparc.md |    6 +++---
 2 files changed, 5 insertions(+), 3 deletions(-)
diff mbox

Patch

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 4848147..ebf8cdc 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,7 @@ 
 2011-10-31  David S. Miller  <davem@davemloft.net>
 
+	* config/sparc/sparc.md (cmask patterns): Allow zero operand.
+
 	* dwarf2out.c (cached_next_real_insn): New.
 	(dwarf2out_end_epilogue): Set it to NULL_RTX.
 	(dwarf2out_var_location): Remove cached_next_real_insn local static.
diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md
index 6dd3909..fbd1a87 100644
--- a/gcc/config/sparc/sparc.md
+++ b/gcc/config/sparc/sparc.md
@@ -8452,7 +8452,7 @@ 
 ;; Conditional moves are possible via fcmpX --> cmaskX -> bshuffle
 (define_insn "cmask8<P:mode>_vis"
   [(set (reg:DI GSR_REG)
-        (unspec:DI [(match_operand:P 0 "register_operand" "r")
+        (unspec:DI [(match_operand:P 0 "register_or_zero_operand" "rJ")
 	            (reg:DI GSR_REG)]
                    UNSPEC_CMASK8))]
   "TARGET_VIS3"
@@ -8460,7 +8460,7 @@ 
 
 (define_insn "cmask16<P:mode>_vis"
   [(set (reg:DI GSR_REG)
-        (unspec:DI [(match_operand:P 0 "register_operand" "r")
+        (unspec:DI [(match_operand:P 0 "register_or_zero_operand" "rJ")
 	            (reg:DI GSR_REG)]
                    UNSPEC_CMASK16))]
   "TARGET_VIS3"
@@ -8468,7 +8468,7 @@ 
 
 (define_insn "cmask32<P:mode>_vis"
   [(set (reg:DI GSR_REG)
-        (unspec:DI [(match_operand:P 0 "register_operand" "r")
+        (unspec:DI [(match_operand:P 0 "register_or_zero_operand" "rJ")
 	            (reg:DI GSR_REG)]
                    UNSPEC_CMASK32))]
   "TARGET_VIS3"