From patchwork Mon Jan 27 12:20:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cornelia Huck X-Patchwork-Id: 1229736 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=redhat.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=redhat.com header.i=@redhat.com header.a=rsa-sha256 header.s=mimecast20190719 header.b=FCiMVP2J; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 485prs2dhKz9sSD for ; Mon, 27 Jan 2020 23:26:37 +1100 (AEDT) Received: from localhost ([::1]:44162 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iw3TP-0001RC-Ch for incoming@patchwork.ozlabs.org; Mon, 27 Jan 2020 07:26:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:35469) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iw3OE-0000jN-0E for qemu-devel@nongnu.org; Mon, 27 Jan 2020 07:21:15 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iw3O6-0006tD-RC for qemu-devel@nongnu.org; Mon, 27 Jan 2020 07:21:13 -0500 Received: from us-smtp-delivery-1.mimecast.com ([207.211.31.120]:20088 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iw3O6-0006se-ME for qemu-devel@nongnu.org; Mon, 27 Jan 2020 07:21:06 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1580127666; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=S3Q48Cgu0nCAAaVqjqrUVHb5nNmpYROWKK2lQRQnhVs=; b=FCiMVP2JpvrkaNmkC7YxgJ87aQINFZIUHqBk+O2R4b6nWrjO4BDDv+Qyqsv2GA9aYBbNFw 9ybQHWwuTV825BEEDneI5fTpLlxMOVqgZ5tMxAB5cgZ3s3lrucI7Kc19n2pyimUh/AgfWj BooQ/8hONftPfusjae+LMJwROMG/HSk= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-249-mbQNZJ6BOnioo-zkYD0YzQ-1; Mon, 27 Jan 2020 07:21:01 -0500 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 98A948017CC; Mon, 27 Jan 2020 12:21:00 +0000 (UTC) Received: from localhost (ovpn-116-220.ams2.redhat.com [10.36.116.220]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 10B715DC1E; Mon, 27 Jan 2020 12:20:59 +0000 (UTC) From: Cornelia Huck To: Peter Maydell Subject: [PULL 12/15] target/s390x: Move DisasFields into DisasContext Date: Mon, 27 Jan 2020 13:20:13 +0100 Message-Id: <20200127122016.18752-13-cohuck@redhat.com> In-Reply-To: <20200127122016.18752-1-cohuck@redhat.com> References: <20200127122016.18752-1-cohuck@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-MC-Unique: mbQNZJ6BOnioo-zkYD0YzQ-1 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 207.211.31.120 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , qemu-s390x@nongnu.org, Cornelia Huck , Richard Henderson , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson I believe that the separate allocation of DisasFields from DisasContext was meant to limit the places from which we could access fields. But that plan did not go unchanged, and since DisasContext contains a pointer to fields, the substructure is accessible everywhere. By allocating the substructure with DisasContext, we improve the locality of the accesses by avoiding one level of pointer chasing. In addition, we avoid a dangling pointer to stack allocated memory, diagnosed by static checkers. Launchpad: https://bugs.launchpad.net/bugs/1661815 Signed-off-by: Richard Henderson Message-Id: <20200123232248.1800-5-richard.henderson@linaro.org> Reviewed-by: Thomas Huth Signed-off-by: Cornelia Huck --- target/s390x/translate.c | 22 +++++++++--------- target/s390x/translate_vx.inc.c | 40 ++++++++++++++++----------------- 2 files changed, 30 insertions(+), 32 deletions(-) diff --git a/target/s390x/translate.c b/target/s390x/translate.c index 51a1d865c04e..3674fee10c83 100644 --- a/target/s390x/translate.c +++ b/target/s390x/translate.c @@ -139,7 +139,7 @@ struct DisasFields { struct DisasContext { DisasContextBase base; const DisasInsn *insn; - DisasFields *fields; + DisasFields fields; uint64_t ex_value; /* * During translate_one(), pc_tmp is used to determine the instruction @@ -1094,14 +1094,14 @@ typedef enum { static bool have_field1(const DisasContext *s, enum DisasFieldIndexO c) { - return (s->fields->presentO >> c) & 1; + return (s->fields.presentO >> c) & 1; } static int get_field1(const DisasContext *s, enum DisasFieldIndexO o, enum DisasFieldIndexC c) { assert(have_field1(s, o)); - return s->fields->c[c]; + return s->fields.c[c]; } /* Describe the layout of each field in each format. */ @@ -3763,7 +3763,7 @@ static DisasJumpType op_risbg(DisasContext *s, DisasOps *o) int pos, len, rot; /* Adjust the arguments for the specific insn. */ - switch (s->fields->op2) { + switch (s->fields.op2) { case 0x55: /* risbg */ case 0x59: /* risbgn */ i3 &= 63; @@ -3804,7 +3804,7 @@ static DisasJumpType op_risbg(DisasContext *s, DisasOps *o) len = i4 - i3 + 1; pos = 63 - i4; rot = i5 & 63; - if (s->fields->op2 == 0x5d) { + if (s->fields.op2 == 0x5d) { pos += 32; } @@ -3873,7 +3873,7 @@ static DisasJumpType op_rosbg(DisasContext *s, DisasOps *o) tcg_gen_rotli_i64(o->in2, o->in2, i5); /* Operate. */ - switch (s->fields->op2) { + switch (s->fields.op2) { case 0x55: /* AND */ tcg_gen_ori_i64(o->in2, o->in2, ~mask); tcg_gen_and_i64(o->out, o->out, o->in2); @@ -4489,7 +4489,7 @@ static DisasJumpType op_stnosm(DisasContext *s, DisasOps *o) tcg_gen_qemu_st8(t, o->addr1, get_mem_index(s)); tcg_temp_free_i64(t); - if (s->fields->op == 0xac) { + if (s->fields.op == 0xac) { tcg_gen_andi_i64(psw_mask, psw_mask, (i2 << 56) | 0x00ffffffffffffffull); } else { @@ -6000,7 +6000,7 @@ static void in2_i2_32u_shl(DisasContext *s, DisasOps *o) #ifndef CONFIG_USER_ONLY static void in2_insn(DisasContext *s, DisasOps *o) { - o->in2 = tcg_const_i64(s->fields->raw_insn); + o->in2 = tcg_const_i64(s->fields.raw_insn); } #define SPEC_in2_insn 0 #endif @@ -6299,15 +6299,13 @@ static DisasJumpType translate_one(CPUS390XState *env, DisasContext *s) { const DisasInsn *insn; DisasJumpType ret = DISAS_NEXT; - DisasFields f; DisasOps o = {}; /* Search for the insn in the table. */ - insn = extract_insn(env, s, &f); + insn = extract_insn(env, s, &s->fields); /* Set up the strutures we use to communicate with the helpers. */ s->insn = insn; - s->fields = &f; /* Emit insn_start now that we know the ILEN. */ tcg_gen_insn_start(s->base.pc_next, s->cc_op, s->ilen); @@ -6315,7 +6313,7 @@ static DisasJumpType translate_one(CPUS390XState *env, DisasContext *s) /* Not found means unimplemented/illegal opcode. */ if (insn == NULL) { qemu_log_mask(LOG_UNIMP, "unimplemented opcode 0x%02x%02x\n", - f.op, f.op2); + s->fields.op, s->fields.op2); gen_illegal_opcode(s); return DISAS_NORETURN; } diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c index e1a2d25c2fa4..24558cce8070 100644 --- a/target/s390x/translate_vx.inc.c +++ b/target/s390x/translate_vx.inc.c @@ -732,7 +732,7 @@ static DisasJumpType op_vmr(DisasContext *s, DisasOps *o) } tmp = tcg_temp_new_i64(); - if (s->fields->op2 == 0x61) { + if (s->fields.op2 == 0x61) { /* iterate backwards to avoid overwriting data we might need later */ for (dst_idx = NUM_VEC_ELEMENTS(es) - 1; dst_idx >= 0; dst_idx--) { src_idx = dst_idx / 2; @@ -796,7 +796,7 @@ static DisasJumpType op_vpk(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } - switch (s->fields->op2) { + switch (s->fields.op2) { case 0x97: if (get_field(s, m5) & 0x1) { gen_gvec_3_ptr(v1, v2, v3, cpu_env, 0, vpks_cc[es - 1]); @@ -1038,7 +1038,7 @@ static DisasJumpType op_vstl(DisasContext *s, DisasOps *o) static DisasJumpType op_vup(DisasContext *s, DisasOps *o) { - const bool logical = s->fields->op2 == 0xd4 || s->fields->op2 == 0xd5; + const bool logical = s->fields.op2 == 0xd4 || s->fields.op2 == 0xd5; const uint8_t v1 = get_field(s, v1); const uint8_t v2 = get_field(s, v2); const uint8_t src_es = get_field(s, m3); @@ -1052,7 +1052,7 @@ static DisasJumpType op_vup(DisasContext *s, DisasOps *o) } tmp = tcg_temp_new_i64(); - if (s->fields->op2 == 0xd7 || s->fields->op2 == 0xd5) { + if (s->fields.op2 == 0xd7 || s->fields.op2 == 0xd5) { /* iterate backwards to avoid overwriting data we might need later */ for (dst_idx = NUM_VEC_ELEMENTS(dst_es) - 1; dst_idx >= 0; dst_idx--) { src_idx = dst_idx; @@ -1389,7 +1389,7 @@ static DisasJumpType op_vec(DisasContext *s, DisasOps *o) gen_program_exception(s, PGM_SPECIFICATION); return DISAS_NORETURN; } - if (s->fields->op2 == 0xdb) { + if (s->fields.op2 == 0xdb) { es |= MO_SIGN; } @@ -1567,7 +1567,7 @@ static DisasJumpType op_vmx(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } - switch (s->fields->op2) { + switch (s->fields.op2) { case 0xff: gen_gvec_fn_3(smax, es, v1, v2, v3); break; @@ -1677,7 +1677,7 @@ static DisasJumpType op_vma(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } - switch (s->fields->op2) { + switch (s->fields.op2) { case 0xaa: fn = &g_vmal[es]; break; @@ -1764,7 +1764,7 @@ static DisasJumpType op_vm(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } - switch (s->fields->op2) { + switch (s->fields.op2) { case 0xa2: gen_gvec_fn_3(mul, es, get_field(s, v1), get_field(s, v2), get_field(s, v3)); @@ -1967,7 +1967,7 @@ static DisasJumpType op_vesv(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } - switch (s->fields->op2) { + switch (s->fields.op2) { case 0x70: gen_gvec_fn_3(shlv, es, v1, v2, v3); break; @@ -1998,7 +1998,7 @@ static DisasJumpType op_ves(DisasContext *s, DisasOps *o) } if (likely(!get_field(s, b2))) { - switch (s->fields->op2) { + switch (s->fields.op2) { case 0x30: gen_gvec_fn_2i(shli, es, v1, v3, d2); break; @@ -2015,7 +2015,7 @@ static DisasJumpType op_ves(DisasContext *s, DisasOps *o) shift = tcg_temp_new_i32(); tcg_gen_extrl_i64_i32(shift, o->addr1); tcg_gen_andi_i32(shift, shift, NUM_VEC_ELEMENT_BITS(es) - 1); - switch (s->fields->op2) { + switch (s->fields.op2) { case 0x30: gen_gvec_fn_2s(shls, es, v1, v3, shift); break; @@ -2038,7 +2038,7 @@ static DisasJumpType op_vsl(DisasContext *s, DisasOps *o) TCGv_i64 shift = tcg_temp_new_i64(); read_vec_element_i64(shift, get_field(s, v3), 7, ES_8); - if (s->fields->op2 == 0x74) { + if (s->fields.op2 == 0x74) { tcg_gen_andi_i64(shift, shift, 0x7); } else { tcg_gen_andi_i64(shift, shift, 0x78); @@ -2084,7 +2084,7 @@ static DisasJumpType op_vsra(DisasContext *s, DisasOps *o) TCGv_i64 shift = tcg_temp_new_i64(); read_vec_element_i64(shift, get_field(s, v3), 7, ES_8); - if (s->fields->op2 == 0x7e) { + if (s->fields.op2 == 0x7e) { tcg_gen_andi_i64(shift, shift, 0x7); } else { tcg_gen_andi_i64(shift, shift, 0x78); @@ -2101,7 +2101,7 @@ static DisasJumpType op_vsrl(DisasContext *s, DisasOps *o) TCGv_i64 shift = tcg_temp_new_i64(); read_vec_element_i64(shift, get_field(s, v3), 7, ES_8); - if (s->fields->op2 == 0x7c) { + if (s->fields.op2 == 0x7c) { tcg_gen_andi_i64(shift, shift, 0x7); } else { tcg_gen_andi_i64(shift, shift, 0x78); @@ -2524,7 +2524,7 @@ static DisasJumpType op_vfa(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } - switch (s->fields->op2) { + switch (s->fields.op2) { case 0xe3: fn = se ? gen_helper_gvec_vfa64s : gen_helper_gvec_vfa64; break; @@ -2555,7 +2555,7 @@ static DisasJumpType op_wfc(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } - if (s->fields->op2 == 0xcb) { + if (s->fields.op2 == 0xcb) { gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2), cpu_env, 0, gen_helper_gvec_wfc64); } else { @@ -2581,7 +2581,7 @@ static DisasJumpType op_vfc(DisasContext *s, DisasOps *o) } if (cs) { - switch (s->fields->op2) { + switch (s->fields.op2) { case 0xe8: fn = se ? gen_helper_gvec_vfce64s_cc : gen_helper_gvec_vfce64_cc; break; @@ -2595,7 +2595,7 @@ static DisasJumpType op_vfc(DisasContext *s, DisasOps *o) g_assert_not_reached(); } } else { - switch (s->fields->op2) { + switch (s->fields.op2) { case 0xe8: fn = se ? gen_helper_gvec_vfce64s : gen_helper_gvec_vfce64; break; @@ -2630,7 +2630,7 @@ static DisasJumpType op_vcdg(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } - switch (s->fields->op2) { + switch (s->fields.op2) { case 0xc3: fn = se ? gen_helper_gvec_vcdg64s : gen_helper_gvec_vcdg64; break; @@ -2688,7 +2688,7 @@ static DisasJumpType op_vfma(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } - if (s->fields->op2 == 0x8f) { + if (s->fields.op2 == 0x8f) { fn = se ? gen_helper_gvec_vfma64s : gen_helper_gvec_vfma64; } else { fn = se ? gen_helper_gvec_vfms64s : gen_helper_gvec_vfms64;